TW201234188A - Memory access device for memory sharing among multiple processors and access method for the same - Google Patents
Memory access device for memory sharing among multiple processors and access method for the same Download PDFInfo
- Publication number
- TW201234188A TW201234188A TW100138121A TW100138121A TW201234188A TW 201234188 A TW201234188 A TW 201234188A TW 100138121 A TW100138121 A TW 100138121A TW 100138121 A TW100138121 A TW 100138121A TW 201234188 A TW201234188 A TW 201234188A
- Authority
- TW
- Taiwan
- Prior art keywords
- memory
- access
- cpu
- cpus
- data
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
- G06F13/1663—Access to shared memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/366—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using a centralised polling arbiter
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Information Transfer Systems (AREA)
- Memory System (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010262860 | 2010-11-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201234188A true TW201234188A (en) | 2012-08-16 |
Family
ID=46145677
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100138121A TW201234188A (en) | 2010-11-25 | 2011-10-20 | Memory access device for memory sharing among multiple processors and access method for the same |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US9268721B2 (ja) |
| JP (1) | JP5426036B2 (ja) |
| CN (1) | CN103201725B (ja) |
| DE (1) | DE112011103916B4 (ja) |
| GB (1) | GB2500529B (ja) |
| TW (1) | TW201234188A (ja) |
| WO (1) | WO2012070319A1 (ja) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI671632B (zh) * | 2018-10-24 | 2019-09-11 | 財團法人工業技術研究院 | 記憶體裝置及其復新資訊同步方法 |
| CN115480708A (zh) * | 2022-10-11 | 2022-12-16 | 成都市芯璨科技有限公司 | 一种分时复用局部存储器访问的方法 |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5426036B2 (ja) | 2010-11-25 | 2014-02-26 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 複数のプロセッサのメモリ共有化のためのメモリアクセス装置、及びそのアクセス方法 |
| US9208002B2 (en) | 2012-01-06 | 2015-12-08 | International Business Machines Corporation | Equalizing bandwidth for multiple requesters using a shared memory system |
| CN103544123A (zh) * | 2012-07-16 | 2014-01-29 | 深圳市中兴微电子技术有限公司 | Sdram控制器及对sdram存储空间的访问方法 |
| KR20150018291A (ko) * | 2013-08-09 | 2015-02-23 | 에스케이하이닉스 주식회사 | 메모리 시스템 |
| US9286208B2 (en) * | 2014-02-07 | 2016-03-15 | Kabushiki Kaisha Toshiba | Controller controlling an interleave operation, solid-state drive including the controller, and control method controlling an interleave operation |
| JP5911548B1 (ja) * | 2014-10-23 | 2016-04-27 | インターナショナル・ビジネス・マシーンズ・コーポレーションＩｎｔｅｒｎａｔｉｏｎａｌ Ｂｕｓｉｎｅｓｓ Ｍａｃｈｉｎｅｓ Ｃｏｒｐｏｒａｔｉｏｎ | 共有メモリへのアクセス要求をスケジューリングするための装置、方法およびコンピュータプログラム |
| JP6114767B2 (ja) * | 2015-01-28 | 2017-04-12 | 株式会社東芝 | ブリッジ装置およびその方法、ストレージ装置、ならびにプログラム |
| JP5989818B2 (ja) * | 2015-01-28 | 2016-09-07 | 株式会社東芝 | ブリッジ装置およびその方法、ストレージ装置、ならびにプログラム |
| US10133493B2 (en) * | 2016-03-01 | 2018-11-20 | Marvell World Trade Ltd. | DRAM controller with adaptive precharge policy |
| US10198216B2 (en) * | 2016-05-28 | 2019-02-05 | Advanced Micro Devices, Inc. | Low power memory throttling |
| CN108536619B (zh) * | 2017-03-03 | 2021-12-14 | 北京忆恒创源科技股份有限公司 | 快速恢复ftl表的方法与装置 |
| US10628057B2 (en) * | 2017-03-28 | 2020-04-21 | Hewlett Packard Enterprise Development Lp | Capability based locking and access of shared persistent memory |
| JP6890055B2 (ja) * | 2017-06-30 | 2021-06-18 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| KR102499255B1 (ko) * | 2018-02-19 | 2023-02-13 | 에스케이하이닉스 주식회사 | 통합 메모리 디바이스 및 그의 동작 방법 |
| US11544168B2 (en) | 2017-10-30 | 2023-01-03 | SK Hynix Inc. | Memory system |
| US10714159B2 (en) * | 2018-05-09 | 2020-07-14 | Micron Technology, Inc. | Indication in memory system or sub-system of latency associated with performing an access command |
| JP7018833B2 (ja) * | 2018-06-22 | 2022-02-14 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| CN110688331B (zh) * | 2018-07-05 | 2021-08-17 | 珠海全志科技股份有限公司 | 一种SoC芯片及读取数据的方法 |
| CN109582226A (zh) * | 2018-11-14 | 2019-04-05 | 北京中电华大电子设计有限责任公司 | 一种高速存储访问逻辑结构及其控制方法 |
| JP7142562B2 (ja) * | 2018-12-25 | 2022-09-27 | ルネサスエレクトロニクス株式会社 | 半導体装置、および、データのアクセスを制御するための方法 |
| JP7381603B2 (ja) * | 2019-12-05 | 2023-11-15 | オリンパス株式会社 | データ転送装置およびデータ転送方法 |
| CN113835673B (zh) * | 2021-09-24 | 2023-08-11 | 苏州睿芯集成电路科技有限公司 | 一种用于降低多核处理器加载延时的方法、系统及装置 |
| CN115225592B (zh) * | 2022-06-01 | 2024-01-12 | 裕太微(上海)电子有限公司 | 一种直接存储器访问数据传输方法及系统 |
| CN116521096B (zh) * | 2023-07-03 | 2023-09-22 | 摩尔线程智能科技(北京)有限责任公司 | 存储器访问电路及存储器访问方法、集成电路和电子设备 |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3317150B2 (ja) | 1996-07-29 | 2002-08-26 | 日本電気株式会社 | 情報処理装置 |
| US6182177B1 (en) * | 1997-06-13 | 2001-01-30 | Intel Corporation | Method and apparatus for maintaining one or more queues of elements such as commands using one or more token queues |
| JPH11120124A (ja) | 1997-10-14 | 1999-04-30 | Toshiba Corp | バスアクセス装置、バス調停システム、ｃｄ−ｒｏｍデコーダ、ｄｖｄ−ｒｏｍデコーダ及びｃｄ−ｒｏｍドライブ |
| JP3999943B2 (ja) * | 2001-03-13 | 2007-10-31 | 株式会社東芝 | マルチバンクアクセス制御装置及びマルチバンクアクセス制御方法 |
| US20060059319A1 (en) | 2002-04-04 | 2006-03-16 | Rudi Frenzel | Architecture with shared memory |
| JP2006099731A (ja) * | 2004-08-30 | 2006-04-13 | Matsushita Electric Ind Co Ltd | リソース管理装置 |
| GB2430053B (en) | 2005-09-08 | 2010-09-22 | Advanced Risc Mach Ltd | Accessing external memory from an integrated circuit |
| US8065459B2 (en) | 2006-05-17 | 2011-11-22 | Nxp B.V. | Multi-processing system and a method of executing a plurality of data processing tasks |
| US20080082707A1 (en) | 2006-09-29 | 2008-04-03 | Synfora, Inc. | Non-blocking bus controller for a pipelined, variable latency, hierarchical bus with point-to-point first-in first-out ordering |
| US8285895B2 (en) | 2007-08-06 | 2012-10-09 | Winbond Electronics Corporation | Handshake free sharing in a computer architecture |
| US7861041B2 (en) | 2007-09-04 | 2010-12-28 | Advanced Micro Devices, Inc. | Second chance replacement mechanism for a highly associative cache memory of a processor |
| WO2010073776A1 (ja) | 2008-12-25 | 2010-07-01 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 記録媒体に記録されたデータを読み出す装置及び方法 |
| JP5426036B2 (ja) | 2010-11-25 | 2014-02-26 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 複数のプロセッサのメモリ共有化のためのメモリアクセス装置、及びそのアクセス方法 |
-
2011
- 2011-10-06 JP JP2012545649A patent/JP5426036B2/ja active Active
- 2011-10-06 CN CN201180051349.2A patent/CN103201725B/zh active Active
- 2011-10-06 WO PCT/JP2011/073053 patent/WO2012070319A1/ja active Application Filing
- 2011-10-06 US US13/989,743 patent/US9268721B2/en not_active Expired - Fee Related
- 2011-10-06 GB GB1311026.7A patent/GB2500529B/en active Active
- 2011-10-06 DE DE112011103916.6T patent/DE112011103916B4/de active Active
- 2011-10-20 TW TW100138121A patent/TW201234188A/zh unknown
-
2016
- 2016-01-15 US US14/997,151 patent/US9460763B2/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI671632B (zh) * | 2018-10-24 | 2019-09-11 | 財團法人工業技術研究院 | 記憶體裝置及其復新資訊同步方法 |
| US10692558B2 (en) | 2018-10-24 | 2020-06-23 | Industrial Technology Research Institute | Memory device and refresh information coherence method thereof |
| CN115480708A (zh) * | 2022-10-11 | 2022-12-16 | 成都市芯璨科技有限公司 | 一种分时复用局部存储器访问的方法 |
| CN115480708B (zh) * | 2022-10-11 | 2023-02-28 | 成都市芯璨科技有限公司 | 一种分时复用局部存储器访问的方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2012070319A1 (ja) | 2012-05-31 |
| US20140059286A1 (en) | 2014-02-27 |
| DE112011103916T5 (de) | 2013-10-10 |
| CN103201725B (zh) | 2015-12-09 |
| CN103201725A (zh) | 2013-07-10 |
| JPWO2012070319A1 (ja) | 2014-05-19 |
| GB201311026D0 (en) | 2013-08-07 |
| US20160211006A1 (en) | 2016-07-21 |
| GB2500529A (en) | 2013-09-25 |
| DE112011103916B4 (de) | 2021-11-25 |
| GB2500529B (en) | 2020-03-25 |
| US9460763B2 (en) | 2016-10-04 |
| US9268721B2 (en) | 2016-02-23 |
| JP5426036B2 (ja) | 2014-02-26 |
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