TW201227915A - Wafer level molding structure and manufacturing method thereof - Google Patents

Wafer level molding structure and manufacturing method thereof Download PDF

Info

Publication number
TW201227915A
TW201227915A TW099146766A TW99146766A TW201227915A TW 201227915 A TW201227915 A TW 201227915A TW 099146766 A TW099146766 A TW 099146766A TW 99146766 A TW99146766 A TW 99146766A TW 201227915 A TW201227915 A TW 201227915A
Authority
TW
Taiwan
Prior art keywords
wafer
crystal
layer
bumps
conductive layer
Prior art date
Application number
TW099146766A
Other languages
English (en)
Other versions
TWI496271B (zh
Inventor
Su-Tsai Lu
Jing-Ye Juang
Yu-Min Lin
Original Assignee
Ind Tech Res Inst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ind Tech Res Inst filed Critical Ind Tech Res Inst
Priority to US12/981,475 priority Critical patent/US8384215B2/en
Priority to TW099146766A priority patent/TWI496271B/zh
Priority to CN2011100342880A priority patent/CN102543969A/zh
Publication of TW201227915A publication Critical patent/TW201227915A/zh
Application granted granted Critical
Publication of TWI496271B publication Critical patent/TWI496271B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2741—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2743—Manufacturing methods by blanket deposition of the material of the layer connector in solid form
    • H01L2224/27436—Lamination of a preform, e.g. foil, sheet or layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73151—Location prior to the connecting process on different surfaces
    • H01L2224/73153—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

201227915 P51990111TW 36210twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶圓級模封接合結構及其製造 方法。 【先前技術】 利用三維(Three Dimension，3D)積體電路(ic)整合技 術提供高密度晶片構裝技術並達成高效率及低耗能，為目 前最有希望解決未來大型晶片運作之方案之一。尤其在中 央處理器（CPU)、快取記憶體、以及記憶卡應用中的快閃 s己憶體(Flash)與控制器（Controller)間資料的傳輸上，更能 突顯石夕晶片穿孔内部互連(through-silicon-via，TSV)的短距 離内部接合路徑所帶來的效能優勢。 因此’在強調多功能、小尺寸的可攜式電子產品領 域，如固態硬碟(Solid State Disk，SSD)和動態隨機存取記 憶體(DRAM)等等新設計的堆疊結構，除可強化應用所強 調的高速效能表現’亦可對晶片功耗的部份有所助益。在 同樣的輸入/輸出（I/O)數目下，可以降低驅動所需的功粍， 同步解決容量、效能與I/O提高的需求。此外，3D晶片的 小型化特性更是市場導入的首要因素，現今3D晶片整合 技術的主軸技術包含石夕晶片穿孔内部互連 (Through-silicon-via, TSV)、微凸塊(Micro Bump)接點製 作、晶圓薄化(Wafer Thinning)、對準(Alignment)、接合 (Bonding)及點膠製程的建立。 由於晶圓/晶圓對接技術(wafer-on-wafer, WOW)仍有 201227915 P51990111TW 36210twf.doc/n 晶片良率(known good dies，KGD)不足的問題，導致整體構 裝之良率無法改善。因此，採用晶片/晶片接合技術 (Chip-to-Chip ’ COC)及晶片/晶圓接合技術
(Chip-to-Wafer’COW)以解決此問題，如何在COC及COW 製程技術上大量的組裝並堆疊KGDs，確認接點良率及降 低成本將是考慮的因素。 在目前3D晶片整合技術中，目前堆疊技術朝向1〇微 φ 米（Micr〇meter，μιη)級的間距(Pitch)，以及 50 微米（pm)厚 度以下等級的薄型晶片’為了提高產能與良率，接合技術 亦由晶片/晶片接合技術(COC)逐漸轉向晶片/晶圓接合 (cow)構裝技術，唯如何提高接合良率及降低成本的結構 仍屬重要議題。 如圖1所示，為習知一種使用底膠填充的晶片/晶圓接 合(cow)構裝技術的結構示意圖。晶圓12〇位於載體 (Cairier)100上’並具有一緩衝層u〇位於其間。而多個具 有堆疊的晶片結構112包含三層晶片13〇、140與15〇堆 春 疊’並與晶圓120透過銅凸塊(Cu Bump)或是銅/錫銀微凸 塊（Cu/SnAg Micro Bump)電性接合。而後進行底膠 (Underfill)填充和模封(Molding)製程，完成底膠(Underfm) 層160與模封(Molding)層170。由於堆疊技術朝向1〇微米 (μπι)級的間距(Pitch)以及50微米（μιη)厚度以下等級的薄 型晶片，造成在進行底膠填充後，會產生溢膠的問題，影 響晶片/晶圓接合(cow)構裝技術的良率。 由於必須採用堆疊（Stacking)、填充底膠以及模封 201227915 P51990111T W 36210twf· docAi (Molding)三個步驟’在製程上需要花費較多的時間，增加 製造的成本。而底膠填充和模封製程需要使用不同的材 料，也使成本上增加。另外，由於採用這樣堆疊的晶片結 構，是透過金屬熔接(Metal Joint)以電性連接，在熱膨脹的 不一致(Thermal Expansion Mismatch)，也會造成良率上的 問題。 如圖2所不，為習知另一種使用非流動性底膠 (Non-flow UnderfiU ’ NFU)製程的晶片/晶圓接合(c〇w)構 裝技術的結構示意圖。晶圓220位於載體(Carrier)2〇〇上， 並具有一緩衝層210位於其間。多個具有堆疊的晶片結構 222包含三層晶片230、240與250。此三層晶片23〇、24〇 與250在完成堆疊結構之前’預絲貼—層非流動性底膠 (NFU)232、242、252，並與晶圓 22G 透過銅凸塊(Cu Bump) 或是銅/錫銀微凸塊(Cu/SnAgMicroBump)電性接合。而後 進行模封(Molding)製程，完成模封27°〇。 由於必須採用NFU製程在晶片上黏貼NFU材料，而 後進行堆疊(Stacking)以及模封(M〇lding)#i個步驟，在製 程上需要花費較多的時間，增加製造的成本。而非流動性 底膠(卿)的黏貼與模封製程f要使用不同的材料，也使 成本上增加。另外，由於採料樣堆疊的晶片結構，是透 過金屬熔接_alJolnt)以電性連接，在熱膨服的不一致， 也會造成良率上的問題。 【發明内容】 201227915 P51990111T W 3621 Otwf.doc/n 本發明提供一種晶圓級模封接合結構及其製造方法。 在一實施例中，提出一種模封接合結構，包含一第一 晶片、一第二晶片、多個貫穿電極以及一黏著材料。此第 一晶片包含一第一晶背、一第一晶面和多個第一晶側，而 該第一晶面上有多個第一晶面凸塊。第二晶片包含第二晶 背及第二晶面，其中該第二晶背上包含多個第二晶背凸 塊，該第二晶面上包含多個第二晶面凸塊。該些貫穿電極 位於該第二晶片中，分別電性導通該第二晶背凸塊和該第 二晶面凸塊。該黏著材料置於第一晶片和第二晶片之間， 且完全包覆第一晶片之第一晶側。 在一實施例中，提出一種晶圓級晶片之封裝方法，包 含提供一基板，包含一主動面，其中一第一圖案化導電層 位於主動面。將基板之主動面覆蓋一第一黏著層。提供第 一晶片，包含一第一表面與一第二表面，其中一第二圖案 化導電層位於第一表面。將一緩衝材料層附著於第一晶 片，其中第一晶片之第二表面與緩衝材料層接合。將附著 有緩衝材料層之第一晶片連接至基板，使第一晶片之第二 圖案化導電層與基板之第一圖案化導電層電性連接。使用 附著有緩衝材料層之第一晶片與基板進行一第一壓合過 程，其中緩衝材料層之面積大於第一晶片之第二表面之面 積。第一黏著層完全包覆第一晶片之晶側。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 201227915 P51990111TW 36210twf.doc/n 【實施方式】 為解決晶片/晶圓接合技術(cow)堆疊架構時，底膠 (Underfill)填充和模封(Molding)所遭遇的困難，本案提出 一創新解決方案，同時完成細間距底膠填充和晶圓級模封。 如圖3A所示，為本揭露内容所提出晶圓級的模封接 合結構’在多個實施例其中的一個結構示意圖。晶圓31〇 位於載體(Carrier)300上’並具有一緩衝層302位於其間。 晶圓級模封接合結構304位於晶圓310上，在此實施例中 包含三層晶片320、330與340。在此實施例中以三層結構 說明，但並非以此為限制。而晶片320、330、340的厚度， 在一實施例中’可以小於或等於1〇〇微米(um)而大於5微 米。 晶圓310包含晶背及晶面，其上面分別包含多個晶背 凸塊和晶面凸塊，如圖所示的晶背凸塊316和晶面凸塊 312，而更包含多個貫穿電極，分別電性導通所述的晶背凸 塊和晶面凸塊’如圖所示的貫穿電極314。 晶片320、330與340則分別包含晶背、晶面和多個晶 侧，晶面與晶背分別具有多個晶面凸塊，在一選擇實施例 中，還包含晶背凸塊以及電性連接所述凸塊的貫穿電極。 例如如圖所示，晶片320表面包含晶面凸塊322、貫穿電 極324與晶背凸塊326’晶片330表面包含晶面凸塊332、 貫穿電極334與晶背凸塊336,晶片34〇表面上包含晶面 凸塊342。上述的凸塊可以為銅凸塊(Qi Bump)或是銅/錫 銀微凸塊(Cu/SnAg Micro Bump)等等結構。 201227915 P51990111TW 36210twf.doc/n 黏著材料350可為高分子膠材，其中包含多個導電顆 粒351及/或多個非導電顆粒353，置於晶圓31〇與晶片 320、330與340之間’並同時完全包覆這些晶片32〇、330 與340的晶側。當黏著材料350包含導電顆粒353時，晶 面凸塊322、332、342透過導電顆粒353分別電性連接至 晶背凸塊316、326、336。當黏著材料350無包含導電顆 粒353時，晶面凸塊322、332、342分別以接觸方式電性 φ 連接至晶背凸塊316、326、336。包含導電顆粒353之黏 著材料350可以為異方性導電膠(Anisotr〇pic C0nductive Adhesive，ACA)，不包含導電顆粒353之黏著材料350可 以為非導電膠(Non-conductive Adhesive，NCA)。 在整個模封接合結構304中，堆疊結構中的最上層， 例如b曰片340，其晶片的晶背表面是可以裸露，而整個模 封接合結構304中，晶片340的晶背表面與黏著材料35〇 的表面是可以實質上等高，而形成此模封接合結構3〇4的 模封結構。 • 圖3B是說明本揭露内容所提出晶圓級的模封接合結 構製程示意圖’以形成例如圖3A的模封接合結構。 首先，提供一晶圓310，此晶圓310包含晶面311與 晶背313，而在晶面311與晶背313上分別包含多個晶背 凸塊和晶面凸塊’如圖所示的晶背凸塊312、322、332、 342和晶面凸塊316、326、336。而在晶圓310内包含多個 貫穿電極，如圖所示的貫穿電極314，用以電性導通所述 的晶背凸塊316與晶面凸塊312。而在晶圓310的晶背313 201227915 r j iyyui 11TW 36210twf.doc/n 表面上，塗上一層黏著材料352。此黏著材料352包含多 個導電顆粒351及非導電顆粒353。值得注意的是，以下 實施例雖以包含導電顆粒351之黏著材料352為例示，但 實際之接合方式，亦可使用如前段所述之方法，故並不以 此為限。 而後，1^供名人形成晶片/晶圓接合(C〇\y)堆疊架構的多 個晶片，例如圖中標示的晶片32〇、33〇與34〇。在此實施 例中僅說明部分晶片，但在整個晶圓上，可在同一層包含 多個晶片以形成堆疊架構，在此不再說明。 晶片320包含晶面32卜晶背323和多個晶侧325。在 晶面321上具有多個凸塊，例如圖示的晶面凸塊322，而 f晶背323上也可選擇性地具有多個凸塊，例如圖示的晶 背凸塊326。而晶片320的部分的晶面凸塊與晶背凸塊之 間，具有貫穿電極用以電性連接，例如圖示的晶面凸塊322 與晶背凸塊326’包含一貫穿電極324做電性連接。 而在整個晶圓級接合堆疊架構中，與晶片32〇同一層 的晶背表面上，塗上-層黏著材料354，例如進行晶圓^ 的異方性導電膠貼合(Wafer level AC A Lamination)。 而晶片330包含晶面33卜晶背333和多個晶側335。 在晶面331上具有多個凸塊，例如圖示的晶面凸塊332， ^晶背333上也可選擇性地具有多個凸塊，例如圖示的 曰曰月凸塊336。而晶片330的部分的晶面凸塊與晶背凸塊 之門具有貝牙電極用以電性連接，例如圖示的晶面凸塊 332與晶背凸塊336，包含一貫穿電極μ4做電性連接。而 201227915 rDiyyuiilTW 36210twf.doc/n 在整個晶圓級接合堆疊架構中，與晶片330同一層的晶背 表面上，塗上一層黏著材料356，例如異方性導電膠(aca)。 而晶片/晶圓接合(COW)堆疊架構的最上層，例如是晶 片340，包含晶面34卜晶背343和多個晶側345。在晶面 341上具有多個凸塊，例如圖示的晶面凸塊％]。 對準上述晶片320、330與340和晶圓31〇進行堆疊接 合。並藉由黏著材料，例如異方性導電膠，接人上述曰片 31 330與340及晶圓31〇,達成電性導通上 與晶拍Π_从·义β A a , t^ ，…一M W」-处日日叫〇工尼 者凸塊’並同時完全包覆之上述晶片32G、33()鱼34〇 的晶側325、335與345。 ” 圖曰3B所提出晶圓級的模封接合模封接合結構製程， =如以a日片320與晶圓310分別為第一晶片以及第二晶片 為例說明。此第一晶片（晶片Dm ^ 曰曰 换_哲 2〇)，包含第一晶背（晶背凸 ，巧、第-晶面（晶面321)和多個第一晶側(晶側325)， 晶 面上有多個電極（晶面凸塊322)。而^ 晶 片（例 ;曰曰° 310)’包含第二晶背（晶背313)及第二晶面（晶面 Ή6、’其中此第二晶背上包含多個晶背凸塊(晶背凸塊 此第_日日面上包含多個晶面凸塊（晶面凸塊M2)。而 =貫穿電極(如貫穿電極314)，位於第二晶片中，分別電 生導通上述的晶背凸塊和晶面凸塊。而黏著材料(黏著材料 ’置於第-晶片和第二晶片之間，且完全包覆第 片之第 n二， 晶側 晶
兩-圖3B所朗的晶圓級模封接合結構製程示意圖，僅 雨經由晶圓級的異方性導電膠貼合(Wafer levd ACA 201227915 f^iyyunlTW 36210twf.doc/n
Lamination)與堆疊(Stacking)兩個步驟，在製程上相較於傳 統需採用如圖1的堆疊、填充底膠以及模封三個步驟，或 疋如圖2的黏貼NFU材料、堆疊以及模封三個步驟，在製 权上需要花費較少的時間，可以有效降低製造的成本。而 對於底膠填充和模封製程，只需使用相同，可使成本降低。 另外，由於採用這樣堆豐的晶片結構，是透過異方性導電 膠(ACA)的導電顆粒電性連接，因此，在面對熱膨脹的不 一致(Thermal Expansion Mismatch)的情況，也不會造成影 響良率的問題。 / 本揭露内容所提出晶圓級的模封接合結構，可運用在 多個實施例中，其中一部份實施例的晶片堆疊結構，則如 圖4A〜4G的實施例所示。 如圖4A所示，本揭露内容提出一種晶圓級的模封接 合結構，包含至少上晶片410與下晶片420A堆疊電性連 接。上晶片410與下晶片420A的厚度，在一實施例中， 可以小於100微米（um)而大於5微米。 上晶片410包含基底層412與圖案化導電層414，此 圖案化導電層414為進行後段製程(Back-end-of-line， BEOL)時，已經形成於基底層412上的各種元件佈局’而 晶面上具有多個電極418。貫穿電極416則是形成於上晶 片410内，並連接到電極418。 下晶片420A包含晶面與晶背，在晶面上有多個晶面 凸塊425。而此實施例中，下晶片420的晶背上，加上一 絕緣層422，例如一介電層（Dielectric layer)。而在絕緣層
S 12 201227915 P51990111TW 36210twf.doc/n 422上’則可形成多個電錢金屬凸塊(Electroplating Metal Bump)421A。而多個貫穿電極423，則是分別電性導通上 述晶面凸塊425與電鍍金屬凸塊421A。 圖4B則是本揭露内容提出一種晶圓級的模封接合結 構之另一實施例。與圖4A相同部分則不再冗述，而差異 則是在於下晶片420A晶背的絕緣層422上，形成多個無 電锻金屬凸塊(Electroless Metal Bump)421B。而後在絕緣 層422上形成晶圓級的異方性導電膠(ACA)428。經由異方 性導電膠的接合(ACA Joint)，上晶片410的電極418可與 下晶片420B的無電鍍金屬凸塊421B堆疊而電性連接。 圖4C則是本揭露内容提出一種晶圓級的模封接合結 構之另一實施例。與圖4A相同部分則不再冗述，而差異 則是在於下晶片420C晶背的絕緣層422上，形成多個晶 背金屬薄膜(Back side Metal Thin Film)421C。而後在絕緣 層422上形成晶圓級的異方性導電膠(ACA)428。經由異方 性導電勝的接合(ACA Joint)，上晶片410的電極418可與 下晶片420C的晶背金屬薄膜421C堆疊而電性連接。 圖4D則是本揭露内容提出一種晶圓級的模封接合結 構之另一實施例。與圖4A相同部分則不再冗述，而差異 則是在於下晶片420D晶背的絕緣層422上，形成重佈局 層（Redistribution Layer，RDL)421D。此重佈局層 (RDL)421D例如包含鋁(A1)、銅或其合金材質。而後在絕 緣層422上形成晶圓級的異方性導電膠(ACA)428。經由異 方性導電膠的接合(ACA Joint)，上晶片410的電極418可 13 201227915 P51990111TW 362 lOtwf. doc/n 與下晶片420D的重佈局層（RDL)421D堆疊而電性連接。 此架構可減少對準的問題。 圖4E則是本揭露内容提出一種晶圓級的模封接合結 構之另一實施例。與圖4A相同部分則不再冗述。此實施 例適用於石夕B曰片穿孔内部互連(thr〇Ugh_siiicon_vja，tsv) 的結構。而與圖4A差異則是在於下晶片42〇]E晶背上，直 接利用矽晶片穿孔内部互連(TSV)423與異方性導電膠 (ACA)428，與上晶片410的電極418進行電性連接。 圖4F則是本揭露内容提出一種晶圓級的模封接合結 鲁 構之另一貫施例。與圖4A相同部分則不再冗述，而差異 則是在於上晶片410晶面的柱狀電極418F。而下晶片42〇f 晶背的絕緣層422上，形成多個晶背金屬薄膜洞(Back sMe
Metal Thin Film Cavity)429。而後在絕緣層422上形成晶圓 級的異方性導電膠(ACA)428。經由異方性導電膠的接合 (ACA Joint)，上晶片410的柱狀電極418F可透過在下晶 片420B的晶背金屬薄膜洞429内的異方性導電膠 (ACA)428導體，與下晶片420F的貫穿電極423，或是矽 _ 晶片穿孔内部互連(TSV)堆疊而電性連接。 圖4G則是本揭露内容提出一種晶圓級的模封接合結 構之另一實施例，與圖4E具有類似的結構。與圖4A相同 部分則不再冗述。此實施例適用於矽晶片穿孔内部互連 (TSV)的結構。而與圖4A差異則是在於下晶片420E晶背 上’直接利用石夕晶片穿孔内部互連(TSV)423與異方性導電 膠(ACA)428 ’與上晶片410的電極418進行電性連接。而
S 14 201227915 P51990U1TW 36210twf.doc/n 與圖4E的差異在於’在下晶片42〇E晶背上具有多個凹槽 427，可防止接合結構滑移的情況。 圖5是說明本揭露内容所提出晶圓級的模封接合結構 製程示意圖。 首先’提供一晶圓510,此晶圓510包含晶面與晶背，
並在晶圓510的晶背表面上，形成一層黏著材料52〇，例 如異方性導電膠(ACA)。此黏著材料520包含多個導電顆 粒及高分子膠材。而形成方式可以為黏貼或是塗上等方式。 而後，進行晶片/晶圓接合(COW)堆疊的製程，經過預 先凸塊形成製程(Pre-bond process)在晶片的晶面及/或晶背 上形成多個凸塊。並接著在晶片上形成黏著材料，例如進 行晶圓級的異方性導電膠貼合（Wafer kvel aca Lamination)，而形成多個晶片堆疊結構53〇。而後，對整 個晶圓進行接合的製程，並隨後使用切割滾輪54〇進行切 割製程(Dicing Process) ’形成多個模封接合結構55〇。 在本揭露所提出一種晶圓級的模封接合結構的其中— 個實施例的接合架構’不但可達成高密度的電極接^，降 低製程溫度的接合界面溫度可低於或等於2〇〇攝氏溫度 200。〇 ’但最好大於⑽。C，並且能縮㈣程的時間^可 ==秒、，但最好大於。·5秒鐘’並同如^ 、本揭路内容提出一種晶圓級模封接合結構的製 法’可有效崎低製程步驟、降低成本(轉和模封6 成），並藉由導電顆粒或非導電顆粒填充於模封材料間= 15 201227915 DiyWlllTW 36210twf.doc/n 低其熱阻，以增加晶圓⑽莫封架構的可靠性。 本揭露内容提出-種晶圓級模封接合結構，在一實施 例中:可對晶圓級模封架構進行延伸，因此，運用不同晶 片堆豐之架構亦屬本揭露内容所屬之範B壽。 «月多…、圖6a 6e，疋說明本揭露内容所提出晶圓級模 封接合結構的製程方法巾，晶片貼合的方法實施例流程 圖。請參照圖6a ’提供_基板61G ’包含—主動面612， 其中-第-圖案化導電層620位於此主動面612上。將此 基板61G之主動面612覆蓋—第一黏著層63()。 馨 而後如圖6b ’提供—第一晶片64〇，包含一第一表面 料2與一第二表面644,其中一第二圖案化導電層64〇位於 第一表面642。並接著提供一緩衝材料層66〇，而將緩衝材 料層660附著於第一晶片64〇 ,其中第一晶片64〇之第二 表面644與此緩衝材料層66〇接合。上述緩衝材料層66〇 之面積大於第一晶片640之第二表面644面積，而緩衝材 料層660例如為矽膠(siiicon rubber)。第一晶片64〇的厚度 小於100 μπι，在一實施例中，為5〇微米（μιιη)等級的薄型 ⑩ 晶片。 接著如圖6C，將附著有緩衝材料層660之第一晶片 640連接至基板610,使第一晶片640之第二圖案化導電層 650與基板610之第一圖案化導電層62〇電性連接。使用 附著有緩衝材料層660之第一晶片64〇與基板61〇進行一 第一壓合過程。此第一壓合過程之時間長度可小於或等於 1〇秒鐘，最好大於0.5秒鐘，而操作的接合界面溫度可低
S 16 201227915 P51990111TW 3 621 Otwf.doc/n 於或导於200 C，但最好大於go。c。 上述基板610之第-圖案化導電層62()與 =第二圖案化導電層65〇的接合，在 實: 可以透過例如金屬熔接(metal J01nt)以電性連接貫= 一^ 擇實施例巾，第-黏著層㈣更包含多個導 ;2 化導電層650透過這些導電微上 f連接至基板610之第—圖案化導電層_。在經過壓人
=，如圖6d所示’第一黏著層63"目對於 之主動面612的表φ 632,其相對於基板6 的垂直高度，實質上等於第-晶片_之第二表面⑽相 對於基板61〇之主動面612的垂直高度。在移除緩衝材料 層660後，第一晶片640的第二表面6私與第一黏著層㈣ 與第二表面實值上料的暴露平面奶上，可形成一保護 。月 > 圖7a 7e，疋說明本揭露内容所提出晶圓級模 封接合結_製财法中U貼合料另—實施例流程 圖。請參照圖7a ’提供一基板71〇，包含一主動面712， 其中-第-圖案化導電層72〇位於此主動面712上。將此 基板710之主動面712覆蓋一第一黏著層73〇，其中黏著 層730更包含多個導電微粒732。 而後如圖7b，提供一第一晶片74〇，包含一第一表面 M2與一第二表面744’其中一第二圖案化導電層75〇位於 第-表面742。並接著提供—緩衝材料層·，而將緩衝材 料層760附著於第一晶片74〇,其中第一晶片74〇之第二 17 201227915 P51990111TW 3621〇twf.doc/n 表面744與此緩衝材料層760接合。上述缓衝材料層760 之面積大於第一晶片740之第二表面744面積，而緩衝材 料層760例如為矽膠(siliconrubber)。第一晶片740的厚度 小於100 μηι ’在一實施例中，為50微米（μπ1)等級的薄型 晶片。 接著如圖7c，將附著有緩衝材料層76〇之第一晶片 740連接至基板710’使第一晶片74〇之第二圖案化導電層 750與基板710之第一圖案化導電層72()電性連接。使用 附著有缓衝材料層760之第一晶片740與基板710進行一 · 第一壓合過程。此第一壓合過程之時間長度可小於或等於 10秒鐘，最好大於0.5秒鐘，而操作的接合界面溫度可低 於或#於200 C，但最好大於8〇。c。 上述基板710之第一圖案化導電層72〇與第一晶片 740之第二圖案化導電層75〇的接合，在此實施例中，第 一晶片740之第二圖案化導電層75〇透過這些導電微粒 732以電性連接至基板71〇之第一圖案化導電層72〇。在經 過壓合過程後’如圖7d所示，第一黏著層73〇相對於基板 籲 710之主動面712的表面732，其相對於基板71〇的主動面 712的垂直高度’實質上等於第一晶片74〇之第二表面％ 相對於基板710之主動面712的垂直高度。如圖％所示， 在，除緩衝材料層76〇後，第一晶片74〇的第二表面％ ，第黏著層73〇與第二表面實值上等高的暴露平面乃2 上，可形成一保護層770。 請參照圖8a〜8e，是說明本揭露内容所提出晶圓級模
S 18 201227915 P51990111TW 36210twf.doc/n 封接合結構的製程方法另一實施例流程圖。請參照圖8a， 提供一基板810’包含一主動面812’其中一第一圖案化導 電層820位於此主動面812上。將此基板81〇之主動面812 覆蓋一第一黏者層831。第一黏著層831的材料可以為異 方性導電膠(Anisotropic Conductive Adhesive，ACA)，或是 由高分子膠材所組成’包含例如多個導電顆粒及/或多個非 導電顆粒。藉由導電顆粒或非導電顆粒填充於模封材料間 以降低其熱阻，以增加晶圓級模封架構的可靠性。 而後如圖8b，提供一第一晶片84〇，包含一第一表面 842與一第二表面844’其中第一晶片840包含在第一表面 842包含多個凸塊852，在第二表面844包含多個凸塊 856’而每個凸塊852與對應的凸塊856之間包含一内連線 結構854。此内連線結構854為矽晶片穿孔内部互連 (through-silicon-via ’ TSV)結構。而凸塊 852 與凸塊 856 可 為金屬或導電材料。 接著提供一緩衝材料層860，而將緩衝材料層86〇附 著於第-晶片840’其中第一晶片84〇之第二表面m盥 此緩衝材料層_接合。上述緩衝材料層_之面積大於 第一晶片840之第二表面844面積’而緩衝材料層例 如為矽膠(silicon rubber)。第一晶片刚的厚度小於1〇〇 μιη ’在-貫施例中’ & 5〇微米（㈣等級的薄型晶片。 接著如圖8G’將附著有緩衝材料層860之第-晶片 _連接至基板⑽，使第一晶片84〇的凸塊852與基板 81〇之第-圖案化導電層820電性連接。使用附著有緩衝 19 36210twf.doc/n 201227915
!· «/ 1 1 1TW 材料層860之第一晶片840與基板81〇進行一第一壓合過 程。此第-塵合過程之時間長度可小於或等於1()秒鐘二最 好大於0.5秒鐘，而操作的接合界面溫度可低於或等於 200° C，但最好大於80。c。 上述基板810之第一圖案化導電層82〇與第一晶片 840的凸塊852接合，在一選擇實施例中，可以透過^如 金屬熔接(metal joint)以電性連接。在另—選擇實施例中， 第一黏著層831更包含多個導電微粒，第—晶片84〇之第 二圖案化導電層850透過這些導電微粒以電性連 810之第-圖案化導電層82〇。在經過壓合過程後，二圖 8d所示，第一黏著層831相對於基板810之主動面812的 表面832，其相對於基板81〇的主動面812的垂直高度， 貫質上4於第一晶片840之第二表面844相對於基板81〇 之主動面812的垂直高度。 如圖8d所示，在移除緩衝材料層86〇後，將第一晶 片840之第二表面844上，以及第一黏著層831的表面832 上，覆蓋一第一黏著層833。而後提供一第二晶片，包 含一第三表面872與一第四表面874,其中在第三表面872 包含例如第二圖案化導電層880。接著提供如前述的緩衝 材料層860附著於第二晶片87〇，並與第二晶片之的第四 表面874接合。 接著如圖8e，將附著有緩衝材料層86〇之第二晶片 870連接至第一晶片840的第二表面844，使第二晶片870 之第二圖案化導電層880與第一晶片84〇的第二表面844 201227915 a 1TW 36210twfdoc/n 上的凸塊856電性連接。使用附 二晶片870與第一晶片84〇，衝材料層副之第 麼合過程之時間長度小於1G秒鐘 j合過程。此第二 低於200。C。 刼作的接合界面溫度 上述第一晶片840的凸塊856 ι 圖案化導電層880的接合，在—】擇請之第二 例如金屬炫接以電性連接。^^透過 =第第二黏著層833更包含多個導電 t日二: 之案化導電層88透過這些導電微粒，電第 一日日片840的凸塊856。 逑接至第 暴露對第圖—示’第：黏著層833 的垂直高度’實質上等於第；第:表面844 對於第-晶片8物二表面844的垂表=相 衝材料層_後，第二晶片8 神除緩 而此時，第二=二晶片等等。 (^〇ugh-sto 雖然本發明已以實施 本發明，任何所屬技術領域中且有通常;；=非用以限定 本發明之精神和範圍内，當可；在不脫離 發明之保護範圍當視後附之申請專利齡^ 【圖式簡單說明】 21 5 201227915 rDiyyuiilTW 36210twf.doc/n 圖1是s兄明習知一種使用底膠填充的晶片/晶圓接合 (COW)構裝技術的結構示意圖。 圖2是說明習知另—種使用非流動性祕(NL Underfill ’ NFU)製程的晶片/晶圓接合(c〇w)；^裝技術的結 構不意圖。 圖3A是說明本揭露内容所提出晶圓級的模封接合結 構，在多個實施例其中的一個結構示意圖。 圖3B是說明本揭露内容所提出晶圓級的模封接合結 構製程示意圖’以形成例如圖3A的模封接合結構。 圖4A〜4G是說明本揭露内容所提出晶圓級的模封接 合結構不同實施例示意圖。 圖5是說明本揭露内容所提出晶圓級的模封接合結構 製程示意圖。 圖6a〜6e是說明本揭露内容所提出晶圓級模封接合結 構的製程方法其中一實施例流程圖。 圖7a〜7e是說明本揭露内容所提出晶圓級模封接合結 構的製程方法其中另一實施例流程圖。 圖8a〜8f是說明本揭露内容所提出晶圓級模封接合結 構的製程方法其中另一實施例流程圖。 【主要元件符號說明】 1 :載體(Carrier) 110 :緩衝層 112 :晶片堆疊結構 201227915 P5iyyuUlTW 36210twf.doc/n 120 ·晶 0 130、140 與 150 :晶片 160 :底膠(Underfill)層 170 :模封(Molding)層 200 :載體(Carrier) 210 :缓衝層 220 :晶圓 222:堆疊的晶片結構 230、240 與 250 :晶片 232、242、252 :非流動性底膠(NFU) 270 :模封(Molding)層 300 :載體(Carrier) 302 :緩衝層 304 :晶圓級模封接合結構 310 :晶圓 312 :晶面凸塊 _ 316:晶背凸塊 320、330 與 340 :晶片 322、332、342 ··晶面凸塊 324、334、344 :貫穿電極 326、336、346 :晶背凸塊 350 :黏著材料 351 :導電顆粒 353 :非導電顆粒 23 201227915 FMyyunlTW 36210twf.doc/n 32卜 331、341 :晶面 323、333、343 :晶背 325、335、345 :晶側 410 .上晶片 420A〜420G :下晶片 412 :基底層 414 :圖案化導電層 418 :電極 418F :柱狀電極 416 :貫穿電極 422 :絕緣層 421A :電鍍金屬凸塊(Electroplating Metal Bump) 421B :無電鑛金屬凸塊(Electroless Metal Bump) 421C :晶背金屬薄膜(Back side Metal Thin Film) 42ID :重佈局層（Redistribution Layer，RDL) 423 :貫穿電極 425 .晶面凸塊 428 :異方性導電膠(ACA) 429 :晶背金屬薄膜洞（Back side Metal Thin Him Cavity) 427 :凹槽 510 :晶圓 520:黏著材料 530 :晶片堆疊結構
S 24 201227915 f5iyy〇lllTW 36210twf.doc/n 540 :切割滚輪 550 :模封接合結構 610 :基板 612 :主動面 620 :第一圖案化導電層 630 :第一黏著層630 640 :第一晶片 642 :第一表面 644 :第二表面 660 :緩衝材料層 670 :保護層 710 :基板 712 :主動面 720 :第一圖案化導電層 730 :第一黏著層 732 :導電微粒 • 740 :第一晶片 742 :第一表面 744 :第二表面 750 :第二圖案化導電層 760 :緩衝材料層760 770 :保護層 810 :基板 812 :主動面 25 201227915 X U IP^\J 1
11TW 36210twf.doc/n 820 :第一圖案化導電層 831、833 :黏著層 840 :第一晶片 842 :第一表面 844 :第二表面 852、856 :凸塊 854 :内連線結構 860 :緩衝材料層 870 :第二晶片 872 :第三表面 874 :第四表面 880 :第二圖案化導電層 26

Claims (1)

  1. 201227915 rjiyyvi i 1TW 36210twf.doc/n 七、申請專利範圍： 1. 一種模封接合結構，包含： 一第一晶片，包含一第一晶背、一第一晶面和多個第 一晶側，該第一晶面上有多個第一晶面凸塊； 一第二晶片，包含一第二晶背及一第二晶面，其中該 第二晶背上包含多個第二晶背凸塊，該第二晶面上包含多 個第二晶面凸塊； 多個貫穿電極’位於該弟二晶片中5分別電性導通該 些第二晶背凸塊和該些第一晶面凸塊;以及 一黏著材料，置於該第一晶片和該第二晶片之間，並 同時完全包覆該第一晶片之該些第一晶側； 其中該第一晶片中之該第一晶面凸塊電性連接至該 第二晶片令之該第二晶背凸塊。 2. 如申請專利範圍第1項所述之模封接合架構，其中 該第一晶片更包含多個第二貫穿電極，該第一晶背更包含 多個第一晶背凸塊，該些第二貫穿電極位於該第一晶片 中，分別電性導通該些第一晶面凸塊與該些第一晶背凸塊。 3. 如申請專利範圍第1項所述之模封接合架構，其中 該些晶面凸塊與晶背凸塊為電鑛金屬或無電鑛金屬其中之 〇 4. 如申請專利範圍第1項所述之模封接合架構，其中 在該些第一晶背凸塊與該第二晶片之第二晶面之間更包含 一絕緣層（dielectric layer)。 5. 如申請專利範圍第1項所述之模封接合架構，其中 27 ί 1TW 36210twf.doc/n 201227915 rj 該黏著材料在該些晶侧具有相同厚度。 * 6.如申請專利範圍第1項所述之模封接合架構，其中 該第一晶片厚度小於或等於100微米(um)但大於5微米。 如^請專利範圍第1項所述之模封接合架構，1中 田-黏者材料包含多個導電顆粒時，該第 、 =過該些導電顆粒電性連接至該第二晶 該黏著材所述之模封接合架構，其中 多個非導電顆^心子膠材，且該高分子膠材中包含 9·一種晶圓級模封接合結構，包含： 一晶圓，包含—第一 曰 晶背上包含多個晶背凸塊，該：勺丄其中該第_ 塊’該晶圓更包含多個第—二3多個晶面凸 晶背凸塊和該些晶面凸塊；=電極’ *別電性導通該些 夕個堆结構，其令每—該堆疊結構包含 多個;:二第包含:第二晶背、第二晶面和 及 _二晶面上有多個第一電極;以 一黏著材料，置於該第一晶片和該 晶 構更包含多架 片令分別電性導通該些第一電極。 於^- 28 201227915 r^iyyunlTW 36210twf.doc/n 11. 如申請專利範圍第10項所述之晶圓級模封接合架 構，其中該第一晶片之第二晶背更包含多個晶背電極，以 電性導通該些第二貫穿電極。 12. 如申請專利範圍第11項所述之晶圓級模封接合架 構，其中每一該堆疊結構更包含一第二晶片，該第二晶片 包含一第三晶背、第三晶面和多個第三晶侧，該第三晶面 上有多個第二電極，其中，該些第二電極電性連接至該第 一晶片的該些晶背電極’且該黏者材料完全包覆該苐二晶 片之該些第三晶側。 13. 如申請專利範圍第9項所述之晶圓級模封接合架 構，其中該些晶面凸塊為電鑛金屬或無電锻金屬其中之一。 14. 如申請專利範圍第9項所述之晶圓級模封接合架 構，其中在該些晶背凸塊與該第一晶片的該第二晶背之間 更包含一絕緣層（dielectric layer)。 15. 如申請專利範圍第9項所述之晶圓級模封接合架 構’其中該黏者材料在該些晶側具有相同厚度。 16. 如申請專利範圍第9項所述之晶圓級模封接合架 構，其中當該黏著材料包含多個導電顆粒時，該晶圓之晶 背凸塊透過該些導電顆粒電性連接至該第一晶片之該第一 電極。 17. 如申請專利範圍第16項所述之晶圓級模封接合架 構，其中該黏著材料包含高分子膠材，且該高分子膠材包 含多個非導電顆粒。 18. —種晶圓級晶片之封裝方法，包含： 29 11TW 3621 Otwf.doc/n 201227915 提供一基板，包含一主動面，其中一第一圖案化導電 層位於該主動面； 將該基板之該主動面覆蓋一第一黏著層； 提供—第一晶片，包含一第一表面與I第二表面，其 中一第二圖案化導電層位於該第一表面； /、 提供一緩衝材料層； 將該緩衝材料層附著於該第一晶片，其中該第一晶片 之該第二表面與該緩衝材料層接合； 曰曰 著有該緩衝材料層之該第一晶片連接至該基 ϋ第—晶片之該第二圖案化導電層與該基板之該第 一圖案化導電層電性連接；以及 〜2附著有該緩衝材料層之該第-晶片與該基板進 1丁 Γ —壓合過程’其中該緩衝材料層之面積大於該第- 日曰片之該第二表面之面積。 19·^請專利範㈣18項所述之晶圓級晶片之封裝 一译隹，、中该第一黏著層相對於該基板之該主動面之垂直 於Ϊ第—晶片之該第二表面相對於該基板之該主動 由之垂直向度。 2〇·如申請專利範圍第Μ項所述之晶圓級晶片之封裝 / ’其中該緩衝材料層為矽膠(silic〇n rubber)。 方法申請專利範圍第18項所述之晶圓級晶片之封裝 ^篦i其中該第一晶片之該第二圖案化導電層與該基板之 “ 圖案化導電層透過金屬熔接(metal joint)以電性連 接。 201227915 rji^vulTW 36210twf.d〇c/n -θ h 2黏著層中更包含複數個導電微粒，該第 “ ^ ΐ二圖案化導電層透過該複數個導電微粒以電 連接至该基板之該第一圖案化導電層。 23.如申δ月專利範圍第18項所述之晶圓級晶片之封裝 4 /、中°亥第曰曰片之厚度小於或等於100微米（μηι)但 大於5微米。
    、24‘如中請專利範圍» 18工員所述之晶 圓級晶片之封裝 H其中該第-麼合過程之時間長度小於或等於1〇秒 鐘’但大於〇·5秒鐘。 25.如申請專利範圍第18項所述之晶圓級晶片之封裝 方法，其中該第一壓合過程之接合界面溫度低於或等於 200° C ’ 但大於 8〇° c。 26·如申請專利範圍第18項所述之晶圓級晶片之封裝 方法，其中該第一晶片更包含一内連線結構與一第三圖案 化導電層；其中該第三圖案化導電層位於該第二表面，該 第二圖案化導電層透過該内連線結構以電性連接至該該第 一表面之該第二圖案化導電層。 27.如申請專利範圍第26項所述之晶圓級晶片之封裝 方法，其中該内連線結構為直通矽晶穿孔(Through-Silicon Via)。 28.如申請專利範圍第26項所述之晶圓級晶片之封裝 方法’在該第一壓合過程後更包含： 移除該緩衝材料層； 31 201227915irw 36210twf.doc/n 將該第一晶片之該第二表面覆蓋一第二黏著層； 提供一第二晶片，包含一第三表面與一第四表面，其 中一第四圖案化導電層位於該第三表面； 將該缓衝材料層附著於該第二晶片，其中該第二晶片 之該第四表面與該緩衝材料層接合； 將附著有該緩衝材料層之該第二晶片連接至該第一 晶片，使5亥第一晶片之該第四圖案化導電層與該第一晶片 之該第二圖案化導電層電性連接；以及 使用附著有緩衝材料層之該第二晶#與該基板 爆 一第二壓合過程。 29. 如申請專魏㈣28顿述之晶圓級晶片之封裝 方法，其中该第二黏著層與該第一黏著層材料相同。 30. 如申請★專利範圍第28項所述之晶圓級晶片之封農 方法，其中忒第一壓合過程之時間長度小於2秒鐘；其中 該第二壓合過程之時間長度小於1〇秒鐘。 31. 如申請專利範圍第28項所述之晶圓級晶片之封裝 方法，其中δ亥第一壓合過程之接合界面溫度低於或等於 200° C，但大於 80。C。 · 32. -種晶圓級晶片之封&结構，包含： 一基板，包含一主動面，其中〆第一圖案化導電層位 於該主動面； 一第一晶片，連接至該基板，包含一第一表面與一第 二表面，其中该第一表面相鄰於該主動面，其中一第二圖 案化導電層位於該第一表面，且該第二圖案化導電層電性 S 32 201227915 P51990111TW 36210twf.doc/n 連接至該基板之該第一圖案化導電層；以及 -第-黏著層，填充於該第—晶片與該基板 覆蓋該基板之該絲面、以及該第―晶片除 = 之所有表面； &面外 古产萆第:ΐ著層相對於該基板之該主動面之垂直 同度專制第-晶片之該第二表面相對於 面之垂直高度。 主動 33.如申明專利範圍第32項所述之晶 結構，其中該第-晶片之該第二圖案 接。 冤e透過金屬熔接(metal j〇int)以電性連 利辄㈣32項所狀晶®級晶片 :Si著層中更包含複數個導電微粒，： 連接至該基板之該第if數個導電微粒電性 結構^和^3^料之封裝 μ»但大於5微米。'度小於或等於1〇〇微米（㈣， 36. 如申請專利範圍第 St;中:第一晶片更包含-内連線= 第3化f第三圖案化導電層位於該第四表Si f f 4电層透過_連_構電性連接至兮第f 面之該第二圖案化導電層。 安主4弟一表 37. 申請專利範圍第36項所述之晶圓級晶片之封裳結 33 201227915 filWUlllTW 36210twf.doc/n ^其^該内連線結構為直通石夕晶穿孔伽呵議⑽ 38.如申請專利範圍 結構，其中更包含一第_曰J所述之晶圓級晶片之封裝 -第三表面與-第四^日日^’連接至該第—晶片，包含 晶片之該第二表面；^ 1亥第二表面接鄰於該第- 該第三表面，該第四圖^含—第四圖案化導電層位於 之該第三_料電^化導電層連接至該第一晶片 39·如申請專利範圍 結構，其中更包含 6項所述之晶圓級晶片之封裝 第二晶片之間，且，充填於該第—晶片與該 等於該第二晶片之該第^者層相對於該基板之垂直高度 有;:該第二黏著層覆蓋該第-軸 40.如申請專利範 結構’其中該第二黏：===封裝 34 1
TW099146766A 2010-12-30 2010-12-30 晶圓級模封接合結構及其製造方法 TWI496271B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/981,475 US8384215B2 (en) 2010-12-30 2010-12-30 Wafer level molding structure
TW099146766A TWI496271B (zh) 2010-12-30 2010-12-30 晶圓級模封接合結構及其製造方法
CN2011100342880A CN102543969A (zh) 2010-12-30 2011-02-01 晶片级模封接合结构及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW099146766A TWI496271B (zh) 2010-12-30 2010-12-30 晶圓級模封接合結構及其製造方法

Publications (2)

Publication Number Publication Date
TW201227915A true TW201227915A (en) 2012-07-01
TWI496271B TWI496271B (zh) 2015-08-11

Family

ID=46350468

Family Applications (1)

Application Number Title Priority Date Filing Date
TW099146766A TWI496271B (zh) 2010-12-30 2010-12-30 晶圓級模封接合結構及其製造方法

Country Status (3)

Country Link
US (1) US8384215B2 (zh)
CN (1) CN102543969A (zh)
TW (1) TWI496271B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI633646B (zh) * 2017-04-06 2018-08-21 優顯科技股份有限公司 用於批量移轉微半導體結構之方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8384215B2 (en) * 2010-12-30 2013-02-26 Industrial Technology Research Institute Wafer level molding structure
US9157014B2 (en) 2012-11-29 2015-10-13 Micron Technology, Inc. Adhesives including a filler material and related methods
US9418985B2 (en) 2013-07-16 2016-08-16 Qualcomm Incorporated Complete system-on-chip (SOC) using monolithic three dimensional (3D) integrated circuit (IC) (3DIC) technology
US10163864B1 (en) * 2017-08-16 2018-12-25 Globalfoundries Inc. Vertically stacked wafers and methods of forming same

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1321980A4 (en) * 2000-09-25 2007-04-04 Ibiden Co Ltd SEMICONDUCTOR ELEMENT, METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT, MULTILAYER PRINTED CIRCUIT BOARD, AND METHOD FOR MANUFACTURING MULTILAYER PRINTED CIRCUIT BOARD
JP2002151551A (ja) 2000-11-10 2002-05-24 Hitachi Ltd フリップチップ実装構造、その実装構造を有する半導体装置及び実装方法
US20020098620A1 (en) 2001-01-24 2002-07-25 Yi-Chuan Ding Chip scale package and manufacturing method thereof
JP3891133B2 (ja) 2003-03-26 2007-03-14 セイコーエプソン株式会社 電子部品の製造方法および電子部品の実装方法
US6841883B1 (en) 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
US7088005B2 (en) 2003-12-31 2006-08-08 Intel Corporation Wafer stacking with anisotropic conductive adhesive
JP5052130B2 (ja) * 2004-06-04 2012-10-17 カミヤチョウ アイピー ホールディングス 三次元積層構造を持つ半導体装置及びその製造方法
JP4795677B2 (ja) * 2004-12-02 2011-10-19 ルネサスエレクトロニクス株式会社 半導体装置およびそれを用いた半導体モジュール、ならびに半導体装置の製造方法
JP5123664B2 (ja) * 2005-09-28 2013-01-23 スパンション エルエルシー 半導体装置およびその製造方法
JP2007103737A (ja) 2005-10-05 2007-04-19 Sharp Corp 半導体装置
CN101097932A (zh) * 2006-06-30 2008-01-02 曾世宪 低噪声轻薄型光电感测装置及其制造方法
US20080108181A1 (en) * 2006-11-06 2008-05-08 City University Of Hong Kong Method for attaching integrated circuit component to a substrate
KR100838647B1 (ko) * 2007-07-23 2008-06-16 한국과학기술원 Ａｃｆ／ｎｃｆ 이중층을 이용한 웨이퍼 레벨 플립칩패키지의 제조방법
US8101460B2 (en) * 2008-06-04 2012-01-24 Stats Chippac, Ltd. Semiconductor device and method of shielding semiconductor die from inter-device interference
US7851893B2 (en) * 2008-06-10 2010-12-14 Stats Chippac, Ltd. Semiconductor device and method of connecting a shielding layer to ground through conductive vias
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US8263434B2 (en) * 2009-07-31 2012-09-11 Stats Chippac, Ltd. Semiconductor device and method of mounting die with TSV in cavity of substrate for electrical interconnect of Fi-PoP
US8822281B2 (en) * 2010-02-23 2014-09-02 Stats Chippac, Ltd. Semiconductor device and method of forming TMV and TSV in WLCSP using same carrier
US8492911B2 (en) * 2010-07-20 2013-07-23 Lsi Corporation Stacked interconnect heat sink
US9224647B2 (en) * 2010-09-24 2015-12-29 Stats Chippac, Ltd. Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
US8384215B2 (en) * 2010-12-30 2013-02-26 Industrial Technology Research Institute Wafer level molding structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI633646B (zh) * 2017-04-06 2018-08-21 優顯科技股份有限公司 用於批量移轉微半導體結構之方法
US10504872B2 (en) 2017-04-06 2019-12-10 Ultra Display Technology Corp. Method of batch transferring micro semiconductor structures

Also Published As

Publication number Publication date
TWI496271B (zh) 2015-08-11
US8384215B2 (en) 2013-02-26
CN102543969A (zh) 2012-07-04
US20120168933A1 (en) 2012-07-05

Similar Documents

Publication Publication Date Title
US11217563B2 (en) Fully interconnected heterogeneous multi-layer reconstructed silicon device
TWI331391B (en) Stackable semiconductor device and fabrication method thereof
TWI469312B (zh) 晶片堆疊結構及其製作方法
TWI308382B (en) Package structure having a chip embedded therein and method fabricating the same
TWI502723B (zh) 多晶粒堆疊封裝結構
TW201225762A (en) Package substrate having an embedded via hole medium layer and method of forming same
TW200847351A (en) Wafer level system in package and fabrication method thereof
WO2013127045A1 (zh) 一种用于三维集成混合键合结构及其键合方法
TW200935574A (en) Inter-connecting structure for semiconductor device package and method of the same
WO2018171100A1 (zh) 集成有功率传输芯片的封装结构的封装方法
TW201227915A (en) Wafer level molding structure and manufacturing method thereof
TW202139361A (zh) 製作雙側半導體裝置之方法及相關裝置、總成、封裝及系統
US20220352121A1 (en) Semiconductor package having passive support wafer
US20240170435A1 (en) Anisotropic conductive film with carbon-based conductive regions and related semiconductor device assemblies and methods
WO2018157546A1 (zh) 集成有供电传输系统的封装件的封装方法
CN114203563A (zh) 一种多层堆叠存储器封装方法及封装结构
TW201238015A (en) Inner layer heat-dissipating board and multi-chip stack package structure having inner layer heat-dissipating board and fabrication method thereof
TW200935580A (en) Method for manufacturing stack package using through-electrodes
US20150179557A1 (en) Semiconductor chips having heat conductive layer with vias
TWI234246B (en) 3-D stackable semiconductor package
TW200841407A (en) Stackable semiconductor device and manufacturing method thereof
WO2011148445A1 (ja) 半導体装置及びその製造方法
CN207852655U (zh) 半导体芯片的封装结构
CN207587718U (zh) 指纹识别芯片的封装结构
TWI832348B (zh) 封裝結構及其製作方法