TW201201008A - Composite semiconductor memory device with error correction - Google Patents

Composite semiconductor memory device with error correction Download PDF

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Publication number
TW201201008A
TW201201008A TW100106888A TW100106888A TW201201008A TW 201201008 A TW201201008 A TW 201201008A TW 100106888 A TW100106888 A TW 100106888A TW 100106888 A TW100106888 A TW 100106888A TW 201201008 A TW201201008 A TW 201201008A
Authority
TW
Taiwan
Prior art keywords
composite semiconductor
memory device
data
interface
memory
Prior art date
Application number
TW100106888A
Other languages
English (en)
Chinese (zh)
Inventor
Jin-Ki Kim
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Publication of TW201201008A publication Critical patent/TW201201008A/zh

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Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38Response verification devices
    • G11C29/42Response verification devices using error correcting codes [ECC] or parity check
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/611Specific encoding aspects, e.g. encoding by means of decoding
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411Online error correction

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
TW100106888A 2010-03-22 2011-03-02 Composite semiconductor memory device with error correction TW201201008A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US31613810P 2010-03-22 2010-03-22

Publications (1)

Publication Number Publication Date
TW201201008A true TW201201008A (en) 2012-01-01

Family

ID=44648192

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100106888A TW201201008A (en) 2010-03-22 2011-03-02 Composite semiconductor memory device with error correction

Country Status (8)

Country Link
US (2) US9098430B2 (enExample)
EP (1) EP2550661A4 (enExample)
JP (1) JP2013522779A (enExample)
KR (1) KR20120137416A (enExample)
CN (1) CN102812519A (enExample)
CA (1) CA2791931A1 (enExample)
TW (1) TW201201008A (enExample)
WO (1) WO2011116454A1 (enExample)

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US9135185B2 (en) 2012-12-23 2015-09-15 Advanced Micro Devices, Inc. Die-stacked memory device providing data translation
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US9170948B2 (en) 2012-12-23 2015-10-27 Advanced Micro Devices, Inc. Cache coherency using die-stacked memory device with logic die
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US9286948B2 (en) 2013-07-15 2016-03-15 Advanced Micro Devices, Inc. Query operations for stacked-die memory device
CN104750569A (zh) 2013-12-30 2015-07-01 深圳市中兴微电子技术有限公司 一种实现数据纠错的方法及装置
JP6131207B2 (ja) 2014-03-14 2017-05-17 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置
KR102221752B1 (ko) * 2014-03-20 2021-03-02 삼성전자주식회사 메모리 장치의 프로그램 방법 및 이를 포함하는 데이터 독출 방법
US20150311920A1 (en) * 2014-04-25 2015-10-29 Agency For Science, Technology And Research Decoder for a memory device, memory device and method of decoding a memory device
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KR102214556B1 (ko) * 2014-08-19 2021-02-09 삼성전자주식회사 메모리 장치 및 모듈
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KR102231441B1 (ko) * 2014-12-17 2021-03-25 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작 방법
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CN106598499A (zh) * 2016-12-14 2017-04-26 深圳市中博睿存科技有限公司 一种基于fpga的分布式文件系统架构
KR102688433B1 (ko) * 2017-05-07 2024-07-26 에스케이하이닉스 주식회사 메모리 장치, 이를 포함하는 메모리 시스템 및 메모리 시스템의 동작 방법
KR102688423B1 (ko) * 2017-07-05 2024-07-26 에스케이하이닉스 주식회사 메모리 장치, 이를 포함하는 메모리 시스템 및 메모리 시스템의 동작 방법
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI501083B (zh) * 2013-07-03 2015-09-21 Storart Technology Co Ltd 針對快閃儲存系統以bch及ldpc引擎進行檢測與修正錯誤的方法

Also Published As

Publication number Publication date
EP2550661A4 (en) 2013-10-09
CA2791931A1 (en) 2011-09-29
KR20120137416A (ko) 2012-12-20
CN102812519A (zh) 2012-12-05
US9411680B2 (en) 2016-08-09
US9098430B2 (en) 2015-08-04
JP2013522779A (ja) 2013-06-13
WO2011116454A1 (en) 2011-09-29
US20150309867A1 (en) 2015-10-29
EP2550661A1 (en) 2013-01-30
US20110231739A1 (en) 2011-09-22

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