TW201123387A - Thermal-electric separated metal PCB with a chip carrier. - Google Patents

Thermal-electric separated metal PCB with a chip carrier. Download PDF

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Publication number
TW201123387A
TW201123387A TW098144997A TW98144997A TW201123387A TW 201123387 A TW201123387 A TW 201123387A TW 098144997 A TW098144997 A TW 098144997A TW 98144997 A TW98144997 A TW 98144997A TW 201123387 A TW201123387 A TW 201123387A
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Taiwan
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heat
layer
metal
chip
substrate
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TW098144997A
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xiang-hua Wang
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xiang-hua Wang
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Priority to TW098144997A priority Critical patent/TW201123387A/zh
Priority to GB1003477.5A priority patent/GB2476517B/en
Priority to JP2010050081A priority patent/JP2011139008A/ja
Priority to KR1020100021753A priority patent/KR20110074642A/ko
Priority to US12/898,723 priority patent/US20110157834A1/en
Publication of TW201123387A publication Critical patent/TW201123387A/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/053—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an inorganic insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/641—Heat extraction or cooling elements characterized by the materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09054—Raised area or protrusion of metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10106—Light emitting diode [LED]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Led Device Packages (AREA)

Description

201123387 六、發明說明： 【發明所屬之技術領域】 一種「熱電分離之金屬載芯片板.」，尤指—種應 用（但不限）於發光二極體（LED)或相關技術之金屬 載名片板設計。 【先前技術】 按金屬載芯片板（Metal Core-C h ip on board;即MCC0B)是電子產品中最基礎的構件，但 隨著科技的提昇，設於金屬載芯片板上的芯片（晶 片）功能更強’目此發熱的現象也愈趨普遍，以發 光二極體（LED)為例，當照明用的白光 功率愈高，其發熱就愈多，這個發散出二= 需快速的將其排出，才能確保安全及電子零件的壽 命；請參看第8圖所示，是習用的一種金屬載芯片 板’它包含有最底層的散熱基板（8〇)(通常是鋁 板），以及在該散熱基板（8 〇 )的側面壓合有一介 電層（8 1 )( —般使用氧化銘，簡稱為aA〇 )，並 在該介電層（8 1 )上佈設有電性導通層 (Electrical Connection) ( 8 2 )’ 該電性導通層 (8 2 )可以是多層次的設計’具體實施例可分為 第一基層（8 2 1 )(例如：金Au )、第二基層（8 2 2 )(例如··鎳N i )及第三基層（8 2 3 )(例如： 銅Cu ) ’則在該電性導通層（8 2 )上即可設有發 201123387 "極體（L E D )晶片（8 3 )，並打上金線（8 >、電路相通，而形成一完整的電路板，但這種 :構係有缺點的’例如該晶片（8 3 )所產生的熱 月b 1如刖碩所示）係透過該介電層（8 1 )，再傳至金 屬政…、基板（8 〇 )進行散熱，不但散熱速率過慢， 而且政熱基板（80)並未直接與晶片（83)接 觸，'即無:法對形成發熱源的晶片（8 3 )直接散熱’ 所以使侍整個載芯片板均殘留有較多的熱能， 快速”，是其主要缺點。 。月再參看第9圖所示，係為另-種習用載芯片 板結構，主i後基 要係為一種以鋁基板（9 1 )、介電層（9 0)、銅箱（92)所壓合而成，其中該銘基板（9 …乃作為主要散熱之用，而該介電層（90)多 半係採用有機化合物作為隔緣之用，而該銅箔（9 2 )上即可設有晶片等電子電路（圖中未示），在噹 銅落（9 2 )電路中的晶片發熱時，係透過一定厚 度的介電層1、土 而達到鋁基板（9 1 )以進行 散熱，故散埶的#罢& ‘文果仍然不佳，是習用的通見缺點。 因此，習用因A厶 為金屬戴芯片板的散熱不佳，故 需要其他的許多散埶梦 月文…、破置進行散熱，不但浪費空 及資源，且使成本古 頸。 成本阿居不下，是一項極待克服的瓶 【發明内容】 ί 201123387 本發明之主要目的，在設計一種「熱」、「電」分 離之金屬載芯片板，至少包含有： 一散熱基板，在其—側平面設有較凹下的承 载區及相對凸出的銜接部；一介電層’係在該散 熱基板上以化成被覆（Conversion Coating)方式 形成化合物，並覆設於散熱基板的承載區，且言亥 介電層在位於散熱基板的銜接部形成了窗 的導熱區，且該導熱區係與散熱基板的銜接部相 對應設置；一電性導通層係設在介電層上；如此 —來，將晶片設置於該導熱區内，並與電性導通 層作導線跨距聯接，即可使導熱和導電經由不同 路控導體徹底分離，使晶片的熱快速由導熱區直 達於散熱基板進行散熱，而不會干擾到電子零件 的導電傳遞。 【實施方式】 為使貴審查委員能清楚了解本發明之内容，僅 以下列說明搭配圖式，說明如后。 凊參閱第1、2圖所示’本發明之金屬載芯片 板包含有： “ —散熱基板（1 0 )，尤以鋁材基板 ML 4-, ^ 〃丨主’在该 …、基板（10)的適當位置設有較凹下 (Ί r的承載區 丄1 )及相對凸出的銜接部（1 2 )。 介電層（2 0 )’係覆設於散熱基板（ 201123387 承載區（i i ) ’且係以散熱基板（1 〇 )本身經由 化成被覆（Conversion Coating)方式形成化合物’ 例如··氣化鋁或其他氣體所形成的鋁化合物，且該 介電層（2 0 )在位於散熱基板（2 〇 )的銜接部 (工2)形成了窗口狀的導熱區（21)。
該導熱區（2 1 )係與散熱基板（i 〇 )的銜 接部（1 2)相對設置，因此可以依實際的需要而 有不同的形狀設置，以下僅針對導熱區（2丄）的 形狀變化作-說明；則請參看第3圖所示，係設成 為多個（或單個）長條形的導熱區（2 i a )，再靖 參看第4圖所示’係設成多個（或單個）方形（二 狀）的導熱區（2 1 b )，這都是最常用的形式，至 於其他不同的形狀（例如幾何形狀）依然是本案的 特色所在’在此不·一 一贊述。 請參看第1 、2、3 、4圖袖_ , ^ ^ , _所不，半導體導熱 膠（30)係覆設於諸導熱區（2 !wo •丄）（2 1 a ) ( 2 1 b )上，以供如第1圖所示的晶片（5 0 )放置 其上。 請參看第1圖所示，電性導通層⑴此㈣
Connection) (40)係設在介電層（2〇)上；本 發明在使用於發光二極體的半導髀 丁哥體貫施時，可在導 熱區（21)位置的半導體導熱膠（3〇)上設置 發光二極體 性導通層（ 晶片（5 0 )，並打上 4 0 )相接而形成一 金線（6 0 )與電 完整的電路結構， 6 [ 201123387 因此當發光一極體晶片（5 0 )發光後，其熱量如 圖中的箭頭所示’能直接透過半導體導熱膠（3 〇 、 後’即直接由散熱基板（1 〇 )所吸收，使本發明 的金屬載芯片板較習用更具有散熱速率更快的優 點’同時增加零件的壽命’使電路不受到熱能的影 響’使品質更為穩定’為本發明的主要特徵。 請參看第5圖所示，為本發明另一實施例，主 要是在散熱基板（1 〇 〇)的平面位置設有數道凹 下的承載區（1 1〇)，並設有介電層（2〇)，事 實上，該介電層（20)係以化成被覆（conversi〇n Coating)方式形成化合物直接在散熱基板（丄〇 〇 ) 上成型，例如使用：氧化鋁或其他氣體所形成的鋁 化合物，該散熱基板（1 Q 〇)的平面介電層（2 0 )及銜接部（1 2 0 )的適當位置設有濺鍍層（4 2)’該濺鍍層（42)以銅為最佳，其中在介電層 (20)上的濺鍍層（42)上方設佈有電路的電 性導通層（4 1 )，而在銜接部（i 2 Q )上的㈣ 層（4 2 )則在塗設半導體導熱膠（3丄）後再設 日日片（5 1 )’並打上金線（6 〇 )亦具有上述快速 散熱且造成熱、電分離的效果，使熱能從晶片（5 1)的下方直接由熱傳導至散熱基板（100)，但 並不影響電性導通層“"的電路品質。 因此本發明第1圖及第5圖所示之特色，能將 晶片（5 0 )( 5 !)的熱源直接傳導至散熱基板（丄 7 201123387 〇)( 1 00) ’而不是如習用第8 、9圖透過介電 層（8 1 )(9〇)再傳至最底層的散熱基板（80) 或銘基板（9 1 )，故解決了習用散熱不佳的瓶頸。 為使責審查委員能深入明白本發明確實可行， 以下再介紹本發明之製造流程，其步驟如下： 1'請參看第6-1圖所示，首先製作一散熱基板 (1 〇 )’該散熱基板（1 〇 )尤以鋁基板為佳。 2· 請參看第6-2圖所示，在該散熱基板（1 〇) 預先設置的位置塗上遮蔽層（7 0)。 3.請參看第6-3圖所示，將散熱基板（1〇)上 無遮蔽層（7 0 )的部份，以化成被覆 (Conversion Coating)方式形成一定深度的介 電層（2 0 )’本發明的實施例係以氧化為實施 例，可將上述的介電層（2 〇 )以陽極氧化鋁（即 ΑΑ0)作為實際的實施方式。 該介電層（2〇)在散熱基板（1 〇)上 圍成有一個或多個如第2 、3、4圖所示的導 熱區（21)(21 a)(2lb)，用以放置晶 片（圖中未示）。 由於該介電層（2 〇 )除入會蝕入散熱基 板（1 0 )，使散熱基板（i )表面形成承載 區（1 1)及銜接部（12)，同時介電層（2 0 )在成型時亦會向上膨脹而突出於銜接部（工 IS1 2 )。 201123387 -3及6 -4圖所示，去掉遮蔽層（7 具有高度差（H)的介電層（2〇) I 2 )，則如第6 - 5圖所示，將其 5. 請參看篥β ^ _ , ~6圖所示，在散熱基板（丄〇)的 銜接p(l2)上塗設半導體導熱勝（3〇); 並在"電層（2 0 )上佈設電性導通層（4 〇 )。
°月參看第6 — 7圖所示，在銜接部（1 2 ) 的半導體導1 + 守熟膠（3 0 )上方設置發光二極體 U )，並打上金線（6 0 )與電性導通 曰^4〇)相接而形成一完整的電路結構，因 發光一極體晶片（5 〇)發光後，其熱量 士第1圖下方的箭頭所示，能直接透過半導體 導熱膠（In、& 、d ◦)後’即直接由散熱基板（1 〇 ) 所吸收。
4 · 請參看第6 0 ) ’並露出 及銜接部（ 研磨整平。 本發明在第6-5的磨平散熱基板（1 〇) 表面之後，另—種實施例，如第7 - 1、7 - 2 ®所不’先設有一濺鍍層（4 2 )，再接續設置 電性導通展^ / 1、 、增（4 1 )、組設晶片（5 1 )及打金 '線的程序’而形成完整的結構，而晶片（5 1 ) 的熱即由下I吉μ难、 卜万直接傳導至散熱基板（1 〇 〇 )。 隹以上所述者’僅為本發明之較佳實施例而 已並非用以限定本發明實施之範g，其他如：將 本發明的特徵作簡單的材質變化，或形狀的改變， 201123387 即利用本發明的特徵，再利用習用技藝應用而 如此種為了規避本發明，由熟習此技藝人士即成 本發明的說明而作出等效取代或輕易改依 I的變化 者，在不脫離本發明之精神與範圍下之均 /Ar ^ f Cj 梦?_ 夕飾，皆應涵蓋於本發明之專利範圍内。 綜 上 所 述 > 本發 明 能 時 延 長 了 電 子 零 件的 使 用 價 值 又 因 未 曾 公開 而 具 利 的 保 護 乃 爰 依專 利 法 利 之 中 請 〇
提供更佳的散熱效果，同 哥命’具有產業上的利用 有專利之新穎性，應予專 之規定，向鈞局提起專 201123387 【圖式簡單說明】 第1圖係為本發明之使用實施示意圖。 第2圖係為本發明之結構實施例圖（1)。 第3圖係為本發明之結構實施例圖（2)。 第4圖係為本發明之結構實施例圖（3)。 第5圖係為本發明之結構實施例圖（4)。 第6 -1圖係為本發明之製造流程圖1。 第6 -2圖係為本發明之製造流程圖2。 第6 - 3圖係為本發明之製造流程圖3。 第6 -4圖係為本發明之製造流程圖4。 第6 -5圖係為本發明之製造流程圖5。 第6 -6圖係為本發明之製造流程圖6。 第6 - 7圖係為本發明之製造流程圖7。 第7 - 1圖係本發明之製造流程圖之變化例1。 第7 -2圖係本發明之製造流程圖之變化例2。 第8圖係為習知第一種金屬載芯片板結構示意圖。 第9圖係為習知第二種金屬載芯片板結構示意圖。 【主要元件符號說明】 1 0散熱基板 1 1承載區 1 2銜接部 2 0介電層 2 1導熱區 1 0 0散熱基板 1 1 0承載區 1 2 0銜接部 2 0 0介電層 2 1 a導熱區 [S1 201123387 2 1 b 導 敎 區 3 0 半 導 體 導熱 3 1 半 導 體 導熱膠 4 0 電 性 導 通層 4 1 電 性 導 通層 4 2 減 鍍 層 5 0 晶 片 5 1 晶 片 6 0 金 線 7 0 遮 蔽 層 8 0 散 熱 基 板 8 1 介 電 層 8 2 電 性 導 通層 8 2 1 第 一 基層 8 2 2 第 二 基層 8 2 3 第 —- 基層 8 3 晶 片 8 4 金 線 9 0 介 電 層 9 1 鋁 基 板 9 2 銅 箔 h 度 差

Claims (1)

  1. 201123387 七、申請專利範圍： 至少包 1.種「熱電分離之金屬載芯片板結構 含有： -散熱基板，在其一側平面設有較凹下的承 載區及相對凸出的銜接部； 一介電層，係在該散熱基板上以化成被覆 (Conversion Coating)方式所形成的化合物，並
    覆設於散熱基板的承載區，且該介電層在位於散 熱基板的銜接部形成了窗口狀的導熱區，且該導 熱區係與政熱基板的銜接部相對應設置； 一電性導通層係設在介電層上。 2.如申請專利範圍第i項戶斤述之「熱電分離之金屬 載芯片板結構」，其中，該散熱基板為鋁材基板。 又如申請專利範圍第i項所述之「熱電分離之金屬 載芯片板結構」’其中，該導熱區為複數個。 4. 如申請專利範圍第w所述之「熱電分離之金屬 載芯片板結構」，其中，該導熱區為長條形。 5. 如申請專利範圍第丨項所述之「熱電分離之金屬 載芯片板結構」，其中，該導熱區為方形。 6. 如申請專利範圍第丨項所述之「熱電分離之金屬 載芯片板結構」，其中，該散熱基板的銜接部， 於於導熱區的空間塗設有半導體導熱膠。 7.如申凊專利範圍 載芯片板結構」 第1項所述之「熱電分離之金屬 ’其中’該導熱區位置設置有晶 LSI 13 201123387 片。 8. 如申請專利範圍第1項所述之「熱電分離之金屬 載芯片板結構」，其中，該銜接部上覆設有濺鑛 層。 9. 如申請專利範圍第1項所述之「熱電分離之金屬 載芯片板結構」，其中，該介電層與電性導通層 間設有濺鍍層。 ·>
    1 0 _如申請專利範圍第1項所述之「熱電分離之金 屬載芯片板結構」，其中，該散熱基板的導熱區 係為幾何形狀。 11. 一種「熱電分離之金屬載芯片板製造方法」，其 步驟有： (1)製作一金屬散熱基板，並在該散熱基板的_ 部份位置塗上遮蔽層； (2)將散熱基板上無遮蔽層的部份，以化成被覆 (Conversion Coating)方式形成一定深度的 介電層，並使該介電層在散熱基板上圍成有 至少一個導熱區，用以放置晶片；而散熱基 板相對於導熱區形成有銜接部； (3) (4) (5) 去掉遮蔽層，並整平散熱基板的表面 在散熱基板的銜接部上’塗設半導體導埶 膠，並在該介電層上佈設電性導通層； 銜接部的半導體導熱膠上方設置晶片曰，並应 電性導通層作導線跨距聯接，使導孰和導電 201123387 能因經由不同路徑導體分離。 1 2.如申請專利範圍第11項所述之「熱電分離之金 屬載芯片板製造方法」，其中，該介電層為陽極 氧化鋁（即ΑΑ0)。 . 1 3.如申請專利範圍第11項所述之「熱電分離之金 _ 屬載芯片板製造方法」，其中，第（3)步驟之整平 散熱基板的表面之後，插入有塗設濺鍍層的程 序。 . [S1 15
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US20110157834A1 (en) 2011-06-30
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GB2476517A (en) 2011-06-29
JP2011139008A (ja) 2011-07-14

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