TW201044540A - Semiconductor device and method of mounting pre-fabricated shielding frame over semiconductor die - Google Patents
Semiconductor device and method of mounting pre-fabricated shielding frame over semiconductor die Download PDFInfo
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- TW201044540A TW201044540A TW99106840A TW99106840A TW201044540A TW 201044540 A TW201044540 A TW 201044540A TW 99106840 A TW99106840 A TW 99106840A TW 99106840 A TW99106840 A TW 99106840A TW 201044540 A TW201044540 A TW 201044540A
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Description
201044540 六、發明說明: 【發明所屬之技術領域】 本發明概括關於半導體元件,且尤指一種半導體元件 以及在半導體晶粒上配置預先製造的遮蔽框架以隔離電磁 干擾(EMI,electromagnetic interference)與射頻干擾(RFI, radio frequency interference)或其他元件間干擾的方法。 【先前技術】 半導體元件常見於現代電子產品。半導體元件為於電 氣構件的數目與密度而變化。離散的半導體元件通常含有 一個型式的電氣構件,例如:發光二極體(LED,Hght ―㈣、電晶體、電阻器、電容器、電感器與功率加體) 金屬氧化物半導體場效電晶體(M〇SFET,邮…
SemiConductor fleld effect加㈣㈣。積體的半導體元件典 型為含有數百個到數百萬個電氣構件。積體的半導體元件 之實例包括.·微控制器、微處理器、電荷搞合元件⑷CD, charge-coup〗ed device)、太陽能電池與數位微鏡元件 (DMD,digital miCro-mirror device)。 半導體元件實行廣泛範圍的作用,諸如:高速計算、 :送及接收電磁訊號、控制電子元件、轉變陽光為電力及 產生視覺投影以供電視顯像。半導體元件可見於㈣力通 訊、發電、網路、電腦與消費產品之 、 可見於其包括軍事、航空、汽車、如 凡件亦 備之電子產品。 飞車王業控制器與辦公室設 201044540 • 半導體元件利用半導體材料的電氣性質。半導體材料 的原子結構允許其導電性為藉由電場施加或透過摻雜過程 而操縱。摻雜為引入雜質至半導體材料以操縱及控制半^ 體元件的導電性。 一種半導體凡件含有主動與被動的電氣結構。主動結 構(包括:電晶體)控制電流之流通。藉由改變摻雜位準及電 場絲,電晶體促進或限制電流之流通。被動結構(包括: 電ρ且a —極體與電感器)建立於電麼與電流之間的一種關 係,其為必I以實行種種電氣作用。被動與主動結構電氣 連接以形成電路,致使半導體元件為能夠實行高速計算與 其他有用的作用。 &半導體元件通常運用二個複雜的製程所製造,即:前 (^ end)製化與後段(back-end)製造,各者涉及潛在為 數百個步驟。前段製造涉及於半導體晶圓表面的複數個晶 ♦之形《各個晶粒典型為相同且含有其藉由電氣連接主 〇動與被動構件所形成的電路。後段製造涉及自所完成的晶 圓、單幻固別的晶粒且封裝該晶粒以提供結構支撐與環 半導體製以之一個目標為產生較小的半導體元件。較 :的元件典型為消耗較少的功率,具有較高的性能,且可 為較有效率製造。吐冰 „ 卜較小的半導體元件具有較小的使 :間,其針對於較小的最終產品為合意。較小晶粒尺寸 段製程之改良而達成,造成其具有較小、較高密 動與被動構件之晶粒。後段製程可由於電氣互連與 201044540 封裝材料之改良而造成其具有較小的使用空間之半導體元 件封裝。 於同頻的應用,諸如:射頻(RF,radio frequency)無線 通況,積體被動元件(IPD,integrated passive device)經常包 含於半導體元件之内。IPD之實例包括:電阻器、電容器與 電感器。一種典型的射頻系統需要於一或多個半導體封裝 之多個IPD以實行必要的電氣作用。然而,高頻的電氣元 件產生不期望的電磁干擾(EMI)、射頻干擾(RFI)與其他的元 件間干擾,諸如:電容、電感或電導耦合,亦習稱為串音 (cross-talk) ’此將干擾於相鄰電路元件之操作。 於堆疊半導體封裝與外部元件之間的垂直電氣互連可 藉著傳導的石夕通孔(TSV,through silicon via)或通孔(THV, through hole via)而達成。THV藉由鑽孔穿過囊封物且將諸 孔填充導體而形成於環繞元件的周圍區域中。垂直傳導柱 亦可在囊封之前而形成於周圍區域中。二種垂直互連技術 耗費製造時間與費用。 【發明内容】 對於提供垂直電氣互連且進而隔離半導體晶粒為免於 電磁干擾(EMI)、射頻干擾(RFI)與其他元件間干擾的需要為 存在。是以,於一個實施例,本發明為一種製造半導體元 件的方法,包含步驟:提供一預先製造的遮蔽框架丨提供 犧牲性(sacrificial)基板;安裝—半導體晶粒至犧牲性基 板;安裝遮蔽框架在半導體晶粒與犧牲性基板之上;透過 201044540 遮蔽框架而沉藉—臺#仏从 .ΓΛ 囊封物為環繞半導體晶粒;及,移除遮 蔽框架的一第_邱八,、;里+ A ^ 、 。刀暴露囊封物。移除遮蔽框架的第_ 邛幺以保留遮蔽框架的一 A 弟—口P刀在丰導體晶粒之上而作 為免於干擾之遮蔽。該插 種方法更包括步驟:形成一第-互 連結構在半導體晶粒、 i 货遮政框条的第二部分與囊封物的— 第一側之上;移除犧牲性基 .^ 土低,夂,形成一第二互連結構
在半^體晶粒鱼盆相對於香44·4·Ζ_ L 、/、相對於囊封物的第一側之囊封物的一第 二側之上。 步
、、於另一個實施例,本發明為一種製造半導體元件的方 法’包含步驟:提供一預先製造的遮蔽框架;提供一犧牲 土板’安裝半導體晶粒至犧牲性基板;安裝遮蔽框架 在半導體晶粒與犧牲性基板之上;透過遮蔽框架而沉積_ 囊封物為環繞半導體晶粒…移除遮蔽框架的-第一部 ^以暴露囊封物。移除遮蔽框架的第—部分以保留遮蔽框 架的帛一部分在半導體晶粒之上而作為免於干擾之遮 蔽該種方法更包括步驟:形成一第一互連結構在半導體 晶粒、遮蔽框架的第二部分與囊封物的一第一側之上。 於另一個實施例,本發明為一種製造半導體元件的方 包含步驟:提供-預先製造的遮蔽框架;安裝遮蔽框 木在半導體晶粒之上;透過遮蔽框架而沉積—囊封物為 環繞半導體晶粒;纟,移除遮蔽框架的H分以暴露 囊封物而保留遮蔽框架的一第二部分在半導體晶粒之上。 於另一個實施例,本發明為一種半導體元件,其包含 一半導體晶粒及安裝在半導體晶粒之上的預先製造的遮蔽 7 201044540 框架。-囊封物沉積為環繞半導體晶粒。 ^ ,,, 弟一互連結構 形成在囊封物的—第—側、繼架與半導體晶粒之上。 【實施方式】 本發明參考圖式而描述於以下說明的_或多個實施 例,其中,同樣的參考符號代表相同或類似 = 成本發明的目標之最佳模式而描述,將為 解的是:意圖以涵蓋如可為納人於由 隨附的申明專利範圍與以下揭露 .,w ^ + 門谷興圖式所支持的其等 :者所界疋之本發明的精神與範,内的替代、修改與等效 半導體it件通常運用二個複雜的製程所製造:前段製 仏/、後段製造。前段製造涉及 晶粒之形成。㈣圓上的各個曰=晶圓表面的複數個 構件,有主動與被動的電氣 稱仔其為電鐵*連接以形成作用的番,办 如:電晶體)具有能力以控制電/之^主動電氣構件(諸 如:電Γ 通。被動電氣構件(諸 之間的::::器與變壓器)建立於電壓與電流 ’種關係’其為必要以實行電路作用 =與主=件藉由其包括摻雜、沉積、光刻、 Π二處理步驟而形成於半導體晶圓的表面 ^ ^ ,. 或,、、、擴散之技術而引入雜質 導電性,㈣半導體材料成=動:件之半導體材料的 導體’或響應於電場而改變 二的絕緣體、水久的 ¥體材料的導電性。電晶體 201044540 含有變化型式與摻雜程度的區域,其隨著必要而配置以致 使電晶體為能夠於電場施加時而促進或限制電流的流通。 所形ί =動構件為由具有不同的電氣性質之數層材料 曰可猎由其部分為戶斤沉積的材料 種種沉積技術所形成。舉例而言,薄膜沉積及= ::=TVD,che—~ Ο
G 程。各層:常:vap°r:p°sltl°n)、電解電鍍及無電電鑛過 …:成部分的主動構件、被動構件 或於構件之間的電氣連接。 光敏=可運用光刻法所圖案化,光刻法涉及例如光阻的 先敏材枓之沉積於將作圖案 光線而轉移自-光罩至光阻乂“ )運用 先p 。又到光線之光阻圖案部分運 孝浴刈所移除,暴露將作圖g 移除光阻料餘_ @ 案化之下面層的部分者。 1…: 圖案化層。或者是…型 式的材料藉由直接沉積材 一1 法的技術之—種P材料至其運用諸如無電及電解電鑛 圖案化。 先别沉魏刻過程所形成的區域或空隙而 沉積一薄臈的材料於現存的圖案上可能擴 圖案且產生一不均勾平㈣而㈣上U廣大在下面的 生較小且較密隼封^ 均勾平坦表面需要以產 移除自晶圓動與被動構件。平面化可運用以 及磨光曰生一均勾平坦表面。平面化涉 φ Μ a a ^ a jl 磨先墊。一種研磨材料與腐蝕化 干衣οσ為於磨朵如pq 用與化學製品的腐:作:加至晶圓表面1磨料的機械作 用之組合者移除任何不規則的拓撲 9 201044540 結構,造成一均勻平坦表面。 後段製造是指㈣完成的_㈣ 的晶粒且接著封裝該晶粒以供結構 =為個別 晶粒單-化,晶圓沿著稱為鑛道:,隔離。欲將 域而刻劃及切斷。晶圓運用一種雷射;的非作用區 -化。在單-化之後,個別晶粒安 括接腳或接㈣以供互連於其他的系統構件。形 = :晶粒之上的接觸墊接著連接至於封裝内的接觸墊。電氣 連接可藉著焊塊、柱塊'導電糊膏或線接合而作成。^ 囊封物或其他的模製材料沉積於封裝之上以提供實 ::氣隔離。完成的封裝接著插入至一種電氣系統:該半 導體7L件的功能性成為可用於其他的系統構件。 圖1為說明電子元件10,其具有一晶片載體基板或印 刷電路板(PCB,printed circuit b〇ard) 12,印刷電路板 12 具有安裝於其表面之複數個半導體封裝。電子元件Μ可具 有-個型式的半導體封裝、或多個型式的半導體封裝,視 應用而定。不同型式的半導體封裝為了說明而顯示於圖卜 電子兀件10可為一種獨立系統,其運用該等半導體封 裝以實打-種電氣作用。或者是,電子元件1G可為—較大 系統的一個子構件。舉例而言,電子元件10可為一圖形卡、 網路介面卡或其可為插入至電腦之其他的訊號處理卡。半 導體封裝可包括:微處理器、記憶體、特定應用積體電路 (ASIC,application specific imegrated 士⑶⑴、邏輯電路、 類比電路、射頻電路、離散元件或其他的半導體晶粒或電 10 201044540 氣構件。 於圖1,PCB 12提供一種通用的甚拓
艰用旳基扳以供其安裝於PCB 、、導體封裝之結構支撲及電氣互連。傳導訊號線跡^運 用蒸鑛、電解電鍍、無電電鍍、網印、pvD或其他適合金 屬沉積過程而形成在PCB 12的一表面上或於咖Μ的諸 層内。訊號線跡14提供於各個半導體封裝、安裝 i 他外部系統構件之_電氣料。線跡14亦提供對於;;個 半導體封裝之電力與接地連接。 於一些實施例,一種半導體元件具有二個封裝階層。 第一階層封裝為用於機械及電氣式附接半導體晶粒至一載 體的-種技術。第二階層封裝涉及:機械及電氣式附接該 載體至PCB。於其他實施例,一種半導體元件可僅具有第 一階層封裝,其中,該晶粒為機械及電氣式直接安裝至pcB。 為了說明,數個型式的第一階層封裝顯示於pCB 12, 包括:線接合封裝16與倒裝晶片18。此外,數個型式的第 ^二階層封裝顯示為安裝於PCB12,包括:球栅陣列(BGA, ball grid array) 20、塊形晶片載體(BCC,bump cMp carrier) 22、雙列直插封裝(Dip ’ dual in-line package) 24、岸柵陣 列(LGA ’ land grid array) 26、多晶片模組(MCM,multi-chip module) 28、四面扁平無引線封裝(QFN,quad flat non-leaded package) 30與四面扁平封裝32。視系統需求而 定’任何組合的第一與第二階層封裝型式所構成之任何組 合的半導體封裝以及其他的電子構件可連接至PCB 12。於 一些實施例’電子元件1〇包括單一個附接的半導體封裝, 201044540 7其他實施例為需要多個互連的封裝。藉由組合一或多個 =體封裝在單一個基板之上,製造業者可將事先作成的 入至電子元件及系統。因為半導體封裝包括複雜的 功能性,電子jI + , 運用較便宜的構件及一種有效率的製 ^ ^ Ο造成的元件為較不可能失效且較不昂貴以製 造’造成對於消費者之較低的成本。 圖2a說明其安裝於pCB 12之⑽μ的進一步細節。 3了:括包括其具有接觸墊%之半導體晶粒34。半導體晶粒 二主動區域,其含有類比或數位電路而實施為主 34兀之内且破動'件、傳導層與介電層’形成於半導體晶粒 ^ 4根據晶粒的電氣設計而電氣互連。舉例而言, 该電路可包括:一或多一 器、電P且哭“ $體-極體、電感器、電容 ::阻-與其形成於晶粒34之主動區域内的其他電路元 糾。觸墊36為以_種傳導村料所作成,諸如:链⑷)、 :二、錫(Sn)、錄(Nl)、金(Au)或銀(Ag),且為電氣連接 ,、>成於晶,粒34之内的電路元件。接㈣%藉由⑽、 ,、電解電鑛或無電電鑛過程所形成。於⑽& 期間,半導體晶粒34運用一種金_矽的:裝 化物的黏著材料而安裝至一載體U。封裝本體包括 諸如:聚合物或陶導體引線4。連接至載 =二線接合42形成於引線4。與晶粒34的接觸』 =:層封裝。囊封物44沉積在封裝上以供環 34、接觸’亏杂晶粒 、或線接合24藉由插入引線40至 12 201044540 其形成穿過PCB 12的孔而連接至PCB 12。焊料Μ流通環 繞引線40且進入孔以實際及電氣式連接Dn> ^至 12。焊料46可為任何的金屬或導電材料,例如:如、鉛(抑)、 Au、Ag、Cu、辞(Zn)、鉍(Bi)與其合金,具有一種選用的 助熔材料。舉例而[焊料可為共熔Sn/Pb、高鉛或無鉛c 圖2b說明其安裝於%312之3(^22的進一步細節。 半導體晶粒47藉由線接合型式的第_階層封裝而連接至—
載體。BCC 22以一種bcc型式的第 二階層封裝而安裝 至
PCB 12。具有接觸塾48之半導體晶粒心運用—種底部填 充(underfill)或環氧樹脂的黏著材料5〇而安裝在一載體 上。半導體晶粒47為包括:一主動區域,其含有類比或數 位電路而實施為主動元件、被動元件、傳導層與介電層, 形成於半導體晶粒47之内且為根據晶粒的電氣設計而電氣 互連。舉例而t,該電路可包括:一或多個電晶體、二極 體、電感器、電容器、電阻器與其形成於晶粒〇之主動區 域内的其他電路元件。接觸塾48以-種傳導材料所作成, 諸如.A卜Cu、Sn、Ni、Au $ Ag,且為電氣連接至其形 成於晶粒47之内的電路元件。接觸墊48藉由pvD、cVD、 電解電鍍或無電電鍍過程所形成。線接合54及接合塾% 與58電氣連接半導體晶粒47的接觸塾48至歡η的接 觸墊52而形成第-階層封裝。模製化合物或囊封物60沉 積在半導體曰曰粒47、線接合54、接觸墊48與接觸墊之 上,以提供針對㈣元件的實際支#及電氣隔離。接觸塾 “運用蒸鍍、電解電鍍、無電電鍍、網印、pvD或其他適 13 201044540 積巧種而形成在PCB 12之—表面上 以防止氧化。接觸墊64電氣連接至…:為電鑛 14。焊n |㊄孔連接至-或多個傳導訊號線跡 於BCC 22的接觸塾52與PCB 12的接㈣ …料回流以形成凸塊66,其形成於BCC2Upcb 12之間的機械及電氣連接。 /、 於圖2c ’半導體晶粒i 8以一種倒裝晶片型式的第一階
層封裝而安裝為面對朝下至載體76。bga 2〇以一種BGA 型式的第二階層封裝而附接至pCBi2。主動區域%含有類 比或數位電路而實施為主動㈣、被動元件、傳導層與介 電層1成於半導體晶粒18之内且為根據晶粒的電氣設計 而電氣互連。舉例而言,該電路可包括:一或多個電晶體、 二極體、電感H、電容器、電阻器與其形成於半導體晶粒 18的主動區域7〇之内的其他電路元件。半導體晶粒18透 過大量個別傳導焊塊或$ 78 Μ氣及機械式附接至載體 76。焊塊78形成在其配置於主動區域7〇的凸塊墊或互連 位置80之上。凸塊墊8〇以一種傳導材料所作成,諸如: Α卜Cu、Sn、Ni、An或Ag,且為電氣連接至其形成於主 動區域70的電路元件。凸塊墊8〇藉由pVD、cvd、電解 電鍍或無電電鍍過程所形成。焊塊78藉由一種焊料回流過 程而電氣及機械式連接至於載體76的接觸墊或互連位置 82 ° BGA 20藉由大量個別傳導焊塊或球%而電氣及機械 式附接至PCB 12 ^焊塊形成在凸塊墊或互連位置84之上。 凸塊墊84透過其路由通過載體76之導線9〇而電氣連接至 14 201044540 互連位置82。接觸墊88運用蒸鍍、電解電鍍、無電電鍍 網印、PVD或其他適合金屬沉積過程而形成在pcB 12之一 表面上且典型為電鍍以防止氧化。接觸墊88電氣連接至一 或多個傳導訊號線跡14。焊塊86藉由一種焊料回流過程而 電氣及機械式連接至於PCB 12的接觸墊或接合墊88。模製 化合物或囊封物92沉積在半導體晶粒丨8與載體76之上, 以提供針對於該元件的實際支撐及電氣隔離。倒裝晶片式 半導體元件提供自於半導體晶粒18的主動元件至於PCB I2的傳導軌跡之一短的導電路徑’藉以縮小訊號傳播距 離、降低電容及改良整體電路性能。於另一個實施例,半 導體晶粒18可運用倒裝晶片型式的第一階層封裝且無載體 76而機械及電氣式直接附接至ρ〇Β 12。 圖3a至3g說明一種形成於一扇出晶圓階層晶片尺度封 ^ (FO-WLCSP ^ fan-out wafer level chip scale package)^ ^ 具有置放在半導體晶粒上的預先製造的遮蔽層之半導體封 裝的過程。於圖3a,一犧牲性的基板或載體1〇〇含有暫置 或犧牲性的底座材料,諸如:矽、聚合物、聚合複合物、 金屬、陶瓷、玻璃、玻璃環氧化物、氧化鈹、《用於結構 支撐之其他適合的低成本、剛性的材料或塊狀半導體材料。 一介面層102為以熱或光能釋放的暫時接合膜而施加 至載體100。介面層102可為具有濕式蝕刻選擇性之一或多 層的二氧化矽(si〇2)、氮化矽(以川4)、氮氧化々(si〇N)、有 機膜或金屬膜。介面層102運用疊合、pVD、CVD、印製、 旋轉塗覆、噴灑塗覆、燒結或熱氧化而沉積。介面層⑽ 15 201044540 可為一暫時的接合膜或蝕刻阻止層β 半導體晶粒104安裝至介面層1〇2。各個半導體晶粒 刚包括類比或數位電路,其實施為形成於頂側主動表面 且根據晶粒的電氣設計而電氣互連之主動與被動元 件、傳導層與介電層。舉例而言,該電路可包括:一或多 個電晶體、二極體與形成於主動表面⑽之内的其他電路 元件’以實施基頻數位電路,諸如:數位訊號處理器(Dsp, c^gUal signal process〇r)、記憶體或其他訊號處理電路。半 導體晶粒1G4亦可含有用於射頻(RF)訊號處理之積體被動 元件(IPD),諸如:電感器 '電容器與電阻器。接觸墊⑽ 電氣連接至於半導體晶纟1G4的主動表s iQ6之㈣主動 與被動元件與訊號線跡。 >於半導體晶粒1G4@ IPD提供針對於高頻應用所需的 電氣特諸如.共振器、高通遽波器、低通滤波器、帶 通,波器、對稱高品f(Hi_Q)共振變㈣、匹配網路與調言皆 電容器》IPD可運用作為前端的無線射頻構件,其可定位於 天線與收發器之間。IPD電感器可為其操作於高達⑽千死 赫兹(GHz)之-種高品f的平衡不平衡轉換器咖㈣、變壓 器或線圈。於一些應用’多個平衡_不平衡轉換器形成於同 一個基板,允許多頻帶的操作。舉例而言,二或多個平衡_ 不平衡轉換H運用於針對於行動電話或其他的全球行動通 Ifl (GSM . global system for mobile communication)^ _ 四頻帶(quad-band)’各個平衡_不平衡轉換器專用於四頻帶 元件之一個頻帶的操作。 16 201044540 一種典型射頻(RF)系統需要於一或多個半導體封裝之 多個IPD與其他高頻電路以實行必要的電氣作用。高頻電 氣元件產生或易感受到不期望的電磁干擾(EMI)、射頻干擾 (RFI)或其他的元件間干擾,諸如:電容、電感或傳導搞合, 亦習稱為串音(cr0SS-talk),其可能干擾相鄰或附近的電路元 件之操作。 頂无裂造的遮蔽框架110安 欲降低元件間的干擾 〇 裝在半導體晶粒104與介面層102之上,如於圖3&與31) 所不。遮蔽框架110包括一平板lu及複數個本體U4a_ U4f,其整合於板U1且由腔部116所分開。本體ιΐ4&、 14c 114d與114f為充分厚以朝下延伸至介面層I。〗。本 體114a、114c、l14d與114f將成為傳導柱,如下所述。本 體114b與114e相較於本體U4a、U4c、丨丨牝與u4f為較 薄以容納半導體晶粒1〇4。複數個開口丄i2形成通過板】η 至腔β 11 6。遮蔽框架丨丨G可為Cu、Α卜鐵氧體或幾基鐵、 不錢鋼、鎳銀、低碳鋼、石夕鐵鋼、羯片、環氧化物、傳導 樹脂及其能夠阻斷或吸收EMI、R_其他干擾的其他金屬 與複合物。遮蔽㈣11G亦可為—非金屬材料,諸如:碳 黑或銘薄[以降低刪與RFI的效應。遮蔽框架ιι〇的 f體⑽與1146接觸相對於主動表面⑽之半導體晶粒 的背表面。在安襄遮蔽框架11〇之前,—選用式的黏 者或熱介面材料可施加至半導體晶粒HM的背表面。 圖3e顯示-種囊封物或模製化合物ιΐ8為運用一種糊 P製、壓縮模製、轉移模製、液體囊封物模製、真空疊 17 201044540 合或其他適合施加器而沉積在半導體晶粒1〇4與介面層ι〇2 之上。囊封過程透過開口 112而將囊封物118為散佈至遮 蔽框架110之下方的腔部116。囊封物118可為聚合物複合 材料,堵如.具有填料的環氧樹脂、具有填料的環氧丙烯 酸酯或具有適當填料的聚合物。囊封物118為非傳導性且 %境保護半導體元件為免於外部元件與污染物的損害。 於圖3d’研磨機.120移除其包括板hi之遮蔽框架ho 的一部分而朝下至開口 U2,以暴露於腔部116之囊封物 118。遮蔽框架110的本體1141)與114e維持在半導體晶粒 104的背表面之上,以提供針對於晶粒之期望的EMI與R耵 Pw離。半導體晶粒1 04之間的遮蔽框架丨丨〇的其餘部分成 為用於垂直z方向的互連之傳導柱或樁114a、U4c、n4d 與 U4f 〇 於圖3e,一頂側建立的互連結構124形成在囊封物 118、遮蔽框架110的本體1141?與n4e及傳導柱 114c、114d與114f之上。建立的互連結構124包括一導電 層126 ’其運用一種圖案化與沉積過程以片段或部分而形成 在遮蔽框架110及傳導柱114a、114c、114(1與114f之上。 導電層126運用PVD、CVD、電解電鍍、無電電鍍過程或 其他適合金屬沉積過程而形成。導電層126可為一或多層 的A卜Cu、Sn、Ni、Aii、Ag或其他適合導電材料。導電 層126的一個部分電氣連接至傳導柱114a、114c、U4d與 114f。導電層126的其他部分可為電氣共同或電氣隔離,視 半導體晶粒的設計與作用而定。 18 201044540 、絕緣或鈍化層128形成在囊封物118、遮蔽框架⑽ 的本體㈣與心及導電層126之上。絕緣層128可為一 或夕層的SiC^、Sl3N4、Si0N、五氧化二纽叫〇5)、氧化紹 (ai2〇3)或其具有類似絕緣與結構性f的其他材料' 128運用pvd、CVD、制热綸备帝 、、曰 D印I、杈轉塗覆、噴灑塗覆、燒結或 …氧化而沉積。絕緣層128的一部分藉由,刻過程而 移除以暴露導電層126。 —導電I 130運用-種圖案化與沉積過程以片段或部 分而形成在絕緣層128與導電層126之上。導電層可 為-或多層的八卜心^^岣或其他適合導電 材料。導電層130的一個部分電氣連接至導電層126。導電 層130#其他部分可為電氣共同或電氣隔冑,視半導體元 件的設計與作用而定。 一絕緣或鈍化層132形成在絕緣層128與導電層 之上。絕緣層132可為一或多層的叫、叫仏、_Ν、 〇 Ta2〇5、Αΐ2〇3或其具有類似絕緣與結構性質的其他材料。 絕緣層U2運用PVD、CVD、印製、旋轉塗覆、喷灌塗覆、 燒結或熱氧化而沉積。解绦厣η,从 # ^ 把•緣層132的一部分藉由一種蝕刻 過程而移除以暴露導電層13〇。 …於圖3f ’基板100與介面層1〇2藉由化學敍刻、機械 脫落、CMP、機械研磨、熱烘烤、雷射掃描或濕式剝除而 移除底側建立的互連結構1 34形成在囊封物丨丨8、半導 體晶粒HM及傳導柱^、^、⑽與⑽之上。建立 的互連結構134包括一導電層136,其運用一種圖案化與沉 19 201044540 積過程以片段或部分而形成在囊封物i丨8及傳導柱i丨4a、 114c、114d與114f之上。導電層136運用Pvd、CVD、電 解電鍍、無電電鍍過程或其他適合金屬沉積過程而形成。 導電層136可為一或多層的a卜Cu、Sn、Ni、au、Ag或 其他適合導電材料。導電層136的一個部分電氣連接至傳 導柱114a、114c、11牝與114f。導電層136的其他部分可 為電氣共同或電氣隔離,視半導體晶粒的設計與作用而定。 一絕緣或鈍化層138形成在囊封物118、半導體晶粒 1〇4與導電層136之上。絕緣層138可為一或多層的叫、 Si3N4、SiON、Ta205、Al2〇3或其具有類似絕緣與結構性質 的其他材料。絕緣層138運用PVD、CVD、印製、旋轉塗 覆、喷濃塗覆、燒結或熱氧化而沉積、絕緣層138的一部 分藉由一種蝕刻過程而移除以暴露導電層136。 一導電層140運用-種圖案化與沉積過程以片段或部 分而形成在絕緣層138與導電層m之上。導電層140可
:-或多層的Ai、Cu、Sn、Ni、Au、Ag或其他適合導電 :科。導電層140的一個部分電氣連接至導電層136。導電 :140的其他部分可為電氣共同或電氣隔 件的設計與作用而定。 干导體7G 一絕緣或純化層1 4 2形成力紹祕ja 7成在名緣層138與導
之上。絕緣層142可Λ —弋夕成l C
Ta…:了為或多層的叫、Sl3N4、Si〇N、 2〇5、Ah〇3或其具有類似絕緣與結 m ^ & λ 舟丨王貝的其他材料。 ;緣層142運用PVD,、印製、旋轉塗覆、噴m塗二 疋結或熱乳化而沉積。絕緣層142 、是 〇丨刀错由—種蝕刻 20 201044540 過程而移除以暴露導電層140β -導電焊料運用一種蒸鍍 滴或網印過鞋&t 电鮮电鍍、無電電鍍、球 ”過程而沉積在導電層140 金屬或導電絲极知科可為任何的 金,且Γ科’例如:Snw、Am、wu
Sn/Pb /選用的助溶材料。舉例而言,焊料可為絲 回心;π或無錯。焊料藉由將材料加熱為高於其炫點而 口洲·以形成圓球或凸塊丨 -LV ή „ 一愿用,烊塊144回流第 Ο Ο 一-人以改良對於導電層14〇之電氣接觸。 半導體晶粒104以鑛條或雷射切割裝置146而單一化 為個別的半導體元件15〇,如於圖坫所示。在單一化之後, 可堆叠個別的半導體元件15〇,如於圖4所示。傳導柱U4a、 114c、ll4d與li4f提供於頂側互連建立層124與底側互連 建立層134之間的z互連。導電層126與13〇透過傳導柱 U4a與114c而電氣連接至導電層136與14〇及半導體晶粒 的接觸墊1〇8。遮蔽框架11〇的本體U4b與提供 針對於半導體晶粒1〇4的隔離而免於EMI、RFI與其他元件 間干擾。遮蔽框架110的本體U4b與114e可透過互連結構 124與134或傳導柱U4a、114c、lHd與11付而連接至一 低阻抗的接地點。遮蔽框架110的本體114b與lHe免除需 要單獨的EMI遮蔽(如於先前技術所見),其增加對於製程 的時間與成本。遮蔽框架110的本體114b與114e亦提供由 半導體晶粒104所產生的熱量之消散。遮蔽框架11〇的本 體114a、114c、114d與114f連接於互連結構124與134之 間的傳導柱。 21 201044540 圖5顯示半導體元件的另一個實施例❶於此例,半導 體疋件152包括其形成於半導體晶粒1〇4之矽通孔(tsv) 154矽通孔1 54藉由蝕刻或鑽孔一通孔為通過半導體晶粒 1〇4的石夕材料且以A】、Cu、Sn、Ni、Au、々、欽⑺)、鎮 (w)或其他適合導電材料而填充該通孔所形成。遮蔽框架 的本體114b與114e透過石夕通孔154而電氣連接至接觸 墊108與互連結構134。是以,矽通孔154提供自遮蔽框架 110的本體114b與U4e為透過接觸墊1〇8與互連結構134 至一外部的低阻抗接地點之一傳導路徑。 圖6顯示半導體元件16〇,其具有方位為面朝上之半導 體晶粒104的主動表面1〇6與接觸墊1〇8。接觸墊ι〇8透過 接合線162而電氣連接至互連結構13扣接合線166可為一 或多層的A卜Cu、Sn、Ni、Au'岣或其他適合導電材料。 圖7顯示半導體元件164,其具有形成於互連結構124 與134之間的附加遮蔽層166。遮蔽層166可為&、A1 ' 不銹鋼、鎳銀、低碳鋼、矽鐵鋼 '箔片、環氧化物、傳導 樹脂及其能夠阻斷EMI、RFI與其他元件間干擾的其他金屬 與複合物。 儘管本發明之-或多個實施例為已經詳細說明,熟悉 此技術人士將理解的是:對於彼等實施例的修改與調適可 作成而未脫離如以下申請專利範圍所陳述之本發明的範 疇。 【圖式簡單說明】 22 201044540 圖1為說明一種具有安梦於立志 之印刷電路板(PCB); 歧 圖2a至2c為說明其安奘於prR沾也士 , 之進-步細節;dMPCB的代表的半導體封裝 ,圖3a至3g為說明一種在半導體晶粒上形成預先製造的 遮蔽框架的方法; 圖4為說明其具有預先製造的遮蔽框架之堆疊式扇出 晶® 層晶片尺度封裝(FQ_WLCSP),遮蔽框架為安裝在半 導體晶粒之上且互連於傳導柱; 圖5為說明其具有半導體晶粒之f〇_wlcSP,半導體 晶粒具有矽通孔(TSV)以將遮蔽框架接地; 圖6為說明其具有接合線之f〇_wLCSP,接合線連接 於半導體晶粒接觸墊與底側互連結構之間;及 圖7為說明其具有附加遮蔽層之FO-WLCSP,遮蔽層 環繞半導體晶粒而形成於頂側與底側的互連結構之間。 【主要元件符號說明】 10 電子元件 12 印刷電路板 14 訊號線跡 16 線接合封裝 18 倒裝晶片 20 球柵陣列 22 塊形晶片載體 23 201044540 24 雙 列 直插 封 裝 26 山 厗 栅 陣 列 28 多 晶 片 模 組 30 四 面 扁 平 無 引線封裝 32 四 面 扁 平 封 裝 34、 47 半導體晶粒 36、 48 、52、64、88 接觸墊 38 ' 76 載體 40 導體引線 42 > 54 線接合 44 囊封物 46 焊料 50 底部填充或環氧樹脂黏著材料 56、 58 接合墊 60 ' 92 模製化合物或囊封物 66 凸塊 70 主動區域 78 ' 86 焊塊或球 80 凸塊墊 82 接觸墊或互連位置 84 凸塊墊或互連位置 90 導線 100 基板或載體 102 介面層 24 201044540 104 半導體晶粒 106 主動表面 108 接觸墊 110 遮蔽框架 111 平板 112 開口 114a-l 14f 本體 116 腔部 118 囊封物或模製化合物 120 研磨機 124、134 互連結構 126、130、136、140 導電層 1 28、1 32、1 38、142 絕緣或鈍化層 144 焊塊 146 鋸條或雷射切割裝置 150、152、160、164 半導體元件 154 矽通孔(TSV) 162 接合線 166 遮蔽層 25
Claims (1)
- 201044540 七、申請專利範圍: 1. 一種製造半導體元件的方法,包含: 提供一預先製造的遮蔽框架; 提供一犧牲性基板; 安裝一半導體晶粒至該犧牲性基板; 安裝該遮蔽框架在該半導體晶粒與犧牲性基板之上; 透過該遮蔽框架而沉積一囊封物為環繞該半導體晶 粒; 移除該遮蔽框架的一第一部分以暴露該囊封物,其 中’移除該遮蔽框架的第一部分以保留該遮蔽框架的一第 二部分在該半導體晶粒之上而作為免於干擾之遮蔽; 形成一第一互連結構在該半導體晶粒、該遮蔽框架的 第二部分與該囊封物的一第一側之上; 移除該犧牲性基板;及 形成一第二互連結構在該半導體晶粒與其相對於該囊 封物的第一側之該囊封物的一第二側之上。 2. 如申請專利範圍第丨項之方法,其中,移除該遮蔽框 架的第一部分以保留環繞該半導體晶粒之遮蔽框架的一第 三部分’提供電氣連接於第—與第二互連結構之間的一傳 導柱。 3 _如申請專利範圍帛2項之方法,更包括: 堆疊複數個半導體元件;及 透過該傳導柱而電氣連接該等堆疊的半導體元件。 如申明專利1已圍第1項之方法,更包括:提供通過該 26 201044540 遮蔽框架的一開口以將該囊封物散佈至遮蔽框架之下方的 腔部。 5. 如申請專利範圍第1項之方法,更包括:形成於該半 導體aa粒的一碎通孔以將該遮蔽框架接地。 6. 如申請專利範圍第1項之方法,更包括:形成於該半 導體晶粒的接觸墊與第二互連結構之間的一接合線。7. 如申請專利範圍第丨項之方法,更包括:形成於第一 與第二互連結構之間而環繞該半導體晶粒的一遮蔽層。 8. —種製造半導體元件的方法,包含: 提供一預先製造的遮蔽框架; 提供一犧牲性基板; 安裝一半導體晶粒至該犧牲性基板; 安裝該遮蔽框架在該半導體晶粒與犧牲性基板之上; 透過該遮蔽框架而沉積一囊封物為環繞該半導體晶 粒; 移除該遮蔽框架的一第一部分以暴露該囊封物,其 中,移除該遮蔽框架的第一部分以保留該遮蔽框架的一第 二部分在該半導體晶粒之上而作為免於干擾之遮蔽;及 少取一第 第二部分與該囊封物的一第一側之上。 9.如申請專利範圍第8項之方法,更包括:形成一負 互連結構在該帛導體晶粒與其相對於該囊封物的第一相 該囊封物的一第二側之上。 更包括:形成於第 10·*!申請專利範圍第9項之方法 27 201044540 一與第二互連結構之間 L ^ 衣、,免β玄+導體晶粒的一遮蔽層。 11. 如申請專利範圍第9 >如以松 貝<方法,其中’移除該遮蔽 框架的第一部分以保留環繞 \ 衣現4 +導體晶粒之遮蔽框架的一 第二。Ρ釦’提供其連接於第一 上 乐與第二互連結構之間的一傳 導柱。 12. 如申請專利範圍第 只I方法,更包括: 堆疊複數個半導體元件;及 透過該料柱而電氣連接該等堆疊的半導體元件。 13. 如申請專利範圍第8項之方法,更包括:提供通過 該遮蔽框架的一開口以將續壸 亥囊封物散佈至遮蔽框架之下方 的腔部。 14. 如申請專利範圍第8瑁 ^ 項之方法’更包括··形成於該 半導體晶粒的-矽通孔以將該遮蔽框架接地。 15. 種製造半導體元件的方法,包含: 提供一預先製造的遮蔽框架; 安裝該遮蔽框架在一半導體晶粒之上; 粒 透過该遮敝框架而沉積—囊封物為環繞該半導體晶 及 移除該遮蔽框架的-第一部分以暴露該囊封物而保留 該遮蔽框架的一第二部分在該半導體晶粒之上。 如申請專利範圍第15項之方法,更包括: 卜形成第一互連結構在該半導體晶粒、該遮蔽框架的 第二部分與該囊封物的一第一側之上;及 形成第一互連結構在該半導體晶粒與其相對於該袭 28 201044540 封物的第一侧之該囊封物的一第二側之上。 ‘ 17.如申請專利範圍第15項之方法,其中,移除該遮蔽 框架的第一部分以保留環繞該半導體晶粒之遮蔽框架的一 第三部分以提供一傳導柱。 18.如申請專利範圍第17項之方法,更包括: 堆疊複數個半導體元件;及 透過該傳導柱而電氣連接該等堆疊的半導體元件。 19•如中請專利範圍第15項之方法,更包括:提供通過 該遮蔽框架的一開口以將該囊封物散佈至遮蔽框架之下方 的腔部。 、…20.如申請專利範㈣15項之方法,更包括:形成於該 半導體晶粒的一矽通孔以將該遮蔽框架接地。 21. —種半導體元件,包含: 一半導體晶粒; 一預先製造的遮蔽框架,安裝在該半導體晶粒之上; Q 一囊封物,沉積為環繞該半導體晶粒;及 -第-互連結構,形成在該囊封物的一第一側、遮蔽 框架、與半導體晶粒之上。 22. 如申請專利範圍第21項之半導體元件’更包括:一 第二互連結構’其形成在該半導體晶粒與相對於該囊封物 的第一側之該囊封物的一第二側之上。 23. 如申請專利範圍第22項之半導體元件,更包括:一 傳導柱,其形成為環繞該半導體晶粒’該傳導柱為該遮蔽 框架的一部分。 29 201044540 24. 如申請專利範圍第23項之半導體元件,更包括:複 數個半導體元件,其透過該傳導柱而電氣連接。 25. 如申請專利範圍第21項之半導體元件,更包括:一 矽通孔,其形成於該半導體晶粒且電氣連接至該遮蔽框架。 八、圖式. (如次頁) 30
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-
2010
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- 2010-02-22 SG SG10201509258TA patent/SG10201509258TA/en unknown
- 2010-03-10 TW TW099106840A patent/TWI553816B/zh active
-
2012
- 2012-01-13 US US13/350,692 patent/US9406619B2/en active Active
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Also Published As
Publication number | Publication date |
---|---|
US8097489B2 (en) | 2012-01-17 |
US20100237477A1 (en) | 2010-09-23 |
SG10201509258TA (en) | 2015-12-30 |
US9406619B2 (en) | 2016-08-02 |
US20120112328A1 (en) | 2012-05-10 |
SG165239A1 (en) | 2010-10-28 |
TWI553816B (zh) | 2016-10-11 |
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