TW201027627A - Method for forming copper wiring in semiconductor device - Google Patents

Method for forming copper wiring in semiconductor device Download PDF

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Publication number
TW201027627A
TW201027627A TW098143804A TW98143804A TW201027627A TW 201027627 A TW201027627 A TW 201027627A TW 098143804 A TW098143804 A TW 098143804A TW 98143804 A TW98143804 A TW 98143804A TW 201027627 A TW201027627 A TW 201027627A
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Taiwan
Prior art keywords
insulating film
copper
tungsten
forming
bottom insulating
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TW098143804A
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English (en)
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Rae-Cho Kweng
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Dongbu Hitek Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

201027627 六、發明說明： 【發明所屬之技術領域】 本發明係關於-種半導體裝置之鋼導線形成方法，並且特別 地’本發於-種料體裝置之__成絲，其能夠在一 形成銅導線的單鑲嵌製程之中防止銅導線之間的短路。 【先前技術】 與正在進行的半導體裝置之尺寸減少有關，銅導線之賊面 減少’並且目此電流錢增加。雖由於電辦（Ele翻响加⑽， EM)可在金屬導線之中產生低可靠性的嚴重問題。因此，相比較 於銘（A1)具有更低之電阻’並且具有良好歡性_可用作金 屬導線之材料。 然而’由於製造易揮發化合物之困難，使用乾姓刻製程不能 約製造銅導線。因此銅導線主要使用一鑲嵌製程製造。以下，將 結合圖式部份描述一習知技術之單鑲嵌製程。 第1A圖」至「第if圖」係為一習知技術之單鑲嵌製程之 各二驟之Dij視圖。如「第1A圖」所示，—底絕緣膜⑺可沉積於 半導體基板之頂部之上。可選擇性地姓刻底絕緣膜1〇用以形成 複數個過孔11。 然後，如「第1B圖」所示，鎢2〇可沉積於底絕緣膜1〇與這 二過孔11 (如「第1A圖」所示）之全部表面之上。其後，如「第 」斤丁透過執行一化學機械研磨（Chemical Mechanical 201027627
Polishing，CMP)製程用以去除底絕緣膜10之上過度沉積的鎢20， 可形成複數個鎢插塞21。 如「第1D圖」所示，一頂絕緣膜30可沉積於底絕緣膜1〇 之頂部的全部表面之上。然後，如「第1E圖」所示，可選擇性地 蝕刻頂絕緣膜30用以形成複數個溝道31。 如「第1F圖」所示，銅40可沉積於頂絕緣膜30與這些溝道 31之全部表面之上。然後，如「第jo圖」所示，透過執行一化 ® 學機械研磨（CMP)製程用以平坦化溝道31，可形成複數個鋼導 線41。 在以上之步驟之中，如「第lc圖」所示，當執行過度研磨用 以元全去除底絕緣膜1〇之頂部上過量沉積的鶴之時，此過度研磨 可蝕刻底絕緣膜10。此種情況之下，底絕緣膜1〇在具有較高圖案 密度的區域A相比較於具有較低圖案密度的一區域可更多蝕刻 ❹（其稱為一”圖案密度效應〇。結果，如「第沿圖」所示，在靠 近具有較南圖案密度之區域A的銅導線之間產生短路B。 此外，當糊底職膜之時，由於賴塞相比較於底絕緣膜 具有更高之研磨速率，因此鶴插塞減較於統緣膜具有得到更 夕之研磨。這樣可產生另—問題’即在形成銅導線期間在鎮插塞 與銅導線之間產生不良接觸。此問題稱作一,，淺碟化,,。 【發明内容】 因此’馨於以上的問題，本發明之目的在於提供一種半導體 201027627 . » ^置之銅導線形成方法，並且特別地，本發明關於 置之銅導鎗花但干等體裝 、、'/成方法，其能夠在—形成銅導線 防止銅導線之_鱗。 綠之中 根據本翻之實補，—種轉财置之够_成方法可 =·沉積—底絕緣膜於-半導體基板之上；形成複數個過孔於 &、ε緣膜之巾，沉積絲舰賴之頂部之全部表面之上，以使 得使用__充這麵孔；透過執行—鎢化學機械研磨製程用 〇 以去除底絕_之頂部之上崎的過量鶴，形成複數個嫣插塞； 透過執仃-鶴聰製程，去除底絕緣膜之頂部之上保留之鶴；沉 積一頂絕緣膜於底絕緣膜之頂部之上；透過形成複數個溝道於頂 絕緣膜之上，暴露這些鶴插塞之頂部；沉積銅於頂絕緣膜之全部 表面之上卩使得制銅_:填充這些溝道；以及平坦化溝道之 頂部之上的銅。 底絕緣膜可用作一研磨停止件，當探測到底絕緣膜之時鶴化 學機械研賴社刻停止。舰緣射使H終端探廳探測。❹ 一鶊回崎程可在—氟族氣體之環境下執行。此氟族氣體可為 三氟化氯（C1F3)或三氟化氮⑽3)。在鎬回婦程製程期間， 過度蝕刻可在3%至5%的範圍之内執行。 透過執行-活性離子餘刻製程這些溝道形成於頂絕緣膜之. 上。沉於統賴之之”表面之上賴高密度電聚化 學氣相沉積執行。 201027627 接_本發日仅實關，—鮮特打之縛線配設為··沉 積:底絕緣膜於-半導體基板之上，·形成複數個過孔於底絕緣膜 之巾，>儿_於絲賴之卿之全部表蚊上，贿得這些過 孔使糊_充，·使用1化學機械研磨製程㈣除底絕緣 膜之頂部之上沉積的過量鶴，以形成複數個鶴插塞；在一鶴族氣 體之域之中朗—鎢贿製程，麵底絕緣膜之頂部之上保留 病的鶴；沉積一頂絕緣膜於底絕緣膜之頂部之上，·透過執行-侧 ❹製程形成複數個溝道於頂絕緣膜之上，暴露這些嫣插塞之頂部； 沉積銅於舰緣膜之全部表面之上，以使得使關_填充這些 溝道；以及平坦化溝道之頂部之上的銅。 【實施方式】 第2Α圖」至「第2Η圖」係為本發明之實施例之一單鎮嵌 製程之中各步驟之剖視圖。首先，如「第2Α圖」所示，複數個過 β 孔110可形成於一底絕緣膜1〇〇之中。底絕緣膜1〇〇可沉積於一 半導體基板之上，並且底絕緣膜1〇〇可為一金屬導線間介電層、 一前金屬介電層、未摻雜矽玻璃（Und〇pedSilicateGlass USG)、 氟化矽玻璃（Fluorinated Silicate Glass，FSG)、磷化矽破璃 (Phospho-Sihcate Glass，PSG )、或硼磷矽破璃 (Borophospho-silicate Glass, BPSG )。 一阻擔層金屬可沉積於底絕緣膜100與這些過孔110之全部 表面之上。該阻擋層金屬可形成為一鈦/氮化鈦（Ti/TiN)多層 7 201027627 結構。阻擋層金屬有助於在一隨後製程之中沉積於過孔之中鶴之 黏附，並且可防止鎢擴散至底絕緣膜100之中。如果底絕緣膜1〇〇 係為於前金屬介電層，擇可通過鈦與>5夕之結合形成;g夕化物 (TiSi2)’並且因此能夠減少這些接觸插塞與一源極/没極區之間 的接觸電阻。 然後，如「第2B圖」所示，鎢200可沉積於底絕緣膜1〇〇與 這些過孔110 (如「第2A圖」所示）之全部表面之上，以使得這 些過孔110可間隙填充有鶴200。可使用高密度電聚化學氣相沉積 (High Density Plasma Chemical Vapor Dep〇siti〇n, )執行 該間隙填充。 其後，如「第2C圖」所示，透過執行—鶴化學機械研磨（咖' 製程用以去除底絕緣膜觸之頂部上過度沉積的鶴測。在該鶴化 學機械研磨（CMP)製程之中，底絕緣膜1_作-研磨停止件。 在-研磨不狀糾下執行彻。也就找，在触學機械研磨 (_製程_ ’當_作研磨停树的親緣_之時， 研磨可立赃止。使用-光終端_器可探_此研磨停止件。 然而’當制研磨从之條件執行研磨之時，鎢可 絕緣膜100之頂部之上。然後，如「 ^ 弟2D圖」所示，透過執行一 鎢回蝕乂程用以去除底絕緣膜100 之頂邛上保留的鎢200,可形成 族氣體，例如三氟化氣（_或三 氟化II (NF3)之讀下執行細韻製程。 201027627 在鶴回餘製程期間，可執行過度蝕刻用以完全去除底絕緣膜 100之頂部上保留的鎢，在這—點之上，可僅執行3至5%的過度 蝕刻用以最小化由過度蝕刻產生的鎢插塞210之頂部份之損傷。 然後，如「第2E圖」所示，一頂絕緣膜300可沉積於底絕緣 膜1〇〇之頂部之上。頂絕緣膜3⑻可透過一化學氣相沉積方法沉 積，與底絕緣膜100之形成相類似，頂絕緣膜3〇〇可包含有未摻 雜石夕玻璃（USG)、說化石夕玻璃（FSG)、鱗化石夕玻璃（pSG)或硼 ❹傘> 玻璃（BPSG )。 然後’如「第2F圖」所示，透過使用一蚀刻製程在頂絕緣膜 300之上形成複數個溝道31〇，可暴露鎢插塞η。之頂部 。可透過 -活性離子侧（Reaetiveb^eh，·)製程侧溝道31〇。 然後，如「第2G圖」所示，銅4〇〇可沉積於頂絕緣膜3〇〇 之全部表面之上，以使得可使用銅4〇〇間隙填充這些溝道31〇 (如 馨第2F圖」所不）。銅沉積可包含一形成一銅種晶層之步驟以及 銅真充之步驟。可使用物理氣相沉積或化學氣相沉積形成該銅 種a曰層。使用化學氣相沉積、電鍍等可獲得銅填充。 、，最後’如「第圖」所示，銅4〇〇可在溝道MO之頂表面之 上平坦化’由此職魏_導線。紐，料坦化可透過一 化學機械研磨（CMP)執行。 根據本發明之實_ ’此種轉财置之解線形成方法能 夠在-形成銅導線的單鑲喪製程之中防止銅導線之間的短路。此
I 201027627 外可月b在鶴插塞之形成期間最小化鑛插塞之頂部份之損傷。 」本毛3以A述之說gg揭露如上，其應看作對本發明之較 佳實施例之且並_贿定本發明之麵。因此，關於本發 明所界之保護翻請參酬社巾請專繼目。 【圖式簡單說明】 第1A圖至第ig圖係為一習知技術之單鑲嵌製程之各步驟之 剖視圖；以及 第2A圖至第2H圖係為本發明之實施例的一單鑲嵌製程之各❽ 步驟之剖視圖。 【主要元件符號說明】 10 底絕緣膜 11 過孔 20 鶴 21 鎢插塞 30 頂絕緣膜 31 溝道 40 銅 41 銅導線 100 底絕緣膜 110 過孔 200 鎢 10 201027627
210 300 310 400 410 A B 鶴插塞 頂絕緣膜 溝道 銅 銅導線 區域 短路
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Claims (1)

  1. 201027627 七、申請專利範圍： 1· 一種半導體裝置之銅導線形成方法，係包含： 沉積一底絕緣膜於一半導體基板之上； 形成複數個過孔於該底絕緣膜之中； 沉積鶴於該底絕緣膜之頂部之該全部表面之上，以使得使 用該鎢間隙填充該等過孔； 透過執行-雜學機械研磨縣用以去親底絕緣膜之 朗部之上骑的過量鶴’形成複數個鶴插塞； 透過執行-翻崎程，去除該絲賴之_部之上保 留之該嫣； 沉積一頂絕緣膜於該底絕緣膜之該頂部之上； 透過形成魏贿道概魏顧之上，暴等鶴插塞 之頂部； 匕積銅於該頂絕緣膜之該全部表面之上，以使得使用該銅 間隙填充該等溝道；以及 平坦化該等溝道之該頂部之上的該銅。 2.如睛求項第丨項所述之半導體裝置之銅導線形成方法，其中當 探測到該底絕緣膜之時該鶴化學機械研磨製程立刻停止，盆中 該底絕緣_作—研磨停止件。 二求項第2項所述之半導體裝置之銅導線形成方法，其中使 光終端探測__底絕緣膜。 12 201027627 4.如請求項第！項所述之半導體裝置之銅導線形成方法，其中該 鶴回钱製程係在-氟魏體之氣體環境下執行。 • 5·如請求項第1項所述之半導體裝置之銅導線形成方法，其中在 •回崎程製程期間，過度侧係在3%至现的範圍之内 執行。 6.如請求項第！項所述之轉體裝置之銅導線形成方法，其中透 過執仃-蝴抛或透概行—活性軒制製程該等溝道 ® 形成於該頂絕緣膜之上。 如月长項第1項所述之半導職置之銅導線形成方法，其中沉 積鎢於該絲賴之頂部之該全部表面之上係使㈣密度電 榮·化學氣相沉積執行。 8. -種轉體裝置之銅導線，係配設為： 沉積一底絕緣膜於一半導體基板之上； _ 形成複數個過孔於該底絕緣膜之中； 沉積鶴於該底絕緣膜之頂部之該全部表面之上 等過孔使用該鎢間隙填充； 仔〜 使用-鎮化學機械_製㈣以去除該底絕緣膜之 邓之上沉積的過量鎢，形成複數個鎢插塞； 在一鶴族氣體之環境之中制—鎢聰製程 緣膜之該頂部之上保留的該鶴； 痛底絶 沉積一頂絕緣膜於該底絕緣膜之該頂部之上； 13 201027627 201027627 之 透過執行一链刻製程形成複數個溝道於該頂絕緣膜 上’暴露該等鎮插塞之了員部； '儿積銅於該頂絕緣膜之該全部表面之上，以使得使用該銅 間隙填充該等溝道；以及 平坦化該等溝道之該頂部之上的該銅。 9·如請求項第12項所述之半導 到該底絕緣膜之裝置之銅導線’配設為當探柯 底絕緣臈作為-研磨停^止該鶴化學機械研磨雜，其， © 〇·如明求項第12項所述之半導體I置之銅導線，配設 製程期間過度_係為一％至观之範圍之内。，鴣
TW098143804A 2008-12-31 2009-12-18 Method for forming copper wiring in semiconductor device TW201027627A (en)

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