TW201010068A - Solid-state imaging device, production method thereof, and electronic device - Google Patents

Abstract

Disclosed is a solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed.

Description

[Technical Field] The present invention relates generally to a solid-state imaging device, a method of manufacturing the same, and an electronic device including the same. [Previous Technology] Solid-state imaging devices are roughly classified into: an amplifying solid-state imaging device, which is generally described by a CMOS (Complementary Metal Oxide Semiconductor) image sensor; and a charge transfer type imaging device, which is constituted by a CCD (Charge Coupled) Device) Image sensor to represent. Solid-state imaging devices have been widely used in digital still cameras, digital camcorders, and the like. In addition, CM〇s$ image sensors have been used more and more frequently as solid-state imaging devices mounted in mobile devices in recent years, especially due to the relatively low source voltage and low power consumption characteristics of CM〇s image sensors. Mobile devices such as a cellular phone with a camera, a PDA (personal digital assistant), and the like. In a CMOS solid-state imaging device including a pixel section and a peripheral circuit section, the configuration of the isolation regions is known, and the isolation regions are separated by the same STI (shallow trench isolation) in the pixel section and the peripheral circuit section ) Structure formation. Further, in a CMOS solid-state imaging device, another configuration of an isolation region in a pixel section is also known, and the isolation regions are formed by a diffusion layer (see Japanese Unexamined Patent Application Publication No. Publication No. 2005-347325 And Japanese Unexamined Patent Application Publication No. 2006-24786). BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic view showing an exemplary CMOS solid-state imaging device having an isolation region formed by a diffusion layer. Referring to FIG. 1 'providing a CMOS solid-state imaging device 101, which includes a pixel section 1?3 having a plurality of pixels arranged on a semiconductor substrate 102, and a shape 137409.doc 201010068 formed on the periphery of the pixel section 103 A peripheral circuit section 104 of the logic circuit is included. In the pixel section 103, a plurality of unit pixels 11A are arranged in a two-dimensional array in which each of the unit pixels is formed, the pixel including a photodiode (PD) 107 serving as a photoelectric conversion element and a plurality of pixel transistors 108. For the purpose of clarity, such pixel transistors are representatively illustrated by a single pixel transistor 108 in FIG. 1 and form a pixel transistor 1〇8 that includes a source/drain region 109 and a gate insulating film and gate. Electrode (not shown). A multi-level wiring layer 114 is formed over the pixel 110, which includes a plurality of wiring layers 113 having an insulating film 112 formed thereunder for passivation, and an on-chip color filter is formed on the thus formed structure. Sheet 115 and crystal-loaded microlens 116. Although not shown in the drawings, another multi-level wiring layer is similarly formed in the peripheral circuit section 1 to 4, and the multi-level wiring layer includes a plurality of wiring layers having an insulating film formed thereunder. An isolation region 121 in the pixel portion 103 is formed, which includes a p+ diffusion region 122 formed by ion implantation in the semiconductor substrate 102, and a ruthenium oxide film insulating layer 123 formed on the diffusion region. Although the insulating layer 123 is partially buried in the substrate 102, the buried depth hi is set to 50 nm or less, and the total thickness is set in the range of about 50 to 150 nm. On the other hand, an isolation region 125 is formed in the peripheral circuit portion 104 by an STI structure, and the STI structure is formed by a trench 126 disposed in the semiconductor substrate 102 and an oxidized oxide film insulating layer 127 embedded in the trench 126. composition. The buried depth h2 of the insulating layer 127 in the substrate 1 〇 2 is in the range of about 200 to 300 nm, and the protruding height h3 outside the surface of the substrate is sufficiently lower than the insulating layer in the pixel section 103. The protrusion height of 123 is h4. 137409.doc 201010068 In addition, an example of an isolation region formed in a pixel section is disclosed in Japanese Unexamined Patent Application Publication No. Publication No. No. 2005-191262, and another example of the isolation region in the DRAM is disclosed in Japanese Unexamined Patent. Application Publication No. 2007-288137. SUMMARY OF THE INVENTION Regarding an isolation region in a solid-state imaging device, the former structure in which the same STI structure in the pixel segment and the peripheral circuit segment is formed in the above structure is known to have a problem of an increase in white point. That is, since the STI isolation region in the pixel section is formed deep in the semiconductor substrate similarly to the STI isolation region in the peripheral circuit section, stress and damage effects applied to the photodiode are increased, and this results in The white point increases. In order to suppress such white spots, it is necessary to strengthen the blockage at the edge of the STI isolation region (i.e., the accumulation of holes). Since the enhancement of the clogging or the increase in the accumulation of holes is carried out by P-type ion implantation, this tends to reduce the area of the n-type region constituting the photodiode and thus the amount of the saturation signal is lowered. Therefore, there is a trade-off between the increase in congestion and the reduction in the amount of saturated signal. The latter of the above structure (refer to the structure of Fig. 1) can be used as a remedy for forming the isolation region m including the germanium + diffusion region 122 and the insulating layer 123 disposed on the diffusion region. However, in this case, since the formation of the above-described diffusion region must be included in addition to the process of forming the isolation region 125 by the STI structure of the peripheral circuit portion 104 t, there is a problem that the number of processes is increased. Further, as shown in FIGS. 2A and 2B, since the protrusion height h4 of the insulating layer 123 is relatively large in the isolation region 121 of the pixel section, the gate electrode m (131A, 131B, 131C) of the pixel transistor is formed. There is a problem during the process steps that produce 137409.doc 201010068 excess residue 133a. That is, as shown in FIG. 2B, when the polysilicon film 133 is disposed on the entire surface and then subjected to a patterning process using lithography and a remnant technique, it is relatively easy to have insulation with a large gradient difference. A residue of conductive polycrystalline stone is formed on the sidewall of layer 123. When the polysilicon residue l33a is formed, several adverse effects may occur, such as short-circuit faults between adjacent gate electrodes 131 of the pixel cells, and the absence of imaging features. Incidentally, the codes 131A, 1318, and 131C used in Figs. 2 and 2B respectively represent the gate electrodes for transferring, resetting, and amplifying the transistors. In addition, the code 13 4 indicates the n+ source/> and the polar region. In addition, with the structure shown in FIG. 1, since the protruding height h4 from the substrate of the insulating layer constituting the isolation region in the pixel portion is large, the distance L1 between the photodiode and the crystal-loaded microlens tends to As it becomes larger, it is detrimental to the efficiency of collecting light and causes a decrease in sensitivity of the inductor. In view of the above and other problems, the present invention provides a solid-state imaging device which allows a reduction in the number of manufacturing processes and improvement of pixel characteristics including sensitivity, and a method of manufacturing the same. Further, the present invention provides an electronic device incorporating a solid-state imaging device. Provided is a solid-state imaging device according to an embodiment of the present invention, comprising a pixel, a section, a peripheral circuit section, a first isolation region having an ST1 structure formed on a semiconductor substrate in a peripheral circuit section, and a pixel A second isolation region having an STI structure formed on the semiconductor substrate in the segment. Forming a second isolation region of the pixel region such that a portion thereof buried in the semiconductor substrate is shallower than a portion of the first isolation region buried in the semiconductor substrate, and a height of a top surface thereof is equal to a structure having an STI structure The height of an isolation zone. 137409.doc 201010068 In a solid-state imaging device according to an embodiment of the present invention, a portion of a second isolation region in a pixel segment buried in a semiconductor substrate is buried than a first isolation region in a peripheral circuit segment The portion of the semiconductor substrate is shallow so as to suppress stress and (4) adverse effects on the photoelectric conversion element. The surface height of the second isolation region of the pixel segment is equal to and is as low as the surface height of the first isolation region in the peripheral circuit segment, so that the electrode is fabricated during the process of fabricating the gate electrode after forming the device separation region The material does not remain on the side walls of the device separation zone. Since the surface height of the second isolation region in the pixel segment is made equal to the surface height of the first isolation region of the peripheral circuit segment ten, processing due to the difference of the STI structures of the first and second isolation regions may be performed. The increase in the steps is suppressed to a minimum. For the solid-state imaging device according to the embodiment of the present invention, since the surface height of the second isolation region in the pixel section is equal to and as low as the surface height of the first isolation region in the peripheral circuit section, the self-photoelectric conversion element The film thickness of the insulating interlayer between the surface and the wiring on the lowermost layer is reduced. Therefore, the distance between the photoelectric conversion element and the crystal-loaded micromirror becomes small in accordance with the decrease in the film thickness described above, thereby improving the light collecting efficiency. Since the portion of the second isolation region in the pixel segment buried in the semiconductor substrate is shallower than the portion of the first isolation region in the peripheral circuit segment buried in the semiconductor substrate, stress and damage can be suppressed. The adverse effect on the photoelectric conversion element is as described above such that the surface height of the second isolation region in the pixel section is equal to and as low as the surface height of the first isolation region in the peripheral circuit section. Therefore, the electrode material does not remain on the sidewalls of the isolation region during the fabrication of the gate electrode after the isolation region is formed. 137409.doc 201010068 A method of manufacturing a solid-state imaging device according to an embodiment of the present invention, comprising the steps of: (a) forming a first channel in a portion of an isolation region in a peripheral circuit segment to be formed on a semiconductor substrate Forming a second trench in a portion of the trench and the other isolation region in the pixel region to be formed, wherein the second trench is shallower than the first trench, (1)) including the first and second trenches An insulating layer is formed on the inner structure of the trench, and (C) the first and second isolation regions are formed by grinding the insulating layer to have surface heights equal to each other. Φ For the method of manufacturing a solid-state imaging device according to an embodiment of the present invention, the first trench formed on the side of the peripheral circuit segment and the second trench formed on the side of the pixel segment are performed in the same process The insulating layer is deposited, the second trench has a shallower depth than the first trench, and the insulating layer is ground, and the surface heights of the insulating layers for forming the first and second isolation regions are equal to each other. Therefore, the increase in the number of processing steps attributed to the difference in the STI structure of the first and second isolation regions can be minimized. Because the surface height of the second isolation region in the pixel segment is equal to and is as low as the surface height of the first isolation region in the _ peripheral circuit segment, the electrode material is not formed during the gate electrode fabrication after the isolation region is formed Reserved on: * Side wall of the isolation zone. Since the second trench on the side of the pixel segment is shaped to be shallower than the first trench on the side of the peripheral circuit segment, the stress applied to the photoelectric conversion element by the second isolation region can be suppressed. The adverse effects of injury. An electronic device according to an embodiment of the present invention is provided, comprising a solid-state imaging device, an optical system configured to direct incident light to a photoelectric conversion element included in the solid-state imaging device, and configured to process from solid-state imaging 137409 .doc -9- 201010068 Signal processing circuit for the output signal of the device. The solid-state imaging device includes a pixel section and a peripheral circuit section, wherein the first isolation region is formed in the peripheral circuit section by an STI structure on the semiconductor substrate and the second isolation region is in the pixel section by using the semiconductor substrate The STI structure is formed. Forming a second isolation region in the pixel segment such that a portion thereof buried in the semiconductor substrate is shallower than a portion of the first isolation region buried in the semiconductor substrate and a height of a top surface thereof is equal to a first isolation having an STI structure The area is still good. In an electronic device according to an embodiment of the present invention, in the solid-state imaging device, a portion of the second isolation region in the pixel section buried in the semiconductor substrate is buried than the first isolation region in the peripheral circuit segment The portion in the semiconductor substrate is shallow so as to suppress the adverse effects of the second isolation region on the stress and damage of the photoelectric conversion element. Making the surface height of the second isolation region in the pixel segment equal to and as low as the surface height of the first isolation region in the peripheral circuit segment, so that the electrode material is not formed in the gate electrode fabrication after forming the device separation region Retained on the sidewall of the device compartment. Because the height of the surface of the pixel segment from the d is equal to that in the peripheral circuit segment

One and second barriers are suppressed to a minimum. For an electronic device according to an embodiment of the present invention,

137409. Doc 201010068 The portion placed in the semiconductor substrate is shallower than the portion of the first isolation region in the peripheral circuit portion buried in the semiconductor substrate. Therefore, the adverse effects of stress and damage due to the second isolation region on the photoelectric conversion element can be suppressed. Because the surface height of the second isolation region in the pixel segment is equal to and as low as the surface height of the first isolation region in the peripheral circuit segment, the electrode material is not retained during the gate electrode fabrication after the isolation region is formed. On the side wall of the isolation zone. Φ Thus, in accordance with embodiments of the present invention, improvements in process reduction and pixel characteristics including sensitivity can be achieved. [Embodiment] A preferred embodiment of the present invention will be described in detail with reference to the drawings. Embodiments of the present invention are described below with reference to the accompanying drawings. It is not intended to be exhaustive or to limit the invention to the details disclosed in the embodiments. A solid-state imaging device according to an embodiment of the present invention is characterized by the configuration of an isolation region included in a pixel section of a φ imaging and a peripheral circuit section. Figure 3 is a diagram showing the solid state imaging applied to an embodiment of the present invention:  Schematic diagram of the configuration of the device or CM0S image sensor. Provided is a solid-state imaging device 1 in this example, which includes a pixel section 3 (so-called imaging section) having a two-dimensionally regularly arranged on a semiconductor substrate 11 of, for example, a stone substrate a plurality of pixels 2 of a plurality of photoelectric conversion elements; and also includes peripheral circuit sections. Each of the plurality of pixels 2 is formed, which includes, for example, a photodiode as a photoelectric conversion element and a plurality of pixel-like transistors (so-called M〇S transistors). These pixel transistors are provided, which include 137409. Doc 201010068 Four types of transistors, such as transfer transistors, reset transistors, amplifier transistors, and select transistors. A pixel transistor is alternatively provided that includes three types of transistors, such as transfer, reset, and amplify the transistor other than the selection of the transistor. Since the equivalent circuit of the unit pixel is similar to the equivalent circuit of the past, a detailed description thereof is omitted herein. A peripheral circuit section is provided, which includes a vertical drive circuit 4, a row signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The control circuit 8 is configured to generate a clock signal and a control signal for use as a standard for operating the vertical drive circuit 4, the line signal processing circuit 5, and the horizontal drive circuit 6 based on the vertical sync signal, the horizontal sync signal, and the main clock, and The signals generated by these are input to the vertical drive circuit 4, the line signal processing circuit 5, the horizontal drive circuit 6, and the like. Providing a vertical drive circuit 4 including, for example, a shift register and configured to selectively scan each of the pixels 2 included in the pixel section 3 in a column by column in the vertical direction, and A pixel signal based on signal charge generated corresponding to the amount of light received by the photoelectric conversion element (that is, the photodiode in this example) in each pixel 2 is supplied to the line signal processing circuit 5 via the vertical signal line 9. . A row signal processing circuit 5' is provided for, for example, a respective row of pixels 2 included in a pixel segment and configured to perform various types of signal processing, such as noise removal (this will be done pixel by pixel) The image from the currently selected line: the first set of signals outputted by the second reference signal is compared to the second set of signals output from the black reference pixels (placed around the effective pixel area). That is, the line signal processing circuit 5 performs 137409 such as to remove the fixed pattern noise inherent to the pixel 2. Doc 201010068 Signal processing for CDS (related double sampling), signal amplification and other similar processes. At the output stage of the line signal processing circuit 5, a horizontal selection switch (not shown) is connected between the line signal processing circuit 5 and the horizontal signal line 1''. Providing a horizontal driving circuit 6 including, for example, a shift register, and The g is outputted to the horizontal signal line 10 by successively outputting horizontal scanning pulses to sequentially select each of the row signal processing circuits 5 and to convert the pixel signals of each of the self-signal processing circuits $. The output circuit 7 is grouped so that each of the line signal processing circuits 5 is continuously processed by the horizontal signal line 1 (10), and the thus processed signal is output. Further, since the surface illumination type solid-state imaging sensor is covered in the example of the present invention, a multi-level wiring layer having an insulation formed thereunder is formed on the side of the substrate surface on which the pixel section 3 and the peripheral circuit section are formed. Membrane = used for purification. In the pixel section 3, a crystal-loaded % color filter having a planarization film formed thereunder and further forming a crystal-loaded microlens on the on-chip color filter is formed on the multi-level wiring layer. A light shielding film is formed in a region other than the pixel region in the imaging section. In more detail, the light-shielding dam is disposed in a region other than the photodiode (so-called photodetector portion: minute) in the peripheral circuit section and the imaging section. The uppermost wiring layer of the multi-level wiring layer can be used to form a mask.  Light film. Incidentally, as described later, for the back-illuminated solid-state imaging device, the multi-level wiring layer is not formed on the back surface as the light incident side (so-called light receiving surface). That is, a multi-level wiring layer is formed on the side opposite to the surface of the light receiving surface. Although the solid-state imaging device according to the embodiment of the present invention, and particularly the shape 137409. Doc 13· 201010068 The configuration of the isolation regions formed therein may be primarily suitable for CMOS solid-state imaging devices as described herein, but is not intended to limit the invention to those disclosed in the embodiments. [First Embodiment of Solid-State Imaging Device] Fig. 4 is a view for explaining a solid-state imaging device according to a first embodiment of the present invention. Referring to Fig. 4, a main portion of an image forming apparatus including pixel sections (so-called image forming regions) 23 and peripheral circuit sections 24 formed on a semiconductor substrate 22 such as a germanium substrate, respectively, is shown. A solid-state imaging device 21 of the present embodiment is provided, the solid-state imaging device 21 including a pixel section 23 having a plurality of pixels arranged on a semiconductor substrate 22, and a peripheral circuit section 24 formed on a periphery of the pixel section 23, It includes, for example, logic circuitry. The pixel section 23 is provided with a plurality of unit pixels 25 arranged in a two-dimensional array in which each of the unit pixels is formed, which includes a photodiode (PD) 26 serving as a photoelectric conversion element and a plurality of pixels Transistor 27. For the purpose of clarity, such pixel transistors are representatively illustrated by a single pixel transistor 27 in FIG. 4, and the pixel transistor 27 is formed. It includes a source/drain region 28 and a gate insulating film and a gate electrode (not shown). A multi-level wiring layer 33 is formed over the pixel, which includes a plurality of wirings 32 (having an insulating interlayer 3 1 formed thereunder) and forms an on-chip color filter 34 and a crystal-loaded micro on the structure thus formed. Lens 35. The peripheral circuit section 24 is provided with a formed logic circuit (including, for example, a CMOS transistor (not shown)), and has another multi-level wiring layer similarly formed, the multi-level wiring layer including a plurality of wiring layers (having a formation thereof) The lower insulating interlayer 3 1). In the solid-state imaging device 21 of the present embodiment, electrons are used as signal power 137409. Doc -14· 201010068 Lotus. As shown in FIG. 5, a photodiode 26 is provided in a die-type (or first conductivity type) semiconductor well region 36 of a semiconductor substrate, which includes an n-type (or a second conductivity type opposite to the first conductivity type) a charge accumulation region 37, an insulating film 319 formed on the surface of the accumulation region, and a p+ semiconductor region 38 (so-called hole) for controlling dark current formed in a vicinity of an interface with, for example, an oxidation; Accumulation layer). Further, in the present embodiment, the device isolation (FIG. 4) in the peripheral circuit section 24 is formed by embedding the insulating layer 42 in the trench 41 formed in the semiconductor substrate 22 in advance. The first isolation region 43 of the STI structure. In addition, to similarly implement the device isolation in the pixel section 23, the second isolation region 45 of the STI structure is formed by embedding the insulating layer 42 in another trench 44 formed in the semiconductor substrate 22 in advance. . A first isolation region 43 in the peripheral circuit portion 24 is formed, wherein a buried depth h5 of the buried portion of the insulating layer 42 in the semiconductor substrate is in a range of about 200 to 300 nm, and protrudes from a surface of the semiconductor substrate 22. The height of the top surface of the portion (i.e., the protrusion height h6) is in the range of about 〇 to 40 nm. The buried depth h5 is measured herein as the distance from the surface of the semiconductor substrate 22 under the insulating film 39, and the protrusion height h6 is also the height measured from the surface of the semiconductor substrate 22 under the insulating film 39. On the other hand, for the second isolation region 45 in the pixel portion 23, the buried depth h7 of the portion in which the insulating layer 42 is buried in the semiconductor substrate is formed, and the buried depth 1 on the side of the peripheral circuit portion 24 is formed. ^ Shallow. Further, the second isolation region 45 is formed to have a top portion 137409 of a portion of the insulating layer 42 extending from the surface of the semiconductor substrate 22 which is approximately equal to the protrusion height h6 on the side of the peripheral circuit portion 24. Doc -15- 201010068 The height of the face (ie the height h8). Thus, the second isolation region 45 can be formed to have an extension height h8 in the range of about 0 to 40 nm, a buried depth h7 in the range of about 50 to 160 nm, and a total thickness h9 in the range of about 70 to 200 nm. On the side of the peripheral circuit section 24, the protrusion height h6 of the first isolation region 43 must be in the range of about 0 to 40 nm due to the limitation of the general MOS structure. On the side of the pixel section 23, the protrusion height h8 of the second isolation region 45 is set to be in the range of about 0 to 40 nm from the protrusion height h6 on the side of the peripheral circuit section 24. Furthermore, due to the limitation of pixel characteristics, the total thickness h9 in the range of about 70 to 200 nm as described above is required for the second isolation region 45. This total thickness h9 of the second isolation region 45 in the pixel portion 23 is sufficient to produce a satisfactory device isolation feature, even after the wiring is formed on the insulating layer 42, the parasitic MOS transistor is not formed, and the photodiode is not formed. 26 imposes undesirable effects such as stress and damage. That is, as will be described later, for the projection height h8 in the range of 0 to 40 nm, the polysilicon does not remain on the side wall of the portion other than the projecting surface of the second isolation region 45 during the manufacture of the gate electrode by the polysilicon. Therefore, short circuit faults between the gate electrodes can be prevented. For a height h8 of more than 40 nm, the polysilicon residue is relatively easily formed on the sidewall of the overhang. Further, for the buried depth h7 which is shallower than 50 nm, the parasitic MOS transistor is easily formed when the wiring is formed over the second isolation region 45. On the contrary, for a depth h7 deeper than 160 nm, stress and damage are more easily applied to the photodiode 26, and this can be a factor for generating white spots. Therefore, if the total thickness h9 is in the range between 70 and 200 nm, a satisfactory device isolation characteristic of the isolation region 45 is obtained 137409. Doc -16- 201010068 and can suppress the generation of white spots. In this context, the heights of the first and second isolation zones "and h8 should be noted that if such heights are found to be f' relative to each other based on the manufacturing process accuracy within the limits of the processing variation, then the definition is the same. The film thickness of the nitride film mask processed in the trench (ditch), for a nitride film having a thickness of about 2 〇〇 nm, there is substantially an in-plane variation of about ±10% of the wafer. A change in CMP grinding (chemical mechanical polishing) of 20 to 30 nm. Therefore, even if the process is designed such that the protruding heights h6 and h8 in the pixel section 23 and the peripheral circuit section 24 are equal to each other, there are still about 20 to 3 The possibility of a change in 〇nm. Even if the comparison between the pixel section 23 and the peripheral circuit section 24 is performed during the strict inspection at any position on the surface of the wafer and thus the extension is not exactly the same, then The difference between the heights h8 and h6 is kept within the range of less than 30 nm, so as expected, the two are still regarded as "the same height j" as mentioned in the above embodiment. For the solid according to the first embodiment The state imaging device 21, the second isolation region 45 of the pixel portion 23 and the first isolation region 43 of the peripheral circuit portion 24 are formed in a sti structure, and the corresponding insulating layer 42 is extended from the surface of the semiconductor substrate 22. The heights h6 and h8 are the same. Because of the configuration, the process of embedding the insulating layer 42 and the planarizing insulating layer 42 can be performed simultaneously in the manufacturing, so that the number of processes can be reduced. For the solid-state imaging according to the first embodiment The device 21, forming the protrusion height h8 of the second isolation region 45 in the pixel section 23 is equivalent to the protrusion height h6 of the first isolation region 43 in the peripheral circuit section 24, that is, sufficiently small, so that 137409 . Doc -17- 201010068 The film thickness of the insulating interlayer between the photodiode 26 and the first layer wiring becomes small. Therefore, the distance U between the photodiode 26 and the crystal-loaded microlens 35 becomes smaller than the distance L1 previously shown in FIG. Therefore, the light collecting efficiency to the photodiode 26 is improved and the sensitivity is improved. For the second isolation region 45 in the pixel section 23, its protrusion height h8 above the substrate is in the range of 〇 to 40 nm, which is the same as the protrusion height h6 of the first isolation region 43 in the peripheral circuit section 24. small. Therefore, the patterning of the polysilicon film is performed with high precision during the step of forming the gate electrode of the pixel transistor, and the polysilicon does not remain on the sidewall of the portion of the second isolation region 45 which is outside the surface of the substrate. Therefore, short-circuit failure between pixel transistors which may be caused by polysilicon residues may be avoided. In the pixel section 23, the second isolation region 45 is formed in an STI structure such that the buried depth h7 of the portion where the second isolation region 45 is buried in the semiconductor substrate 22 has an STI structure on the side of the peripheral circuit portion 24. The buried depth of the first isolation region 43 in the semiconductor substrate 22 is "shallow. That is, the buried depth h7 of the second isolation region 45 in the pixel portion 23 is set to be in the range of 5 〇 11111 to 16 〇 nm. This embedding depth h7* exerts an adverse effect such as stress and damage on the photodiode 26. That is, since the depth of the trench 44 is small, the occurrence of defects can be prevented. Therefore, the factor causing the white point can be suppressed. The generation of electrons at the interface between the second isolation region 45 and the photodiode 26 is suppressed, and the electrons are leaked from the interface with the second isolation region 45 into the photodiode 26, thereby suppressing the photodiode The appearance of white spots in the polar body 26. In addition, since the total thickness h9 of the second isolation regions 45 in the pixel segments 23 is in the range of about 70 and 200 nm, sufficient device isolation features can be obtained. Doc -18- 201010068 Externally, even if a wiring extending over the second isolation region 45 is formed, a parasitic MOS transistor may not be formed. In addition, since the device isolation feature can be ensured even if the concentration of the p-type ions at the edge portion (lateral end portion) of the second isolation region 45 in the pixel section 23 is relatively low, it is shown in FIGS. 2 and 23 The prior art configuration with the diffusion layer isolation region is advantageous for self-transfer transistor readout. Although not shown in the drawings, the p-type region mentioned above is formed in an isolation region adjacent to the transfer transistor in the pixel. Since the protrusion height h8 of the second isolation region 45 in the pixel section 23 becomes the same as the protrusion height h6 of the first isolation region 43 in the peripheral circuit section 24, that is, sufficiently small, the photodiode The distance L2 between the 26 and the crystal-loaded microlens 35 becomes smaller than the distance u shown in Fig. 1 +. Therefore, the light collecting efficiency to the photodiode 26 is improved and the sensitivity is improved. Both the second isolation region 45 of the pixel section 23 and the first isolation region 43 of the peripheral circuit section 24 are each configured as an STI structure having respective insulating layers 42 extending from the same surface of the semiconductor substrate 22. The height "and (10). Since the process steps of embedding and planarizing the insulating layer 42 can be performed simultaneously by this configuration, the number of processes can be reduced. Therefore, by the configuration of the solid-state imaging device according to the first embodiment, The reduction in the number of processes during the manufacturing process becomes feasible, and the pixel characteristics can be improved by the improvement of the post-image characteristics and the saturation signal amount, the short circuit between the pixel transistors, etc. In addition, the polysilicon is formed during the fabrication of the gate electrode by the polysilicon film. The residue is not formed on the side wall of the portion of the insulating film 42 which is outside the surface of the extending substrate, and the insulating film 42 forms the second isolation region β in the pixel portion 23. 137409. Doc •19- 201010068 This makes it easier to process the gate electrode and improve manufacturing yield. [Second Embodiment of Solid-State Imaging Device] Fig. 6 illustrates a solid-state imaging device according to a second embodiment of the present invention. Figure 6 is a cross section illustrating a main portion of an image forming apparatus configuration mainly including a photodiode 26 in a pixel section 23 and a second isolation region 45 adjacent thereto. The solid-state imaging device 48 according to the present embodiment is provided with a p-type semiconductor layer 49 which is formed at least in a region where the second isolation region 45 of the pixel portion 23 is in contact with the photodiode, that is, a p-type semiconductor is formed. The layer 49 extends to a portion of the insulating layer 42 in the second isolation region 45 that is in contact with the photodiode % and a portion of the bottom surface of the insulating layer 42 in the second isolation region 45. Incidentally, as indicated by the chain line in the figure, the p-type semiconductor layer 49 may be formed to extend over the entire side surface and the bottom surface of the insulating layer 42 buried in the semiconductor substrate 22. Still alternatively, the P-type semiconductor layer 49 can be formed by, for example, performing ion implantation of impurities. The formation of the P-type semiconductor layer 49 can also be performed by ion implantation into the trench after the trench is completed in the STI structure formation process, or ion implantation into the trench through the insulating layer 42 from above after the completion of the sti structure. Come on. In the latter case where the p-type semiconductor layer 49 is formed by ion implantation after being formed into the insulating layer 42, when the depth of the insulating layer 42 is too deep, even after implantation of ions at any implantation angle, Is it distributed correctly? There is a problem with the type of impurity ions. In order to overcome this problem, it is preferred to form a relatively shallow, slightly tapered insulating layer 42, i.e., such that its width tapers downward. Since the other parts of the configuration are similar to those previously mentioned with reference to Figs. 3 and 4, repeated description thereof is omitted herein. I37409. Doc • 20- 201010068 Regarding the configuration of the solid-state imaging device 48 according to the second embodiment, since the p-type semiconductor layer 49 is between the insulating layer 42 and the photodiode 26 in the second isolation region 45 of the pixel section 23 Formed in the vicinity of the interface, the generation of electrons at the device isolation interface can be further suppressed and the generation of white spots in the photodiode 26 can be suppressed. Furthermore, the present structure can also provide effects similar to those previously described with respect to the configuration description according to the first embodiment. [Third Embodiment of Solid-State Imaging Device] Fig. 7 illustrates a solid-state imaging device according to a third embodiment of the present invention. Fig. 7 is a cross section illustrating a main portion of an image forming apparatus mainly including a photodiode 26 in a pixel section 23 and a second isolation region 45 adjacent thereto. The solid-state imaging device 5 i according to the present embodiment is provided, which further includes a p-type semiconductor layer 52 formed under the insulating layer 42 in the second isolation region 45 of the pixel portion 23, which also serves as a diffusion layer isolation. The p-type semiconductor layer 49 shown in Fig. 7 is formed in a vicinity of the interface between the photodiode 26 and the insulating layer 42 in a manner similar to that of Fig. 6. A device configuration without a P-type semiconductor layer 49 can alternatively be provided. Since the other parts of the configuration are similar to those previously mentioned with reference to Figs. 4, 5 and ,, the repeated description thereof is omitted herein. Regarding the configuration of the solid-state imaging device 5A according to the third embodiment, since the p-type semiconductor layer 52 is further formed under the insulating layer 42 to provide diffusion layer isolation in the second isolation region 45 in the pixel portion 23, the combination The diffusion layer isolation described above further improves the device isolation features of the second isolation region 45 in the pixel section 23. In addition, the present structure can also provide effects similar to those previously described with respect to the configuration descriptions according to the first and second embodiments. 137409. Doc - 21 - 201010068 [Fourth Embodiment of Solid-State Imaging Device] Fig. 8 illustrates a solid-state imaging device according to a fourth embodiment of the present invention. Fig. 8 is a cross section illustrating a main portion of an image forming apparatus mainly including a photodiode 26 in a pixel section 23 and a second isolation region 45 adjacent thereto. A solid-state imaging device 54 according to an embodiment of the present invention is provided which forms a second isolation region in the pixel section 23 having an STI structure shallower than the STI structure on the side of the peripheral circuit section 24 in the above embodiment. The photodiode 26 is extended such that at least a portion thereof reaches below the second isolation region 45. A p-type semiconductor layer 49 similar to the semiconductor layer shown in Fig. 6 can be formed in the vicinity of the interface between the second isolation region 45 and at least the photodiode 26. A device configuration without a p-type semiconductor layer 49 is alternatively provided. Further, as previously described with reference to Fig. 7, a p-type semiconductor layer 52 serving as a diffusion layer isolation may be formed under the insulating layer 42 in the second isolation region 45. Since the other parts of the configuration are similar to those previously mentioned with respect to the first and second embodiments, the repeated description thereof is omitted herein. Regarding the configuration of the solid-state imaging device 54 according to the fourth embodiment, since the extended photodiode 26 is formed such that at least a portion thereof reaches below the second isolation region 45, the area of the photodiode 26 can be increased. This increase in the area of the photodiode is beneficial to increase the amount of saturation signal and improve sensor sensitivity. Furthermore, the present embodiment can also provide effects similar to those previously described with respect to the configuration descriptions according to the first to third embodiments. [Fifth Embodiment of Solid-State Imaging Device] Fig. 9 illustrates a solid-state imaging device according to a fifth embodiment of the present invention. FIG. 9 is a view only showing the photodiode 26 and the pixel transistor 137409 in the pixel section 23. Doc • 22- 201010068 27 and a second isolation region 45 adjacent thereto, and a cross section of a main portion of the imaging device of the first isolation region 43 of the peripheral circuit segment 24. In the solid-state imaging device 55 according to the embodiment of the present invention, the first isolation region 43 having the STI structure in the peripheral circuit section 24 is formed on the semiconductor substrate 22 in the vertical direction as in the previously described embodiment. In the middle of the depths. Further, the second device separation region 45 having the STI structure in the pixel portion 23 is formed in the semiconductor substrate 22 shallower than the first isolation region 43 in the vertical direction. The insulating layers 42 of the first isolation region 43 and the insulating layer 42 of the second isolation region 45 have the same heights h8 and h6 from the surface of the semiconductor substrate 22. In particular, in the embodiment of the present invention, the insulating portion 42a in the shape of a bird's beak extending from the insulating layer 42 is provided in each of the portions of the first isolation region 43 and the second isolation region 45 that contact the surface of the semiconductor substrate 22. in. That is, the insulating portions 42 of the first isolation region 43 and the second isolation region 45 contact the respective shoulder portions of the surface of the semiconductor substrate 22 to form the insulating segments 42a each having a bird shape, and the shoulder portion of the semiconductor substrate 22 has Insulation section 42& thickness of thick thickness. Further, since the insulating segments 42 & each are in the shape of a bird's beak, the curvature of the insulating layer 42 in the shoulder portion is gentle. In the embodiment of the present invention, as described later, in the thermal oxidation sidewall film of the trenches 4, Μ, before the insulating layer 42 of the yttrium oxide film is embedded in the trench 43, 43, the trenches 41, 44 are The corners of the upper and lower parts are rounded. Further, insulating sections 42a each in the shape of a bird's beak are formed in a corner portion (so-called shoulder portion) above the groove and the weir. Note that as the sidewall film, a 137409 other than the thermal oxide film formed by an insulating treatment (such as plasma deuteration treatment, wire nitridation treatment, etc.) may be used. Doc 23· 201010068 rim film (such as plasma oxide film, electro-nitride film, etc.). Further, in the second isolation region in the pixel portion 23, an impurity implantation region for suppressing dark current is formed from a portion of the interface with the semiconductor substrate 22 to a side surface of the semiconductor substrate 22 (that is, a p-type semiconductor layer 49). That is, the P-type semiconductor layer 49 is formed along the bottom and side surfaces of the insulating layer 42 embedded in the second isolation region 45 to the insulating segments 各自 each in the form of a bird edge, partially reaching the semiconductor in the lateral direction. A region of the surface of the substrate extends in the pixel electrode body 27 to form a closed electrode % so as to straddle the projecting surface projecting from the surface of the second isolation region 45. The other parts of the configuration are similar to those described with reference to the first embodiment, and thus the repeated description is omitted. With regard to the imaging device 55 according to the fifth embodiment, the insulation in the shape of a bird's beak is formed in the corner portion (shoulder portion) of the groove 44 of the second isolation region 45 having the SI7 structure in the pixel section n Section 仏. That is, since the insulating segment 呈 in the shape of a bird's beak as shown in Fig. H) is provided, the concave portion appearing in the isolation region β having the ordinary printed structure shown in Fig. 12 is shown. a divot 59. In the pixel transistor 27t, the end portion of the gate electrode % is formed so as to straddle the isolation region. In the present embodiment, the insulating layer 42 at the corner portion above the trench 44 The thickness tl is large and due to the gentleness of the upper corner portion: the reduced stress is combined to reduce the electric field concentration to the corner portion above the trench 44. The reduction of the electric field concentration increases the threshold in the upper corner portion The voltage grain, and the generation of the parasitic channel component η can be suppressed at the edge portion on the boundary with the second isolation region 45 of the pixel transistor 27 shown in Fig. 11 because the generation of the parasitic channel component 57 is suppressed, so the source is suppressed. 8 and no (10) 137409. Doc -24- 201010068 Leakage current and reduce random noise. Since the quality of the oxide film in the edge portion is relatively poor compared to the center portion, random noise can be reduced. Since the pit 59 is suppressed, the peak value in the {Id (drain current) - Vg (gate voltage) characteristic of the pixel transistor 27 can be reduced. Since it is also in the insulating layer 42 of the first isolation region 43 of the peripheral circuit section 24 in the MOS transistor of the peripheral circuit section 24, the insulating layer 42 of the second isolation region 45 with the pixel section - 23 is used. The structurally similar structure also provides the effect of reducing the peaks in the Id-Vg characteristics. Further, since the curvature of the upper corner portion of the groove 44 is gentle in the second isolation region 45 of the pixel portion 23, the stress applied to the upper corner portion is reduced. This makes it possible to improve the dark current and white point attributed to the floating diffusion (FD) section of the pixel. Also, the junction leakage in the floating diffusion section is suppressed. In the second isolation region having the STI structure in the pixel portion 23, in order to improve the dark current and the white point, a semiconductor layer is provided around the STI structure. In the present embodiment, the p-type semiconductor layer 49 is self-contained. The sidewall of the trench 44 is formed to the side surface of the semiconductor substrate, that is, the p-type semiconductor layer 49 extending toward the side of the active region of the photodiode or the pixel transistor. Therefore, : ' The P-type semiconductor layer 49 is provided on the side of the active region in the upper portion of the trench 44 so as to increase the degree of freedom in improving the dark current and the white point, since it is formed on the side of the active region in the upper portion of the trench 44 in the pixel transistor. The P-type semiconductor layer 49 can make the parasitic channel component smaller. In combination with the above-described pit improvement, the random noise can be improved in a synergistic manner. In addition, the similar effect described in the first embodiment is produced. An embodiment] 137409. Doc -25· 201010068 Next, a first embodiment of a method of manufacturing the solid-state imaging device according to the present invention will be described with reference to Figs. 13A to 17J. This embodiment is suitable for manufacturing a solid-state imaging device according to the above-described second embodiment of the solid-state imaging device shown in Fig. 6, and is particularly suitable for forming an isolation region thereof. First, referring to FIG. UA, a thin insulating film 39 having a first predetermined film thickness is formed on the main surface of the semiconductor substrate 22, and then formed on the insulating film 39 at an etching rate different from the etching rate of the insulating film 39. Another insulating film 61 of a predetermined film thickness. As the insulating film 39, for example, a hafnium oxide film can be used. As the insulating film 61, for example, tantalum nitride having a film thickness of about 〇〇 formed by low-pressure CVD can be used. A photoresist film is deposited over the insulating film 61. The photoresist film is exposed through an optical mask having a prescribed pattern and then developed, thereby forming a resist mask 63 having an opening 62 corresponding to a portion of the isolation region on the side where the peripheral circuit portion 24 is to be formed. . The entire surface on the side of the pixel section 23 is covered by a flat surface resist mask 63 having no opening. Next, referring to FIG. 13B, the insulating films 6A and 309 on the side of the peripheral circuit section 24 are removed by performing selective surging through the resist mask 63, and then by performing selective etching further. The blade of the semiconductor substrate 22 is removed to obtain a pre-ice degree, thereby forming a plurality of trenches 41. These trenches are formed herein as relatively deep trenches having a depth of about 2 〇〇 to 3 〇〇 nm as previously mentioned. Next, as illustrated in Fig. 14C, a new photoresist film is deposited after the resist mask 63 is removed. The photoresist film is exposed through an optical mask having a prescribed pattern and then developed, thereby completing a resist mask 65 having a shape to be formed 137409. Doc 201010068 A portion 64 corresponding to the portion of the isolation region on the side of the pixel segment 23. The entire surface on the side of the peripheral circuit section 24 is covered by a flat surface resist mask 65 having no opening. Next, the insulating films 61 and 49 on the side of the pixel section 23 are removed by performing selective etching via the resist mask 65 with reference to FIG. 14D, and then the semiconductor substrate is removed by further performing selective etching. Portions of 22 are obtained to a predetermined depth, thereby forming a plurality of channels 44. These trenches 44 are formed relatively shallowly, having a depth of about 50 to 160 nm as previously mentioned. Further, in practice, the trench is formed by first performing an etching process to have a depth of about 4 Å to 15 Å, and then the final completed depth in the range of about 50 to 160 nm is obtained by photolithography or the like. Next, as shown in FIG. 15E, the resist mask 65 is removed. Incidentally, although the deep trenches 41 on the sides of the peripheral circuit section 24 have been formed first and then the shallow trenches 44 on the sides of the pixel sections 23 have been formed, the process may alternatively be reversed, wherein first formed The shallow trench 44 on the side of the pixel section 23 and later the deep trench 41 on the side of the peripheral circuit section 24, then, at the process step illustrated in Figure 15F, may be by the inner wall of the trench material The surface is ion implanted to form, for example, a p-type semiconductor layer 49. The p-type semiconductor layer 49 can be formed by ion implantation after the isolation region is completed. Still alternatively, the P-type semiconductor layer 49 can be formed by first implanting a P-type impurity at the step of FIG. 15F and then implanting a second p-type impurity after completing the isolation region, thereby being via the double ion Implanted to form the p-type semiconductor layer 49. 137409. Doc • 27- 201010068 In this example, as illustrated in Figure 15F, a photoresist film is deposited over the entire surface of the structure. The photoresist film is exposed through an optical mask having a prescribed pattern and then developed, whereby a resist mask 67 is formed only on the side of the peripheral circuit portion 24. Subsequently, ion implantation is performed using the insulating film 61 such as a hafnium nitride film on the side of the pixel section 23 as a hard mask to implant the p-type impurity 60 into the entire surface of the pixel section 23. The portion of the substrate 22 which is formed as the insulating film 61 of the hard mask is not subjected to ion implantation of the p-type impurity 6?, and the portion of the substrate 22 which forms the opening 61a (i.e., the inner wall surface of the trench 44) is ion-implanted. Thus, a p-type semiconductor layer 49 is formed on the inner wall surface of the trench 44 (i.e., on the entire inner wall surface including the inner surface and the bottom surface of the wall of the trench 44). This plasma implantation is performed by rotational implantation. Incidentally, the p-type semiconductor layer 49 can be formed only on the inner face of the trench which is in contact with the photodiode by an alternative implantation method. Although the p-type semiconductor layer 49 is formed by ion implantation of p-type impurities because the trench 44 has been formed, does this have a reduced implant? The potential of the concentration of impurities and the advantage of the charge Q per unit area. Referring next to Fig. 16G', after the resist mask 67 is removed, an insulating layer 42 is formed on the entire surface of the structure by, for example, a CVD method to be embedded in the trenches 41 and 44. As the insulating layer 42, for example, a hafnium oxide film can be used. Next, referring to Fig. 16H, at the step of grinding the insulating layer 42 as a post-process, the surface portion of the insulating layer 42 having rough surface irregularities is removed by partial etching to uniformly grind the entire surface. If there is a difference in the density of surface irregularities, 137409 may appear after grinding the entire surface at the same time. Doc •28· 201010068 Uneven grinding finish. Therefore, as illustrated in Fig. 16H, a part of the surname has a surface portion having a rough surface irregularity. Next, as illustrated in Fig. 171, the surface of the insulating layer 42 is subjected to planarization polishing. At this time, the grinding step is terminated on the surface of the insulating film 61. Thereafter, the surface of the crucible is ground such that the protrusion height "and h8" of the insulating layer 42 is in the range of about 〇 to 40 nm, in this example, about 4 〇 nm. At this point, consider 'm grinding after washing, etc. For subsequent operations, the height is set to be relatively thick so as to finally reach the range of 〇 to 4 〇 nm. For example, a CMp (Chemical Mechanical Polishing) method can be used as the polishing method. Next, as illustrated in Fig. 17J, The selective etching removes the insulating film ό 1. Thus, the pixel portion 23 and the peripheral circuit portion 24 are formed, which have the same protruding heights h8 and h6 (h8 = h6), and further include the peripheral circuit portion 24 formed. a first isolation region 43 having a deep STI structure and a second isolation region 45 having an STI structure formed in the peripheral circuit portion 24, the STI structure having a shallower depth than the first isolation region 43. φ in a subsequent process At the step of forming the photodiode 26 and the pixel transistor 27' and further forming a multi-level wiring layer 33 thereon. Further, the on-chip color filter 34 and the crystal-loaded microlens 35 are formed on the multi-level wiring layer 33. , having, flattened underneath The film, thereby forming a desired MOS type solid-state imaging device, is disposed 48. Incidentally, the photodiode 26 may alternatively be formed before the process of forming the first isolation region 43 and the second isolation region 45. Second Embodiment of the Method] Next, a solid-state imaging device 137409 according to the present invention will be described with reference to FIGS. 18A to 22. Doc - -29-201010068 A second embodiment of the manufacturing method. The present embodiment is suitable for manufacturing a solid-state imaging device' according to the above-described second embodiment of the solid-state imaging device shown in Fig. 6, which is particularly suitable for its isolation region. First, referring to FIG. 18A, a thin insulating film 319 having a pre-twist film thickness is formed on the main surface of the semiconductor substrate 22, and then formed on the insulating film 39 at an etching rate different from the etching rate of the insulating film 39. Another insulating film 61 of a second predetermined film thickness. As the insulating film 39, for example, a hafnium oxide film can be used. As the insulating film 6 可, for example, a tantalum nitride film of a film thickness of about 100 nm formed by a low voltage cvd can be used. A photoresist film is deposited over the insulating film 61. The photoresist film is exposed through an optical mask having a prescribed pattern and then developed, thereby forming a resist mask 73 having a side on which the peripheral circuit section 24 is to be formed and a side of the pixel section 23, respectively. Portions of the isolation regions correspond to openings 711 and 722. Next, referring to FIG. 18B, the insulating films 61 and 39 respectively on the side of the pixel section 23 and the side of the peripheral circuit section 24 are removed by performing selective etching through the resist mask 73, and then borrowed The portion of the semiconductor substrate 22 is removed by further performing selective etching to obtain a predetermined depth thereby forming a plurality of trenches 44 and 41a, respectively. These channels 41 are formed herein as relatively shallow trenches having a depth of about 50 to 160 nm as previously mentioned. Further, since the trench 41a on the side of the peripheral circuit section 24 is formed simultaneously with the trench 44 on the side of the pixel section 23, the trench 41a is formed to have a trench having the same depth as the trench 44. Next, as illustrated in Fig. 19C, a new photoresist film is deposited after the resist mask 73 is removed. Exposing the photoresist film 137409 through an optical mask having a prescribed pattern. Doc -30-201010068 and subsequent development, thereby forming a resist mask 74 covering only the sides of the pixel section 23. That is, the resist mask 74 is not formed on the side of the peripheral circuit section, and the entire surface on the side of the pixel section 23 is covered by the resist mask 74. Further, the trench 41a on the side of the peripheral circuit section 24 is removed by etching through the resist mask 74, thereby forming the deep trench 4j. Forming such trenches having a depth of about 200 to 300 nm as previously mentioned - 41 ° φ Next, as illustrated in Figure 19D, the resist mask 74 is removed. Next, at the process step illustrated in Fig. 20E, for example, a p-type semiconductor layer 49 can be formed by ion implantation on the inner wall surface of the trench material. The p-type semiconductor layer 49 can be formed by ion implantation after the isolation region is completed. Still alternatively, the P-type semiconductor layer 49 can be formed by first implanting the first P-type impurity at the step of FIG. 2A and then implanting the second p-type impurity after completing the isolation region, thereby The double ions are implanted to form the p-type semiconductor layer 49. • In this example, as illustrated in Figure 2, after removal of the resist occult 74, a photoresist film is further deposited. This photoresist film is exposed through an optical mask having a prescribed pattern and then developed, whereby the resist mask 76 is formed only on the circumference. ‘On the side of the circuit section 24. Subsequently, ion implantation is performed using the insulating film 61 such as a tantalum nitride film on the side of the pixel portion 23 as a hard mask to implant the P-type impurity 60 into the entire surface of the pixel portion 23. The portion of the substrate 2 which is formed as the hard mask 61 is not implanted with ions of the p-type impurity (10), and the portion of the substrate 22 where the opening 61a is formed (that is, the inner wall surface of the trench 44) is ion-implanted. . Thereby on the inner wall surface of the trench 44 137409. Doc • 31- 201010068 (that is, on the entire inner wall surface including the inner surface and the bottom surface of the wall of the trench 44), a p-type semiconductor layer 49 is formed. This plasma implantation is performed by spin implantation. Incidentally, the p-type semiconductor layer 49 can be formed only on the inner face of the trench which is in contact with the photodiode by an alternative implantation method. Since the subsequent steps illustrated in FIGS. 20F through 22 are similar to those previously described in FIGS. 16(} through 17J, portions corresponding to those shown in FIGS. 17 to 17j are represented by the same numerical values. The repeated description thereof is omitted and omitted herein. At the subsequent processing steps, the photodiode 26 and the pixel transistor 27 are formed in a manner similar to the above-described manner, and the multi-level wiring layer 33 is further formed thereon. Further, the on-line color filter 34 and the crystal-loaded microlens 35' are formed on the multi-level wiring layer 33, and have a planarization film formed thereunder, thereby forming a desired MOS type solid-state imaging device 48. And, the photodiode 26 may be formed before the process of forming the first isolation region 43 and the second isolation region 45. The above manufacturing method of the solid-state imaging device according to the first and second embodiments of the manufacturing method After forming the trenches 44 and 41 on the side of the pixel section 23 and the side of the peripheral circuit section 24, respectively, the second and the second are formed by depositing the insulating layer 42 and grinding by the CMP method in the same process. Isolated area 45 and 43. Therefore, the number of processes in the manufacturing process can be reduced. Further, the second and first isolation regions 45 and 43 having the same projecting height and the second isolation region on the side of the other pixel segment 23 are formed. The depth of 45 is shallower than the first isolation region 43 on the side of the peripheral circuit section 24. Therefore, it is possible to manufacture the subsequent image features, the saturation signal amount, and the like 137409 as previously mentioned. Doc -32- 201010068 Solid-state imaging device with improved pixel characteristics. [Third Embodiment of Manufacturing Method] Next, a third embodiment of the manufacturing method of the solid-state imaging device according to the present invention will be described with reference to Figs. 23 to 25 . The embodiment of the present invention is suitable for manufacturing the solid-state imaging device 55 according to the fifth embodiment shown in Fig. 9, and is particularly suitable for forming its isolation region. • In the manufacturing method according to the third embodiment, first, as illustrated in FIG. 23A, 'the process shown in FIGS. 13A to 15E or FIGS. 18A to 19D' is used in the pixel section 23 and the peripheral circuits, respectively. A shallow trench 44 and a deep trench 41 are formed in the section 24. Fig. 23A shows a state in which a thin insulating film 39 such as an oxide film is formed on the surface of the semiconductor substrate 22 where the trenches 44 and 41 are not formed and an insulating film 61 such as a tantalum nitride film is formed on the thin insulating film 39. . Next, as illustrated in Fig. 23B, the width of the insulating film 61 is selectively narrowed. For example, using a chemical such as hot phosphoric acid, the exposed surface of the insulating film 61 of the tantalum nitride film is selectively removed to a predetermined thickness, and thereby the width φ is narrowed from the initial width d1 to the width d2. The removed width d3 can be made from about 2 nm to 15 nm. If the removed width d3 is less than 2 nm, the effect of the present invention may not be obtained. If the width d3 increases, the gate of the edge of the layer is affected.  The thickening of the oxide film is increased and the effective gate width of the transistor is narrowed. The minimum width of the effective layer in the 90 nm generation needs to be about 12 〇. If the width d3 is 15 nm or more, the minimum width of the effective active layer becomes about 120-15x2 = 90 nm, and the driving force of the transistor having the smallest effective working layer width is deteriorated by about 10%. Because this affects the velocity characteristics, the maximum amount of width is about 15 nm. 137409. Doc - 33 - 201010068 Next, as shown in Fig. 24C, the side walls of the trenches 41 and 44 and the side portions of the semiconductor substrate are subjected to thermal oxidation treatment using the insulating layer 61 of the tantalum nitride film as a mask. The so-called sidewall oxidation of the trenches 44 and 41 is performed. By this thermal oxidation treatment, a thermal oxide film 71 is formed on the sidewalls of the trenches 44 and 41. Since this thermal oxidation is selective oxidation for the surface not covered by the insulating layer 61 of the tantalum nitride film as illustrated in Fig. 26, in the corner portion above the trenches 44 and 41, the oxide film is formed therein. A thermal oxide film 71a which is convex in the shape of a bird's beak. The thermal oxide film 71a in the shape of a bird corresponds to the insulating portion 42a in the shape of a rim shown in Fig. 1A. By this selective oxidation, the surface of the thermal oxide film (the semiconductor substrate 22 which contacts the crucible) in the corner portion above the trenches 44 and 41 becomes gentle rounded curvature. At the same time, the thermal oxide film in the corner portion of the trench 44 and the crucible is rounded. A plasma oxide film, a plasma oxynitride film, or the like formed by selective insulation processing (such as plasma oxidation processing, plasma oxynitridation processing, or the like) other than the thermal oxide film may be used as the self-groove 44 and The sidewall film formed by the side wall of the 41 to the surface of the substrate "selectively performs such plasma oxidation and plasma oxynitridation using the insulating film 61 as a mask. Next, as shown in FIG. 24D, the side of the peripheral circuit section 24 is covered by the anti-instrument mask, and the insulating film 61 of the acoustic film is used as a mask to perform ion implantation of the P-type impurity 60. The upper semiconductor layer 49 on the inner wall surface of the trench 44 in the pixel portion 23 is formed. As shown in Fig. 27, in addition to the inner and bottom surfaces of the trench 44, the p-type semiconductor layer is formed to extend laterally from the upper corner portion of the trench 44. That is, a p-type semiconductor 137409 which extends to the surface of the semiconductor substrate 22 which is not covered by the insulating film 61 is formed. Doc 201010068 Body layer 49. The process shown in Figure 24D corresponds to the process shown in Figures 15F and 20E. The subsequent processes are the same as those shown in Figs. 16G to 17J, Figs. 20F to 21H, and Fig. 22 . Then, as shown in FIG. 25, a first isolation region 43 having a deep STI structure is formed in the peripheral circuit portion 24 and a second isolation region 45 having a shallow STI structure is formed in the pixel portion 23. Wherein the protrusion height (10) in the pixel section 23 and the peripheral circuit section 24 and "the same appeal. At the same time" in the first and second isolation regions 43, 45, the insulating layer 42 is inlaid Into the trenches 41, 44, however, an insulating section 42a in the shape of a bird is formed in each of the corner portions above the trenches 41, 44. Further, a second on the side of the pixel section 23 In the isolation region 45, a p-type semiconductor layer 49 is formed to surround the isolation region 45 and partially extend in a lateral direction from a corner portion of the trench 44. In a subsequent process, a photodiode 26 and a pixel transistor 27 are formed. And a multi-level wiring layer 33 is formed thereon. Further, the crystal-supporting color filter 34 and the crystal-loading microlens 35 are formed on the multi-level wiring layer 33 via the planarization film, and thereby a desired MOS type solid state is obtained. Imaging device 55. According to the manufacturing method of the solid-state imaging device according to the third embodiment, in the form, After the trenches 41, 44, the width of the nitride film 61 is narrowed by the process of Fig. 23B, and the material row trenches 41, == walls are oxidized, that is, the insulating layer 61 whose width is narrowed is used as The mask is used to oxidize the sidewalls of the drains 41 and 44 to form oxidation (4). By selective oxidation, an oxide film having a convex shape in which the oxide film has a convex shape is formed in the corner portion above the trench. 71a. The oxide film 7la is shown in Figure 137409. Doc -35- 201010068 corresponds to the insulating section 42a of the bird's edge shape. Thereafter, the trenches 41, 44' are buried by the insulating layer 42 and thereby the first and second isolation regions 43' 45' are formed so that the pits generated in the ordinary isolation regions having the STS structure can be reduced. Since the pixel transistor in the peripheral circuit section or the pit in the MOS transistor can be controlled, the film quality of the insulating layer in the separation edge portion is inferior to the quality of the gate oxide film in the central portion, but can be improved. The film quality. By eliminating the pits, the parasitic channel component is reduced, and the random noise is reduced. Furthermore, the sidewall oxidation can round the upper and lower corners of the trench 41'44. A surface having a gentle curvature is formed in each of the corner portions above the trench. Thereby, the stress in the upper corner portion of the isolation regions 43, 45 each having the STI structure can be reduced. In the pixel section, the dark current and white point generated by the floating diffusion (FD) section of each pixel can be improved. In the process of Fig. 24D, in order to suppress dark current and white spots, the p-type semiconductor layer 49 is formed by ion implantation. At this time, the semiconductor layer 49 extending in the lateral direction from the side wall of the trench to the surface of the semiconductor substrate is formed. Since the p-type semiconductor layer 49 is formed so as to extend in the lateral direction to the surface of the substrate on the side of the active region, it is possible to increase the degree of freedom in further improving the dark current and the white point. Since the p-type semiconductor layer 49 is formed so as to extend from the upper portion of the trench to the side surface of the substrate, is the edge portion in the upper portion of the trench at the edge portion? The density of the type semiconductor layer 49 becomes high. Thereby, the parasitic channel component at the edge portion of the isolation region of the contact pixel transistor shown in Fig. u can be made smaller. In combination with the improvement of the pit, the random noise can be improved in a synergistic manner / 137409. Doc • 36· 201010068 Further, effects similar to those described with respect to the manufacturing methods of the solid-state imaging devices according to the first and second embodiments are produced. Embodiments of the present invention are applicable to both a surface illumination type solid-state imaging device and a back-illuminated solid-state imaging device. In the CMOS solid-state imaging device as described above, the embodiment of the present invention can be applied to a surface side illumination type device in which light enters from the side of the multi-level wiring layer, and a light-substrate and multi-level wiring layer.  On the contrary, the back side enters the back lighting type device. The solid-state imaging device according to the embodiment of the present invention can be applied to a linear image sensor or the like other than the above-described area image sensor. [Sixth Embodiment of Solid-State Imaging Device] Fig. 28 is a view for explaining a solid-state imaging device according to a sixth embodiment of the present invention. Provided is a solid-state imaging device according to the present embodiment, which reduces an extension height (10) of a second isolation region in a pixel section to be the same as an extension height h6 of a first isolation region in a peripheral circuit section, and is formed in The thickness of the insulating interlayer between the substrate surface and the multi-level wiring layer is thinned or reduced. Simultaneously, . A waveguide structure facing the photodiode 26 is also provided to improve the pixel characteristics of the concentrating efficiency and total sensitivity of the light including the photo-integrated body 26. A solid-state imaging device 55 according to the present embodiment is provided in a manner similar to that described in the first embodiment, and includes a pixel section 23 having a plurality of pixels arranged on the semiconductor substrate 22, And formed on the periphery of the pixel region #23, for example, the peripheral circuit portion 24 of the logic circuit. The pixel section 23 includes a plurality of pixels 25 arranged in a two-dimensional array in which each of the pixels is formed, the pixels comprising acting as a photoelectric conversion 137409. Doc •37- 201010068 Photodiode 26 and pixel transistor 27 of the component. As shown in FIG. 5, a photodiode 26 is provided which includes an n-type or second conductivity type charge accumulation region 37, an insulating film 39 formed on the surface of the accumulation region, and is formed, for example, with yttrium oxide. The ρ + semiconductor region 38 for controlling dark current in the vicinity of the interface of the film. On the insulating film 39 of, for example, a ruthenium oxide film formed on the surface of the photodiode 26, a tantalum nitride film 40 serving as an anti-reflection film is formed. Forming pixel transistors, which are representatively illustrated by a single pixel transistor 27 for clarity purposes, including source/drain regions 28, gate insulating film 29, and formed by, for example, polysilicon The gate electrode is 3 turns. In addition, the source/drain regions 28 are formed in a direction perpendicular to the plane of the drawing. Also, the end portion of the gate electrode 30 is formed so as to straddle the second isolation region 45. In the pixel section 23 and the peripheral circuit section 24, the second isolation region 45 and the first isolation region 43 are respectively formed by the STI structure described above. The first isolation region 43 is buried in the first trench 41. The insulating layer 42 is formed, and the insulating layer has a buried depth h5 and an extended height h6. The second isolation region 45 is formed by an insulating layer 42 buried in the second trench 44, the insulating layer having a buried depth h7 and an extension height h8. As previously mentioned, the protrusion heights h6 and h8 of the isolation regions 43 and 45 are set to be the same. The buried depth of the second isolation region 45 is set to be shallower than the buried depth h5 of the first isolation region 43. In a manner similar to that previously indicated for the first isolation region 43, the buried depth h5 may be in the range of about 2 〇〇 to 3 〇〇 nm 'and the protrusion height may range from about 〇 to 4 〇 nm. In the second isolation region 45, the embedding depth h7 may be in the range of about 5 〇 to 16 〇 nm. The extension h8 may be in the range of about 〇 to 4 〇 nrn and the total thickness h9 may be about In the range of 70 to 200 nm. 137409. Doc -38- 201010068 On the substrate in the pixel section 23, a multi-level wiring layer 33 is formed which includes a plurality of wiring layers 32 having insulating interlayers 31 (3 11 to 315) formed thereunder for passivation (321 to 324). The insulating interlayer 31 can be formed using, for example, an oxidized stone film. In the present example, a plurality of wiring layers 32 including a first layer wiring 321, a second layer wiring 322, a third layer wiring 323, and a fourth layer wiring 324 are formed. Each of the wiring layers 32 (321 to 324) is formed by embedding a damascene process including a button/nitride barrier metal layer 157 and a copper (Cu) wiring layer 158. Forming a first one on each of the insulating interlayer layers 31 between the wirings including the top surface of the copper (Cu) wiring layer 158 (that is, on each of the insulating interlayers 311 to 314) The fourth interlayer wiring diffusion preventing film 159 (159a, 159b, 159c, and 159d) is used to prevent diffusion of copper (Cu) used as a wiring material. The wiring diffusion preventing film 159 is formed of a film including, for example, SiN and/or SiC. In the present example, the wiring diffusion preventing film 159 is formed of Si (: film. Although not shown in the drawings, the peripheral circuit section 24 is provided with the formed logic circuit 'including, for example, a CM〇S transistor, and is provided Other multi-level wiring layers (having a predetermined number of wiring layers) are similarly formed. Further, in the present embodiment, a waveguide 156 is formed over each of the photodiode bodies 26 in the pixel section 23 to effectively effect incident light. Leading to the photodiode 26. A groove 87 is formed in a portion of the multi-level wiring layer 33 facing the photodiode 26 by first selectively etching the insulating interlayer 31 and the interlayer wiring diffusion preventing film 159. And then the first core layer and the second core layer 89 are buried in the recess 87 to form the waveguide 156. During this process, the plane 156a of the waveguide 156 facing the photodiode 26 is formed to terminate at the most The wiring on the lower layer diffuses to prevent the film 丨 59a. That is, the formation of the zither ^56 137409. Doc 39· 201010068 to reach the lowermost wiring diffusion preventing film 159a without passing through the wiring diffusion preventing film 159a of the lowermost layer. Further, a planarization film 90, an on-chip color filter 34, and a crystal-loaded microlens 35 are formed in the pixel section 23. Further, as will be described in detail later, in the present embodiment, the thickness t1 of the insulating interlayer is set to be smaller, wherein the thickness of the insulating interlayer is from the surface of the semiconductor substrate 22 (i.e., the surface of the photodiode 26). The measurement includes the insulating film 39, the anti-reflection film 4, and the first insulating interlayer 311 to the lowermost wiring diffusion preventing film 159a. That is, in order to generate high sensitivity at a blue light wavelength, the film thickness t1 is set in the range of 220 to 320 nm, 370 to 470 nm, or 530 to 630 nm. As shown in Figure 29, which includes a graph of sensitivity as a function of film thickness t1 measured from the surface of the substrate, if just above k and 'film thickness t is 220 to 320 nm, 370 to 470 nm Or in the range of 530 to 630 nm, it is indicated that a blue light sensitivity equal to or greater than one-half the sensitivity difference between the apex and the valley of the sensitivity curve can be obtained. That is, the sensitivity to the approximation equal to or greater than x + [(y_x)/2] is obtained, the t variable X is the sensitivity value at the apex of the curve, and y is the value at the next trough. Since the other parts of the configuration are similar to those previously mentioned with reference to FIG. 4 according to the first embodiment, the repeated description thereof is omitted herein. It should be noted that the configuration of the multi-level wiring layer 33 and the anti-reflection film 40 formed on the surface of the photodiode 26 is a more detailed configuration of the above configuration according to the first embodiment. Regarding the configuration of the solid-state imaging device 55 according to the sixth embodiment, an image 137409 is formed. Doc • 40- 201010068 The protrusion height h8R of the second isolation region 45 in the prime segment 23 is the same as the protrusion height h6 of the first isolation region 43 in the peripheral circuit segment 24, that is, as low as 4 〇 nm or more. less. With this configuration, the film thickness t丨 can be formed to be thinner (measured from the surface of the photodiode 26 to the wiring diffusion preventing film 159a on the lowermost layer in contact with the bottom of the waveguide 156), including the insulating interlayer ( 39, 4〇, 32). Generally, the minimum film thickness of the insulating interlayer 3 1 is limited so as not to induce deposition of the polycrystalline seconds gate electrode on the isolation region 45 having the STI structure during the polishing process after the formation of the insulating interlayer. With the present embodiment, the film thickness can be suppressed during the polishing process by the same protrusion height h8a of the second isolation region 45 forming the pixel portion 23肀 and the protrusion height h6 of the first isolation region 43 of the peripheral circuit portion 24 being the same. A grinding process that varies and achieves a film thickness dl from the top surface of the gate electrode as small as 9 〇 nm becomes feasible. For example, when a projection height h8 of 3 〇 nm is assumed, the entire insulating interlayer can be treated to reduce its film thickness by about 7 〇 nm from the thickness shown in the first comparative example in Fig. 30. Incidentally, in the first comparative example shown in FIG. 30, the protrusion height h3 of the isolation region 43 having the STI structure in the peripheral circuit section 24 is regarded as 30 nm' and the pixel section 23 has The protrusion height h4 of the isolation region 45 of the STI structure is also considered to be 80 nm. In this case, in order to retain the insulating interlayer on the gate electrode, the amount of polishing must be appropriately controlled. Therefore, the final film thickness t2 of the insulating interlayer is obtained to be about 650 nm and thus optimization of sensor sensitivity may not be achieved. It is to be noted that other regions shown in Fig. 30 that are similar to those of the other regions in Fig. 28 are shown with the same numerical values and the repeated description thereof is omitted herein for the purpose of comparison. With the embodiment of the present invention, since it has a film thickness t1 as described above, 137409. Doc -41- 201010068 Thinning of the insulating interlayer and providing a waveguide 156 facing the photodiode 26, thereby improving the concentrating efficiency of light incident on the photodiode 26, and improving sensor sensitivity, especially Blue light sensitivity. Fig. 29 shows the thickness of the insulating interlayer measured from the surface (the surface of the photodiode) 26 of the photodiode 26 to the wiring diffusion preventing film 159a formed by the sic by the configuration of the solid-state imaging device according to the sixth embodiment. A graphical curve of the sensitivity changes of the respective colors (red, green, and blue) of the function, where curve R shows the sensitivity change of the red wavelength, curve G is for green, and curve B is for blue. A ruthenium oxide film 39 is formed on the Si surface, and a nitride nitride film 40' is further formed thereon and the total thickness of the two films 39 and 40 is in the range of about 70 nm. It should be noted that 'the cloud is resistant to reflection and film treatment (determining the limit for its maximum film thickness by considering the ability to form contact vias), and films 39 and 40 can be formed to have a total thickness of about 2 〇 to 12 〇 nm. In the scope. The refractive index of the insulating interlayer thus formed is in the range of 14 to 15. As previously briefly described, the graphical curves of the sensitivity changes for the individual colors shown in Figure 29 were found to improve the sensitivity of blue, which typically has lower luminous efficiency, and for 220 to 320 nm, 370 to 470 nm. The film thickness tl in the range of 530 to 630 nm increases the sensitivity of the sensor most. That is, 'such as blue sensitivity' can obtain a sensitivity equal to or greater than one-half the sensitivity difference between the apex and the valley of the sensitivity curve. In addition, light diffraction occurs when the waveguide structure is included, which is mainly attributed to (a) the material buried in the waveguide (ie, the second core layer 89) and (b) from the surface of the photodiode 26 to the most The difference in refractive index between the layers of the insulating layer formed by the diffusion of the lower wiring prevents the film from being formed (that is, the interference of the incident light is changed by the refractive index of 137409. Doc 201010068 causes and increases or weakens the incident light depending on the thickness of the insulating film. Therefore, there is an optimum range of film thickness of the condensing structure. Therefore, in the present embodiment, the film thickness optimization range can be set in the range of 22 〇 to 32 〇 11111, 3 70 to 47 〇 11111 or 530 to 63 〇 11111. In the first comparative example, since the projection height of the isolation region is relatively 咼 on the side of the pixel section, the reflection of incident light is caused by the extension of the isolation region, and the sensitivity of the sensor is correspondingly reduced. However, in the present embodiment, since the projection height of the second isolation region is lower on the side of the pixel section, the reflection of the incident light by the projection is reduced and the sensitivity of the sensor can be improved. Incidentally, when the two films 39 and 40 having a total film thickness in the range of about 20 to 120 nm are formed, the above range of film thicknesses t of 220 to 320 nm, 370 to 470 nm, and 530 to 630 nm is as follows It varies with the total film thickness. When the total film thickness of the two films 39 and 40 becomes less than 7 〇 nm (for example, 20 nm), the peak position of the sensitivity curve of FIG. 29 is shifted to the left in the figure with respect to the peak position at the thickness of 7 〇ηηι Side (in the direction of increasing the film thickness of the insulating interlayer 311). The amount of displacement corresponding to the current thickness is obtained, which is (dN_7〇)x(nN_n〇)' which is derived from the general relationship used in optical interference: "film thickness". * "Refractive Index" = "Optical Film Thickness". Conversely, when the total film thickness of the two films 39 and 4 becomes greater than 70 nm (for example, 120 nm), the peak position of the sensitivity curve of FIG. 29 is shifted to the right side with respect to the peak position at the thickness of 70 nm (in the minus The displacement corresponding to the thickness is obtained in the direction of the film thickness of the small insulating interlayer 3, which is (70-dN)x(nN-nO). The above code dN refers to the total film thickness of the films 39 and 40, nN The refractive index of the tantalum nitride film 40 is referred to, and nO refers to the refractive index of the hafnium oxide film 39. 137409. Doc •43- 201010068 by this configuration of the isolation region in this embodiment, with other configurations in which the isolation regions in the pixel segments are formed to have the same buried depth as the isolation regions in the peripheral circuit segments In contrast, as previously described in the first embodiment, generation of white spots in the photodiode 26 is suppressed and sensor sensitivity can be further improved. By forming the waveguide so as to terminate at the configuration at the wiring diffusion preventing film, the depth of the waveguide can be kept constant. Incidentally, as the miniaturization of the pixel progresses, if the protruding height of the isolation region on the side of the pixel segment is as large as described in the first comparative example, ax is intended to be formed even in the interlayer of the insulating layer and subsequently flattened. After the polishing step, the uniform planarization of the top surface of the structure is difficult to achieve due to the relatively large step height and the planarization of the wiring diffusion preventing film formed on the structure is difficult to achieve. When the process is further developed in this case to form a multi-level wiring layer and subsequently forming a groove of the waveguide in the multi-level wiring layer, it becomes difficult to form the groove so as to accurately terminate at the lowermost wiring diffusion preventing film. As a result, even if it is intended to form the waveguide by subsequently embedding the cover material layer and the core material layer in the recess, it is expected that the waveguide may not be formed correctly so as to terminate at the lowermost wiring diffusion preventing film. In contrast, by the present embodiment, since the protrusion of the second isolation region in the pixel section is low south, it is feasible to planarize the interlayer of the insulating layer, and a proper waveguide can be formed to terminate the diffusion prevention at the lowest wiring. This is also true at membranes even in device configurations with miniaturized pixels. In addition, as the miniaturization of the pixel progresses, if the protruding height of the isolation region on the side of the pixel segment is as large as described in the first comparative example, then 137409. Doc • 44 - 201010068 When the insulating interlayer is formed by inlaying this portion between the higher projections, there is a problem of forming voids. However, with this example, since the height of the protrusion is low, the formation of voids can be avoided, the efficiency of embedding the interlayer of the insulating layer can be improved, and the formation of the interlayer of the insulating layer can be satisfactorily performed. Further, according to the present embodiment, by suppressing the change in the film thickness in the wafer caused by polishing the insulating interlayer, the effect of the difference in sensitivity between the center and the periphery of the barrier (so-called mask) can be achieved. In addition, according to the sixth embodiment, the present embodiment can also provide effects similar to those previously described with respect to the configuration description according to the first embodiment, including increasing sensor sensitivity, improved image characteristics, and saturation semaphores. Short circuit faults caused between pixel transistors, reduced number of processes, improved manufacturing yield, and the like. Incidentally, the above-mentioned values of the optimum film thickness u in the range of 220 to 32 〇 11111, 37 〇 to 47 ,, or 53 〇 to 63 〇 (4) can be applied not only to the sixth embodiment but also to the application. In the first to fourth embodiments. [Seventh Embodiment of Solid-State Imaging Device] Figs. 31 and 32 are views showing a solid-state imaging device according to a seventh embodiment of the present invention. Figure 31 is a simplified plan view showing the layout of pixels in an image forming area which is a main portion of a solid-state imaging device. 32 is a cross-sectional view taken along line AA of the structure of FIG. 31. The solid-state imaging device 171 of the present embodiment is provided, which includes a pixel section B and a peripheral circuit section 24, wherein the pixel section 23 includes two-dimensional arrays. A plurality of pixels 172 of the array form each of the pixels $ in the: dimensional array, which includes a photodiode (PD) 26 and a plurality of pixel transistors. As by 137409. Doc-45-201010068 Illustrated in the layout shown in FIG. 31, each of the pixels 172 is formed in the present embodiment, which includes a photodiode (PD) 26 and a plurality of transistors, that is, three kinds of transistors. Such as transfer transistor Tr1, reset transistor Tr2, and amplifying transistor Tr3. A transfer transistor Tr1 is formed which includes a source/drain region 173 serving as a floating diffusion (FD) and a formed transfer gate electrode 176 (having a gate insulating film formed thereunder). Forming a reset transistor Tr2 in a manner similar to that described above, the reset transistor Tr2 including a pair of source and drain regions 173 and 174' and a reset gate electrode 177 formed (having another one formed thereunder) Gate insulating film). An amplifying transistor Tr3 is formed which includes a pair of source and drain regions 174 and 175, and an amplified gate electrode 178 (having another gate insulating film formed thereunder). Further, also in the embodiment of the present invention, as shown in Figs. 3A and 32, the isolation region 86 of the p-type impurity region is formed around the periphery of the photodiode (PD) 26. That is, the photodiode (pD) 26 is isolated by a pn junction with the isolation region 86. On the other hand, the region of the pixel transistor such as the transfer transistor Tr1, the reset transistor Tr2, and the amplifying transistor Tr3 is isolated using the second isolation region 45 having the same STI structure as previously mentioned. Since the other portions of the configuration are similar to those previously mentioned in the sixth embodiment, the regions shown in FIG. 32 that are similar to those in FIG. 28 are shown with the same numerical values and are omitted herein. description. With regard to the configuration of the solid-state imaging device 171 according to the seventh embodiment, the junction isolation of the photodiode (1 > 1) 26 is performed by using the isolation region 86 of the P-type impurity region, eliminating halation and Further improve sensor sensitivity. That is, because the protruding portion (with the protruding height h8) in the second isolation region 45 is not 137409. Doc 201010068 exists in the vicinity of the photodiode (PD) 26, so that blooming is not caused by the protruding portion and the concentrating efficiency is further improved. In the pixel section 23, since the structure is adapted to have a combination of pn junction isolation and STI isolation, the isolation tolerance is improved and the gate parasitic capacitance can be reduced. Further, regarding the seventh embodiment of the present invention, Effects similar to those previously described with respect to the configuration description according to the sixth embodiment can be provided. '' Although the pixel configuration above is adapted to include a photodiode and a number of I pixel transistors', the configuration may alternatively be formed for structures having a plurality of pixels that are common to each other, such as where the seventh is similar In the embodiment, the other portion is isolated by the second isolation region 45 having the above-mentioned §τι structure by the Ρ 接 junction) 3⁄4 from the periphery of the photovoltaic < one polar body PD. Of course, the present configuration of the pn junction isolation around the photodiode (PD) can also be applied to the solid-state imaging devices according to the first to seventh embodiments. [Fourth Embodiment of Manufacturing Method] Next, a fourth embodiment of the method of manufacturing the solid-state imaging device according to the present invention will be described with reference to Figs. This embodiment is suitable for manufacturing the solid-state imaging device 55 according to the above-described sixth embodiment shown in Fig. 28, and is particularly suitable for forming an insulating interlayer and a waveguide. . Reference numerals 49 and 52 denote a P-type semiconductor region and a p-type semiconductor layer, respectively. In the manufacturing method according to the fourth embodiment, 'as illustrated in FIG. 33, first formed in the pixel portion 23 and the peripheral circuit portion 24 via the process steps illustrated in FIGS. 13A to 15E or FIGS. 18A to 19D, respectively. The trench 44 and the deep trench 41. Further, the insulating film 42 is buried in the trenches 44 and 41, respectively, so that the protruding heights h6 and h8 are the same to form a second 137409 each having a sti structure. Doc -47· 201010068 Isolation area 45 and first isolation area 43. Further, in the pixel section 23, a photodiode 26 and a pixel transistor 27 are formed. A logic circuit having a CMOS transistor is formed in the peripheral circuit section 24. On the insulating film 39 covering the oxidized chip on the surface of the photodiode 26, an anti-reflection film of a tantalum nitride film is formed, and then, for example, a Cvd method is used to form, for example, a ruthenium oxide film. An insulating interlayer 3 11 is then subjected to planarization grinding by a CMP method to obtain a desired film thickness t1. Next, referring to FIG. 34, a plurality of trenches 92 are formed at predetermined positions of the insulating interlayer 311, and the Cu wiring layer 158 is buried in the trench 92 and underneath it is formed with a button/nitridation for passivation. The barrier metal layer 157 of the button is used to form the first layer wiring 321 . Subsequently, on the entire insulating interlayer 311 including the surface of the first layer wiring 321, a first wiring diffusion preventing film 159a composed of a SiC film or a SiN film for preventing diffusion of the wiring 321 is formed, for example, in this example It is formed of a SiC film. Next, referring to FIG. 35, a second insulating interlayer 312 is formed on the first-layer wiring diffusion preventing film 159a using a process step similar to the above-described process steps, and a barrier metal layer buried in the trench 92 is formed. The second layer wiring 322 of the 157 and Cu wiring layers 158 and the second wiring diffusion preventing film 1 59b. Subsequently, a third insulating interlayer 313, a third barrier 323 having another barrier metal layer 157 buried in the trench 92 and another Cu wiring layer 158, and a third wiring diffusion preventing film 159c are formed. . Further, a fourth insulating interlayer 314 is formed, another barrier metal layer 157 buried in the trench 92, and a fourth wiring 324 of the other Cu wiring layer 1W, and a fourth wiring diffusion preventing the pancreas 1 59d. In addition, a fifth insulating layer is formed on the structure 137409. Doc -48· 201010068 The interlayer 3 1 5 is formed, thereby forming the multi-level wiring layer 3 3 . Next, referring to Fig. 36, the groove 87 is formed by selectively etching a portion of the multi-level wiring layer 33 facing the photodiode 26 so as to terminate at the lowermost wiring diffusion preventing film 159a as the first layer. The insulating interlayer layer 3 15 on the fifth layer, the wiring diffusion preventing film 59d and the insulating interlayer 3 14 on the fourth layer, the wiring diffusion preventing film 59e on the second layer, and the insulating interlayer 3 3, and The wiring diffusion preventing 臈 159b and the insulating interlayer 3 12 on the second layer perform this selective etching. Referring next to Fig. 37, a first core layer 88 including an inner wall of the recess 87 is formed. Thereafter, a second core layer (10) is formed on the first core layer 88 to inlay the recesses 87. The first core layer 88 and the second core layer 89 are formed of a hafnium oxide film or a tantalum nitride film. Thereby, the waveguide 156 composed of the first core layer 88 and the second core layer 89 is formed to reach the wiring diffusion preventing film 159a on the lowermost layer and facing each of the photodiodes 26. If the first core layer 88 is formed of a material having a refractive index higher than that of the material for forming the second core layer 89 and the insulating interlayer layer 3 1 (312 to 3 15) included in the multi-level wiring layer 33, It is then more difficult to leak light out of the waveguide and further increase sensor sensitivity. However, embodiments of the invention are not limited thereto. Also, a waveguide may alternatively be formed comprising a second core layer 89 formed of a material having a higher refractive index than the material forming the first core layer 88. Although not shown in the drawings, subsequent processing steps are performed to continuously form the planarization film 90, the crystal-loaded color filter 34, and the crystal-loaded microlens 35, thereby forming a solid-state imaging skirt according to the sixth embodiment. 5. Regarding the manufacture of the solid-state imaging device according to the fourth embodiment of the manufacturing method 137409. Doc • 49- 201010068 The method 'by grinding the CMP method after forming the second isolation region 45 and the first isolation region 43 such that their protrusion heights h6 and h8 are the same, after forming the first insulating interlayer 3丨丨A satisfactory planarization process becomes feasible during the process. Therefore, the thickness of the first insulating interlayer 3 is reduced, and the film thickness 11 of the insulating interlayer from the surface of the photo-electric body 26 to the wiring diffusion preventing film 59a on the first layer can also be reduced. Further, the waveguide 156 is formed at a position facing the photodiode 26. By achieving formation of an insulating interlayer having a film thickness t1, and by providing a waveguide 56, the light collecting efficiency of guiding incident light into the photodiode 26 is improved, and improved sensor sensitivity can be manufactured. Solid-state imaging device 5 5. Since the formation of the recess 87 for forming the waveguide 156 is terminated at the first-layer wiring diffusion preventing film 159a instead of forming the recess 87 deeper, an undue increase in dark current can be avoided. Further, by terminating the groove 87 at the wiring diffusion preventing film 159a, the depth of the end point can be made uniform and the change in sensitivity can be suppressed. Furthermore, similar to those described above in accordance with the first and second embodiments of the fabrication method, a solid-state imaging device having improved pixel features including post-image features and saturation semaphores can be fabricated. Improve, prevent short-circuit faults between pixel transistors, and so on. In addition, after the trenches 44 and 41 are formed on the side of the pixel section 23 and the side of the peripheral circuit section 24, respectively, deposition of the insulating layer 42 and grinding by the CMP method are performed in the same process, and then formed. One and the second isolation zone "and". Thus, the number of processes can be reduced accordingly. [Fifth Embodiment of Manufacturing Method] 137409. Doc-50-201010068 A fifth embodiment of a method of manufacturing a solid-state imaging device according to the present invention will be described with reference to FIG. This embodiment is suitable for manufacturing a solid-state imaging device according to the above-described seventh embodiment shown in Figs. 3 and 3, and is particularly suitable for forming an isolation region thereof. In the manufacturing method according to the fifth embodiment, as illustrated in FIG. 38, first in the pixel portion 23 and the surrounding circuit portion 24 via the processing steps illustrated in FIGS. 13A to 15E or FIGS. 18A to 19D, respectively. Shallow trenches 44 and deep trenches 41 are formed. Further, the second isolation region 45 and the first isolation region 43 each having the sti structure are formed by embedding the insulating films 42 in the trenches 44 and 41, respectively, so that the extension halves h6 and h8 are the same. Further, in the pixel section 23, a photodiode 26 and transistors Tr1, Tr2, and Tr3 as pixel transistors are formed to constitute a pixel. In the peripheral circuit section 24, a logic circuit including a CM 〇 S transistor is formed. Further, a separation region 86 of a p-type impurity region is formed in the periphery of the photodiode in the pixel portion 23. An anti-reflection film 4 of a tantalum nitride film is formed on the insulating film 39 of the hafnium oxide film formed on the surface of the photodiode 26 (after that, for example, the first layer of the hafnium oxide film is formed by a CVD method) The interlayer 311 is insulated, and then subjected to planarization grinding by a CMP method to obtain a desired film thickness. Subsequently, solid-state imaging according to the seventh embodiment can be manufactured via the same process steps as described above with reference to FIGS. 34 to 37. Regarding the manufacturing method of the solid-state imaging device according to the fifth embodiment of the manufacturing method, the method includes a process of forming the isolation region 86 of the P-type impurity region in the periphery of the photodiode 26 in the pixel portion 23. The isolation zone% does not extend 137409. Doc -51- 201010068 There is no protrusion outside the surface of the substrate and around the photodiode 26. Therefore, since the projecting portion in the periphery of the photo-electric body 26 does not cause halation, a solid-state imaging device 171 having further improved concentrating efficiency can be manufactured. Moreover, the effects similar to those previously described for the manufacturing method according to the fourth embodiment can be provided by the present method. Embodiments of the present invention are applicable to surface-illuminated and back-illuminated solid-state imaging devices. Regarding the CMOS solid-state imaging device as mentioned before, the embodiment of the present invention can be applied to a surface illumination type image forming apparatus that provides light incident from the side of the multi-level wiring layer, and is provided opposite to the side of the multi-level wiring layer from the substrate A back-illuminated imaging device that emits light on the back side. Further, the solid-state imaging device according to the embodiment of the present invention can be applied not only to the above-described area image sensor but also to the linear image sensor. The solid-state imaging device according to an embodiment of the present invention can be suitably adapted to various electronic devices such as a camera having a solid-state imaging device, a mobile device having a camera, and the like having a solid-state imaging device. Fig. 39 is a schematic diagram showing a camera having a solid-state imaging device as an example of the above electronic device according to an embodiment of the present invention. A camera (electronic appliance) 80 according to the present embodiment is provided, which includes an optical system (optical lens) 81, a solid-state imaging device 82, and a signal processing circuit 83. Regarding the solid-state imaging device 82, any of the device orders described in the above embodiments can be preferably modified. The optical system 81 is configured to image image light (incident light) emitted from the subject onto the imaging surface of the solid-state imaging device. Thus, the signal charge is accumulated in a fixed period by the photoelectric conversion element included in the solid-state imaging device 82. Signal processing circuit 83 is configured to provide 137409. Doc-52-201010068 No. L processes the signal output from the solid-state imaging device 82, and then outputs the processed signal as an image signal. The & machine according to an embodiment of the present invention can be formed only as a camera module, which is formed by the modular optical system 8 and the solid state imaging device 82 and the signal processing circuit 83. The embodiment of the present month may be suitably adapted to the camera illustrated in the figure, and the mobile device having the camera (which is represented, for example, by a honeycomb module having a camera module). The structure can be configured as a module with imaging (so-called imaging module) formed by the modular optical system 81, the port "imaging device 82 and signal processing circuit 83. The package according to the present invention can be configured to have The electronic device of the imaging module. According to the electronic device of the embodiment, since the high-quality image can be formed due to the sub-pixel feature of the solid-state imaging device, a high-performance electronic device can be provided. And, the solid-state imaging device according to the embodiment of the present invention may be suitably adapted to (4) solid-state imaging having a plurality of unit pixels arranged, each of which includes a photodiode and a plurality of pixels. The day body 'and (b) each of the solid-state m-shared pixels having the first plurality of so-called shared pixels arranged includes a second plurality of photodiodes. & transfer transistor' and includes each of the other pixel transistors such as reset, amplify, and select transistors. The application of the present invention contains a Japanese priority patent application JP 2_-101971, Jp 2, which is filed on April 9, 2008, August 31, 2008, and August 4, 2008, respectively. 〇〇8_199〇5〇, jp 2 delete - 2〇1117, the subject matter of the subject, and the contents of the case 137409. Doc -53- 201010068 is incorporated herein by reference. Those skilled in the art should be aware of various modifications, combinations, sub-groups, and changes in visual design requirements and other factors as long as they are within the scope of the additional patent application or its equivalent. BRIEF DESCRIPTION OF THE DRAWINGS [Brief Description of the Drawings] The first part of the first part 1 is a diagram illustrating a prior art solid-state imaging device; and FIG. 2A is a plan view illustrating a prior art pixel structure included in an imaging device for the purpose of explaining the problems of the prior art. 2B is a cross-sectional view taken along line A_A of the structure of FIG. 2A; solid form 3 is a diagram generally illustrating a configuration suitable for an image device according to an embodiment of the present invention; A schematic diagram of a solid portion of a first embodiment of a low-explosion-deficient first embodiment according to the present invention is illustrated; Figure 5 of the crucible device is included in the solid state of Chengde.  FIG. 6 is a schematic diagram illustrating a main portion of a solid-state imaging device according to a second embodiment of the present invention; FIG. 7 is a diagram illustrating a second portion of the solid-state imaging device according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 8 is a schematic view showing a portion of a solid-state imaging device according to a fourth embodiment of the present invention; FIG. 9 is a fifth embodiment of a month according to the present invention. A schematic diagram of the main part of the solid-state imaging package; Doc-54- 201010068 Fig. 1 is an enlarged cross-sectional view of an isolation region of a sti structure of a pixel segment according to a fifth embodiment; Fig. 11 is a schematic plan view for describing a pixel transistor of a fifth embodiment; An enlarged cross-section of a sti isolation region for comparison purposes; FIGS. 13A and 13B illustrate, in a series of schematic cross-sectional views, a process step for fabricating a solid-state imaging device according to a first embodiment of the manufacturing method of the present invention 14C and 14D illustrate a sequence of process steps for fabricating a solid-state imaging device according to a first embodiment of the manufacturing method of the present invention in a series of schematic cross-sectional views; FIGS. 15E and 15F are illustrated in a series of schematic cross-sectional views. A sequence of process steps for fabricating a solid-state imaging device according to a first embodiment of the manufacturing method of the present invention; FIGS. 16G and 16H illustrate a first embodiment of a φ manufacturing method according to the present invention in a series of schematic cross-sectional views a sequence of process steps for fabricating a solid state imaging device; 171 and 17J illustrate, in a series of schematic cross-sectional views, a process sequence for fabricating a solid-state imaging device according to a first embodiment of the manufacturing method of the present invention: a sequence; FIG. 18 A and i 8 B A series of schematic cross-sectional views illustrating a sequence of process steps for fabricating a solid-state imaging device according to a second embodiment of the manufacturing method of the present invention; and 19D illustrates a 1374〇9,d according to the present invention in a series of schematic cross-sectional views. 〇 c • 55· 201010068 A sequence of process steps for manufacturing a solid-state imaging device of a second embodiment of the manufacturing method; FIGS. 20E and 20F illustrate a second embodiment of the manufacturing method according to the present invention in a series of schematic cross-sectional views a sequence of process steps for fabricating a solid-state imaging device; FIGS. 2G and 21H illustrate, in a series of schematic cross-sectional views, a sequence of process steps for fabricating a solid-state imaging device according to a second embodiment of the manufacturing method of the present invention; Figure 22 is a series of schematic cross-sectional views illustrating a sequence of process steps for fabricating a solid-state imaging device in accordance with a second embodiment of the manufacturing method of the present invention; Figure 23A 23B illustrates a sequence of process steps for fabricating a solid-state imaging device according to a third embodiment of the manufacturing method of the present invention in a series of schematic cross-sectional views; FIGS. 24C and 24D illustrate the fabrication according to the present invention in a series of schematic cross-sectional views. A sequence of process steps for producing a solid-state imaging device I using a third embodiment of the method; FIG. 25 is a schematic cross-sectional view of U for explaining a third embodiment of the manufacturing method of the present invention for manufacturing a solid-state imaging device Figure 26 is an enlarged view of Figure 24C; Figure 27 is an enlarged view of Figure 24D; Figure 28 is an illustration of a ten item 73 according to the present invention. <Schematic diagram of the main part of the solid-state imaging device of the sixth embodiment; 137409.doc 201010068 FIG. 29 shows a graph showing the sensitivity of the respective colors according to the thickness of the insulating interlayer, according to an embodiment of the present invention, between the insulating layers The layer thickness is measured from the surface of the photodiode serving as the photoelectric conversion element to the wiring diffusion preventing film on the first layer, and these pattern curves are prepared for the purpose of explanation. Figure 30 is a schematic view showing the main part of the solid-state imaging device according to the first comparative example; Figure 31 is a schematic view showing the main part of the solid-state imaging device according to the seventh embodiment of the present invention; Figure 3 is a view along Figure 31 Cross-sectional view taken along line AA of the structure; FIG. 3 is a schematic cross-sectional view showing a process for manufacturing a solid-state imaging device according to a fourth embodiment of the manufacturing method of the present invention; FIG. 34 is a schematic cross-sectional view illustrating Process step for manufacturing a solid-state imaging device according to a fourth embodiment of the manufacturing method of the present invention; FIG. 35 is a schematic cross-sectional view showing a process for manufacturing a solid-state imaging device according to a fourth embodiment of the manufacturing method of the present invention Figure 36 is a schematic cross-sectional view showing a process for fabricating a solid-state imaging device according to a fourth embodiment of the manufacturing method of the present invention; and Figure 37 is a schematic cross-sectional view showing a fourth manufacturing method according to the present invention. Process steps for fabricating a solid-state imaging device of an embodiment; FIG. 38 illustrates a fifth embodiment of a manufacturing method according to the present invention in a schematic cross-sectional view Process for manufacturing a solid-state imaging device of the step; and FIG. 39 is a schematic diagram of a simplified embodiment of the camera configuration adapted consistent set of solid-state imaging Pei embodiment according to the present invention as an embodiment. 137409.doc -57- 201010068 [Description of main component symbols] 1 Solid-state imaging device 2 Pixel 3 Pixel section 4 Vertical drive circuit 5 Line signal processing circuit 6 Horizontal drive circuit 7 Output circuit 8 Control circuit 9 Vertical signal line 10 Horizontal signal line 11 Semiconductor substrate 21 Solid-state imaging device 22 Semiconductor substrate 23 Pixel section 24 Peripheral circuit section 25 Unit pixel 26 Photodiode 27 Pixel transistor 28 Source/nopole region 29 Gate insulating film 30 Gate electrode 31 Insulating interlayer 32 Multilayer Wiring/Multiple Wiring Layers 137409.doc -58- 201010068 33 Multi-level Wiring Layer 34 Crystal-Loaded Color Filters • Light Sheets 35 Crystal-Loaded Microlenses 36 P-Type Semiconductor Well Areas 37 n-Type Charge Accumulation Area — 38 Ρ+Semiconductor 39. Insulating film 40 Nitride film/anti-reflection film stomach 41 Channel 41a Channel 42 Insulation layer 42a Insulation area 43 First isolation area 44 Channel 45 Second isolation area 4 8 Solid-state imaging device 49 Ρ-type semiconductor layer /ρ-type semiconductor region · 51 solid-state imaging device, 52 半导体-type semiconductor layer 54 solid-state imaging device 55 solid-state imaging device 56 Electrode 57 parasitic channel component 59 pit 137409.doc -59- 201010068 60 P-type impurity 61 insulating film 61a opening 62 opening 63_resist mask 64 opening 65 resist mask 67 resist mask 71 thermal oxidation Film/Oxide Film 71a Thermal Oxide Film/Oxide Film 73 Anti-Name Mask 74 Resist Mask 76 Resist Mask 81 Optical System 82 Solid-State Imaging Device 83 Signal Processing Circuit 86 Isolation Area 87 Groove 88 First Core Layer 89 Second core layer 90 Flattening film 92 Trench 101 CMOS solid-state imaging device 102 Semiconductor substrate 137409.doc -60- 201010068 103 Pixel section 104 Peripheral circuit section 107 Photodiode 108 Pixel transistor 109 Source / > and polar regions • 110 unit pixels • 112 insulating film 113 wiring layer w 114 multi-level wiring layer 115 crystal-loaded color light film 116 crystal-loaded microlens 121 isolation region 122 P + diffusion region 123 insulation layer 125 isolation region win 126 channel Ditch 127 Insulation _· 131 Gate electrode 131A Gate electrode 131B Gate electrode 131C Gate electrode 133 Polycrystalline film 133a Polycrystalline residue 134 n+ Source/drain 137409.doc -61 · 201010068 156 156a 157 158 159 159a 159b 159c 159d 171 172 173 174 175 176 177 178 311 312 313 314 315 321 waveguide plane barrier metal layer copper wiring layer interlayer wiring diffusion preventing film first interlayer wiring diffusion prevention Wiring diffusion preventing film on the film/lower layer, second interlayer wiring diffusion preventing film, third interlayer wiring diffusion preventing film, fourth interlayer wiring diffusion preventing film solid-state imaging device, pixel source/no-polar region, and polar/source region > and pole transfer gate electrode reset gate electrode amplification gate electrode insulation interlayer / first layer insulation interlayer insulation layer / second layer insulation interlayer insulation layer / third layer insulation interlayer insulation layer / Four-layer insulating interlayer insulating interlayer/fifth insulating interlayer wiring layer/first wiring 137409.doc -62- 201010068 322 wiring layer/second wiring 323 wiring layer/third wiring 324 wiring layer/first Four-layer wiring 711 opening 712 opening ❹ 137409.doc -63-

Claims (1)

201010068 VII. Patent application scope: 1. A solid-state imaging device, comprising: a pixel segment; a peripheral circuit segment; wherein the peripheral circuit segment is formed on a semiconductor substrate and has one of an STI structure. An isolation region; and a second isolation region formed on the semiconductor substrate having the STI structure in the pixel portion, wherein a portion of the semiconductor substrate buried in the semiconductor substrate is buried in the semiconductor portion than the first isolation region One of the substrates is shallow and the height of a top surface is equal to the height of one of the top surfaces of the first isolation region. 2. The solid-state imaging device of claim 1, further comprising: an impurity implantation region formed at an interface between the second isolation region of the pixel segment and a photoelectric conversion element. 3. The solid-state imaging device of claim 1, wherein one of the photoelectric conversion elements is partially below the second isolation region. A method of manufacturing a solid-state imaging device, comprising the steps of: forming a first trench in a portion of a first isolation region of a peripheral circuit segment to be formed on a semiconductor substrate, and wherein the semiconductor Forming a second trench in a portion of the substrate to be formed in one of the second isolation regions of the pixel segment, the second trench being shallower than the first trench; and including the first trench and the first An insulating layer is formed on a structure inside the two trenches, and I37409.doc 201010068 first isolation region and second isolation region having surface heights equal to each other are formed by grinding the insulating layer. 5. The method of manufacturing a solid-state imaging device according to claim 4, wherein in the step of forming the first isolation region and the second isolation region, the insulating layer is ground such that the first isolation region and the second isolation region are The surface of the semiconductor substrate has an extension height in the range of 0 to 40 nm. 6. The method of manufacturing a solid-state imaging device of claim 4, wherein the step of forming the first trench and the second trench comprises: forming any one of the first trench and the second trench; and subsequently Forming either of the second trench and the first trench. 7. The method of manufacturing a solid-state imaging device according to claim 4, wherein the step of forming the first trench and the second trench comprises: forming a first trench having a same depth by a simultaneous surname engraving process and a second trench; and then the first trench is formed by an etching process to be deeper than the second trench. 8. An electronic device comprising: a solid state imaging device; an optical system configured to direct incident light to one of the photoelectric conversion elements included in the solid state imaging device; and " once configured to process from a signal processing circuit for solid-state output signals of the device; the solid-state imaging device includes: a pixel segment; a peripheral circuit segment; 137409.doc -2· 201010068 in the peripheral circuit segment on a semiconductor substrate a first isolation region having an STI structure formed thereon; and a second isolation region formed on the semiconductor substrate having the STI structure in the pixel portion, the portion of the semiconductor substrate being buried in the semiconductor substrate A portion of the first isolation region buried in the semiconductor substrate is shallow, and a top surface has a height equal to a height of a top surface of the first isolation region. 9. The electronic device of claim 8, wherein the solid-state imaging device comprises an impurity implantation region formed in a region adjacent to one of an interface between the pixel-isolation region and a photoelectric conversion element of the pixel segment make. 10. The electronic device of claim 9, wherein one of the photoelectric conversion elements is partially below the second isolation region. 137409.doc