JP2007266167A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To excellently mitigate electrolysis convergence by allowing an AC edge to be gentle and preventing the generation of a divot in the upper end section of a trench. <P>SOLUTION: A method for manufacturing a semiconductor device includes: a process for forming a first oxide film on a semiconductor substrate; a process for forming a silicon nitride film on the first oxide film; a process for forming an opening part to reach the semiconductor substrate by etching the first oxide film and the silicon nitride film; a process for forming a second oxide film on the semiconductor substrate in the opening part, the surface of the silicon nitride film, and a side surface in the opening of the silicon nitride film by radical oxidation; a process for removing the second oxide film on the semiconductor substrate in the opening part and the surface of the silicon nitride film; a process for forming a groove (the trench) on a silicon substrate by defining the silicon nitride film and the second oxide film of the side wall of the silicon nitride film as a mask; and a process for forming a third oxide film in the groove part. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to STI (Shallow Trench) which is element isolation in a semiconductor device.
Isolation).

  Conventionally, a LOCOS (local oxidation of silicon) method has been mainly used as a method for forming an element isolation region in a manufacturing process of a semiconductor device. However, the LOCOS method has a large dimensional conversion difference due to bird's beaks. For this reason, it is difficult to miniaturize the element, which hinders high density of the element.

  In recent years, therefore, a trench isolation method in which an element isolation insulating film is embedded in a trench has been used. According to this method, since the minimum separation width between elements can be reduced to 0.2 μm or less, a high-density LSI can be manufactured.

  6 to 8 are cross-sectional views for explaining steps relating to a method of manufacturing a semiconductor device by a conventional trench isolation method. First, as shown in FIG. 6A, a protective oxide film 2 and a silicon nitride film 3 are grown on the surface of the semiconductor substrate 1.

  Next, as shown in FIG. 6B, after a resist mask (not shown) is formed on the silicon nitride film 3 by lithography, the silicon nitride film 3 and the protective oxide film in a region not covered with the resist mask are formed. 2 is etched.

  Next, as shown in FIG. 6C, the semiconductor substrate 1 in a region not covered with the silicon nitride film 3 is etched to form a trench 4.

  Next, as shown in FIG. 7D, the surface of the semiconductor substrate 1 is oxidized, thereby forming the in-trench protective oxide film 5 on the side and bottom surfaces of the trench 4.

  Next, as shown in FIG. 7E, a silicon oxide film 6 is deposited on the semiconductor substrate 1 by a CVD (chemical vapor deposition) method using high density plasma. At this time, the silicon oxide film 6 is formed so as to completely fill the inside of the trench 4.

  Next, as shown in FIG. 8F, the surface of the silicon oxide film 6 is planarized by using a chemical mechanical polishing method (CMP) or an etch back method. The planarization is performed until the silicon nitride film 3 is completely exposed.

  Next, as shown in FIG. 8G, the silicon nitride film 3 is removed with a heated phosphoric acid aqueous solution or the like.

  Next, as shown in FIG. 8H, the protective oxide film 2 is wet-etched with a buffered hydrofluoric acid aqueous solution or the like, thereby completing the trench isolation structure. An impurity diffusion layer (not shown) may be formed in the semiconductor substrate 1 before the protective oxide film 2 is etched.

  After the trench isolation structure is completed, known processes for forming a semiconductor element such as a gate oxide film and a gate electrode are performed. In order to form the gate electrode, a gate oxide film and gate electrode polysilicon are grown on the surface of the semiconductor substrate 1. Next, after a resist mask (not shown) is formed on the gate electrode polysilicon by lithography, the gate electrode polysilicon and the gate oxide film in a region not covered with the resist mask are etched to form the gate electrode. Is completed.

  However, in the STI formed by the conventional method, as shown in FIG. 8 (H), the AC edge is steep and stress is high, and thinning occurs in the gate oxide film formed in a later process, and the breakdown voltage characteristic at the edge There was a problem of deterioration. In addition, as shown in the figure, a divot 7 caused by the difference in the etching rate (HF rate) between the thermal oxide film and the HDP oxide film is generated at the STI edge, and this divot 7 is generated during gate polysilicon electrode processing (dry etching). It was difficult to remove the polysilicon accumulated in the substrate. If polysilicon remains in the divot 7, when a voltage is applied to the gate electrode, the electric field concentrates on the polysilicon in the divot 7, current easily flows through the gate oxide film, and the gate electrode is short-circuited. Such a problem occurred.

Therefore, as shown in Patent Document 1 and Patent Document 2, a method of forming a trench after forming a LOCOS oxide film has been proposed.
JP 2002-76109 A JP 2002-190514 A

  However, even by the methods described in the two Patent Documents 1 and 2 described above, the relaxation of electrolytic concentration at the upper end of the trench was insufficient.

  The present invention has been made in view of the above situation, and the AC edge (the end of the trench buried with the HDP oxide film) is further relaxed to prevent the occurrence of a divot at the upper end of the trench, and the electrolytic concentration is good. An object of the present invention is to provide a method of manufacturing a semiconductor device that can be relaxed.

  In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a first oxide film on a semiconductor substrate; a step of forming a silicon nitride film on the first oxide film; Etching the first oxide film and the silicon nitride film to form an opening reaching the semiconductor substrate; and radical oxidation to form the opening on the semiconductor substrate in the opening and the surface of the silicon nitride film; Forming a second oxide film on the side surface of the silicon nitride film in the opening; and removing the second oxide film on the semiconductor substrate and on the silicon nitride film in the opening. Forming a trench in the silicon substrate using the silicon nitride film and the second oxide film on the sidewall thereof as a mask; forming a third oxide film inside the trench; Characterized in that it comprises a that step.

  The thickness of the second oxide film on the silicon nitride film is preferably 50 to 70% with respect to the thickness on the semiconductor substrate. The thickness of the second oxide film on the semiconductor substrate is preferably 300 to 500 mm.

  As described above, according to the method for manufacturing a semiconductor device of the present invention, a LOCOS oxide film is formed before forming a trench in a semiconductor substrate, and when the trench is formed, a part of the LOCOS oxide film is formed at the upper end of the trench. Therefore, the LOCOS oxide film, which is a thermal oxide film, has a lower etching rate than the silicon oxide film, which is a CVD oxide film, and the LOCOS oxide film prevents excessive etching of the silicon oxide film at the upper end of the trench. By such a function of the LOCOS oxide film, a divot does not occur at the upper end portion of the trench, and it is possible to alleviate electric field concentration when a voltage is applied to the gate electrode.

  The AC edge (end portion of the trench) becomes gentle and stress is relieved, and the edge characteristics of the gate oxide film formed in a later process can be improved. Further, since most of the edge is a thermal oxide film, formation of a divot can be suppressed. That is, in radical oxidation, since the dependence of the oxidation rate on the plane orientation is small, facets that leave a slow-oxidized crystal plane hardly occur, and the bird's beak has a good shape. Further, when the trench is formed by etching, the oxide film on the side wall of the silicon nitride film is left without being removed, so that the lateral progress during the subsequent etching with HF (hydrofluoric acid) is delayed, and the divot Formation is suppressed.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to examples. FIG. 1 is a cross-sectional view of a semiconductor device 100 for explaining an embodiment of the present invention, and schematically shows a cross-sectional state of a trench isolation structure portion of the semiconductor device 100 according to the present embodiment.

  As shown in FIG. 1, the trench isolation structure portion of the semiconductor device 100 according to this embodiment includes a trench 104 formed on the surface of a semiconductor substrate 101 and an in-trench protective oxide film (liner formed on the inner wall of the trench 104. Oxide film) 105, a silicon oxide film 106 embedded in the trench 104, and a LOCOS oxide film 108 formed at the upper end of the trench 104.

  Next, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. 2 to 5 are cross-sectional views for explaining steps related to a method of manufacturing a semiconductor device by the trench isolation method according to the present invention. First, as shown in FIG. 2A, a pad oxide film (protective oxide film) 102 is formed on the surface of a semiconductor substrate 101 which is a silicon substrate by thermal oxidation (850 ° C., wet oxidation).

  Thereafter, a silicon nitride film 103 is deposited on the protective oxide film 102 by low pressure chemical vapor deposition (LPCVD). The thickness of the silicon nitride film 103 is about 1500 mm. The processing conditions are 755 ° C., SiH 2 C = 100 ccm, and NH 3 = 1000 ccm.

  Next, as shown in FIG. 2B, after a resist mask (not shown) is formed on the silicon nitride film 103 by lithography, the silicon nitride film 103 and the pad oxide film in a region not covered with the resist mask are formed. 102 is etched to form an opening reaching the silicon substrate 101. Etching is preferably performed by a highly anisotropic dry etching technique, and the width of the etched portion can be set to 0.3 μm, for example.

  Next, as shown in FIG. 2C, an oxide film 108 is grown by about 500 mm in a 1100 ° C. H2 / O2 reduced pressure atmosphere by a general LOCOS method. Here, the H2 flow rate ratio is about 10 to 30%, and the pressure is 10 Torr or less.

  Up to this point, it is almost the same as the conventional LOCOS method, but this embodiment has one feature in that the thickness of the oxide film 108 to be grown is made thinner than the conventional one. Further, as the oxidation method shown in this embodiment, a radical oxidation method in which radicals are generated by thermal oxidation in an O2 / H2 mixed reduced pressure atmosphere is employed, and the silicon nitride film 103 is oxidized to form an oxide film 108 on the surface. To do. In addition, the radical oxidation method includes an oxidation method using a high-concentration oxidized radical generated by plasma. The thickness T1 of the oxide film 108 formed on the surface and side surfaces of the silicon nitride film 103 is about 50 to 70% of the thickness T0 of the thermal oxide film 108 on the silicon substrate 101. When T0 = 500 mm, T1 = 250-350cm.

  Next, as shown in FIG. 3D, the oxide film 108 on the silicon nitride film 103 and the oxide film 108 on the silicon substrate 101 are removed by anisotropic dry etching. At this time, the oxide film 108 on the sidewall of the silicon nitride film 103 is left without being removed.

  Next, as shown in FIG. 3E, the silicon substrate 101 is etched under anisotropic dry etching conditions with high selectivity using the silicon nitride film 103 and the oxide film 108 on the sidewall thereof as a mask to form a groove ( Trench) 104 is formed.

  Next, as shown in FIG. 3F, a thermal oxide film 105 is grown in a thickness of 150 to 200 μm at 1000 ° C. in a Pure-O 2 atmosphere (referred to as liner oxidation).

  Next, as shown in FIG. 4G, the trench 104 is filled with an oxide film 106 by HDP (High Density Plasma). Subsequently, as shown in FIG. 4H, the surface of the oxide film 106 is planarized by CMP. The planarization is performed until the silicon nitride film 103 is completely exposed. Note that after the trench 104 is filled with HDP, an annealing treatment at 1000 ° C. to 1100 ° C. may be performed.

  Next, in order to adjust the STI height, a 5% HF (hydrofluoric acid solution diluted to 5% by mass ratio) treatment is performed to remove a predetermined amount of the HDP oxide film 106 in advance, and then FIG. As shown in FIG. 3, the silicon nitride film 103 is removed with hot phosphoric acid (heated phosphoric acid aqueous solution).

  Next, as shown in FIG. 5J, by removing the pad oxide film 102 with 5% HF, an element isolation region (trench isolation structure) by STI is formed.

  After the trench isolation structure is completed, known processes for forming a semiconductor element such as a gate oxide film and a gate electrode are performed. In order to form the gate electrode, a gate oxide film 109 and gate electrode polysilicon 110 are grown on the surface of the semiconductor substrate 101 as shown in FIG. Next, after a resist mask (not shown) is formed on the gate electrode polysilicon 110 by lithography, the gate electrode polysilicon 110 and the gate oxide film 109 in a region not covered with the resist mask are etched. As shown in FIG. 1, the shape of the gate electrode (110) is completed.

  According to the present embodiment, the AC edge (the end portion of the trench 104 embedded with the HDP oxide film 106) becomes gentle, the stress is relieved, and the edge characteristics of the gate oxide film formed in a later process can be improved. Further, since most of the edge is a thermal oxide film, formation of a divot can be suppressed. That is, in radical oxidation, since the dependence of the oxidation rate on the plane orientation is small, facets that leave a slow-oxidized crystal plane hardly occur, and the bird's beak has a good shape. Further, when the trench 104 is formed by etching, the oxide film on the side wall of the silicon nitride film 103 is left without being removed, so that the lateral progress during the subsequent etching with HF (hydrofluoric acid) is delayed, Divot formation is suppressed.

The present invention has been described with reference to the embodiments. However, the present invention is not limited to the scope of the embodiments, and the design can be changed as appropriate within the scope of the technical idea described in each claim. Needless to say.

FIG. 1 is a sectional view showing the structure of a semiconductor device manufactured according to an embodiment of the present invention. FIG. 2 is a sectional view showing a manufacturing process according to the embodiment of the present invention. FIG. 3 is a sectional view showing a manufacturing process according to the embodiment of the present invention. FIG. 4 is a sectional view showing a manufacturing process according to the embodiment of the present invention. FIG. 5 is a sectional view showing a manufacturing process according to the embodiment of the present invention. FIG. 6 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device. FIG. 7 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device. FIG. 8 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.

Explanation of symbols

101 Semiconductor substrate 102 Pad oxide film (first oxide film)
103 Silicon nitride film 104 Trench
105 Liner oxide film 106 HDP oxide film (third oxide film)
108 LOCOS oxide film (second oxide film)

Claims (8)

Forming a first oxide film on a semiconductor substrate;
Forming a silicon nitride film on the first oxide film;
Etching the first oxide film and silicon nitride film to form an opening reaching the semiconductor substrate;
Forming a second oxide film on the semiconductor substrate in the opening, on the surface of the silicon nitride film, and on a side surface in the opening of the silicon nitride film by radical oxidation;
Removing the second oxide film on the semiconductor substrate and on the surface of the silicon nitride film in the opening;
Forming a trench in the silicon substrate using the silicon nitride film and the second oxide film on the sidewall thereof as a mask;
And a step of burying the inside of the groove with a third oxide film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second oxide film has a thickness of 50 to 70% on the silicon nitride film with respect to a thickness of the semiconductor substrate.   3. The method of manufacturing a semiconductor device according to claim 1, wherein a thickness of the second oxide film on the semiconductor substrate is 300 to 500 mm. 4.   4. The semiconductor according to claim 1, wherein the inside of the trench is filled with the third oxide film, and then planarized by CMP to remove the first oxide film and the silicon nitride film. Device manufacturing method. The silicon nitride film is removed with hot phosphoric acid,
5. The method of manufacturing a semiconductor device according to claim 4, wherein the first oxide film is removed with 5% HF.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the third oxide film is formed by HDP (High Density Plasma).   7. The method of manufacturing a semiconductor device according to claim 1, wherein a fourth oxide film is formed in the groove along the inner wall of the groove before the groove is filled with the third oxide film. The manufacturing method of the semiconductor device characterized by including the process of forming.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the fourth oxide film is formed by thermal oxidation.

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