TW200950630A - Method for making a circuit board - Google Patents

Method for making a circuit board Download PDF

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Publication number
TW200950630A
TW200950630A TW098108880A TW98108880A TW200950630A TW 200950630 A TW200950630 A TW 200950630A TW 098108880 A TW098108880 A TW 098108880A TW 98108880 A TW98108880 A TW 98108880A TW 200950630 A TW200950630 A TW 200950630A
Authority
TW
Taiwan
Prior art keywords
circuit board
circuit
airtight chamber
resist layer
layer
Prior art date
Application number
TW098108880A
Other languages
Chinese (zh)
Other versions
TWI395534B (en
Inventor
Goro Narita
Original Assignee
Element Denshi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Element Denshi Co Ltd filed Critical Element Denshi Co Ltd
Publication of TW200950630A publication Critical patent/TW200950630A/en
Application granted granted Critical
Publication of TWI395534B publication Critical patent/TWI395534B/en

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Examining Or Testing Airtightness (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

This invention provides a method for making a circuit board to improve a known method in which defects tend to occur by a protective resin which flows in the circuit area through pin holes during the process of covering the circuit elements and bonding wires with the protective resin layer, the pin holes being finely formed in the circuit board without being inspected entirely. In the method for making a circuit board of this invention. The method includes the steps of: arranging a plurality of circuit element mounting regions 15, forming a plurality of through hole electrodes 16 in the periphery of the circuit element mounting regions 15, covering at least one end of each of the through hole electrodes 16 with a resist layer, applying pressure onto the circuit board 1 and measuring the variation of the pressure, detecting defects of the pin holes, connecting to the through holes electrodes 16 in the resist layer, building the circuit elements in the circuit board 1 free of defects, bonding the protecting resin layer 16 to cover the circuit elements, to prevent the protective resin 16 from flowing into the through hole electrodes 16 from the resist layer 14.

Description

200950630 六、發明說明: 【發明所屬之技術領域】 本發明係關於一種電路基板之製造方法,特別是關於 在電路基板設置多數個電路元件載置區域,在各電路元件 載置區域之周圍形成多數個貫穿孔電極,以阻劑層覆蓋貫 穿孔電極之一端,對電路基板進行加壓而測定壓力變化, 在檢查連接於貫穿孔電極之阻劑層是否有針孔等後,將保 _ 護樹脂層附著在電路基板的電路基板之製造方法。 ’ 【先前技術】 © 近年來’就電路基板之製造方法而言,係以省材料型 之製造方法為主流,該方法係將多數個半導體元件等電路 元件予以密接組裝,在以保護樹脂總括進行模塑後,進行 切割而分割。 就該電路基板之檢查方法而言,一般係以目視檢查進 行之方法,主要進行以下方法:透過放大鏡一邊目視基板 之圖案形狀,一邊檢測出基板上之針孔或毛邊等缺陷的方 法;或將光源照射到整體基板並以是否有無從針孔或毛邊 ◎ 等缺陷部分洩漏之光來檢測缺陷的方法。 — 再者’亦有一種一邊與預先登錄之良品圖案匹配,一 1 邊檢查缺陷之有無的光學性圖案檢查方法。 在專利文獻1中,揭示有一種將光照射在基板上而檢 測出該基板上之異物、缺陷(針孔)等之異物及缺陷檢查裝 置。異物及缺陷檢查裝置係由以下構件所構成:光源,照 射光轴相對於基板傾斜之入射光;對物鏡,將來自基板之 321097 4 200950630 !=予:聚光;針孔’配置在與基板面之反射點光學性 二=,光學檢測元件,檢測出通過該針孔之反射光; 及使板朝々光轴相對於基板之法線傾斜之方向、亦即X 軸方向移動或使入射光掃描的機構。一邊 射光朝X軸方向移動,一邊使該入射"、 :::元::測r在於基板上之異物或因二射: 反射光以進订異物或缺陷之檢測。 (專利文獻1)日本特開·5.395 © 【發明内容】 ^ (發明所欲解決之課題) 然而’習知之電路基板 杳方法俜由於1,、, 衣以方去中的電路基板之檢 查方法係由於為以目視進行之人為檢查因 遺漏。再者,因檢查對象之細微化、複雜化,而=料 間增加,作業效率降低之問題。 ㈣匕π有作業時 再者’在光學性之圖幸 ❹ 問題’但必須事前登錄良^ :雖可解決前述之 的增加而增加事前處理二而有隨著檢查對象種類 再者,在異物及缺陷檢=問題。 板上一邊移動於基板上,而二、置中,由於係一邊照射基 生的反射光,因此有在不測並辨識因異物或缺陷所產. 法檢測出反射光之問題。反射光之微小針孔之情形時無 再者,由於電路基板、 在組裝電路元件而接合保椒=未被確實地檢測出,因此 路裝置之背面電極侧而附认月曰層時,保護樹脂會流入電 於背面電極,在無法進行銲接 321097 200950630 之情形下以致發生接觸不良。 特別是,伴隨電路元件之微細化,安裝在電路基板之 元件數已大幅地增加,而希望有一種不論檢查對象之電路 基板的大小,皆可在短時間確實地檢查電路基板之良否的 方法。 (解決課題之手段) 本發明係鑑於前述之問題而研創者,其係藉由以下方 法解決前述問題:在電路基板配列多數個電路元件載置區 域,在該電路元件載置區域之周邊形成多數個貫穿孔電極 (through hole electrodes),並以阻劑層(resist layer) 覆蓋前述貫穿孔電極之至少一端,對前述電路基板進行加 壓而測定壓力之變化,並檢測在連接於前述貫穿孔電極的 前述阻劑層是否有剝落、破裂或針孔等缺陷,將電路元件 組裝在前述無缺陷之前述電路基板,附著用以被覆前述電 路元件之保護樹脂層,以防止前述保護樹脂從前述阻劑層 流入至前述貫穿孔電極。 再者,本發明係在測量前述壓力之變化時,夾持前述 電路基板之上表面及下表面而形成氣密室,從前述氣密室 之上側送上加壓之空氣並保持一定時間,以測量前述氣密 室之上側與下側之差壓。 此外,在本發明中,係將從前述氣密室之上侧洩漏至 前述氣密室之下側的漏壓為5Pa以下者判定為良品。 再者,本發明係使用受光元件作為前述電路元件,前 述保護樹脂層係使用透明之環氧樹脂。 6 321097 200950630 (發明之效果) 依據本發明,藉由以阻劑層覆蓋形成於電路基板之電 路元件載置區域之周邊的多數個貫穿孔電極之至少一端, 對電路基板進行加壓而測定壓力之變化 接於貫穿孔電極之阻劑層是否有剝落、破裂或針孔^ -陷。藉此,可在短時間確實地檢查電路基板之有無缺陷, • ^將電路元件僅組裝在無缺陷之電路基板後,附著用以 « 電路元件之賴麟層,目而可防止保騎脂層從阻 巧θ之缺陷流入至貫穿孔電極。 再者,由於就連料之反射檢查針孔之方法都無法檢 要10㈣下之微小針孔都能容易地檢測ώ,且不需 ^性之圖案檢查方法的匹配處理,因而有無須事先登 錄圖案而減少作業之麻煩的優點。 此外,壓力 ⑩ 燹的j疋係夾持電路基板之上表面及 女表面而形減密室,從前述氣密室之上侧送上加壓之空 測量保持一定時間後之氣密室之上側與下側之差 層沾轉此,可瞬間檢查貼附在多數個貫穿孔電極上之阻劑 2陷之有無’因而有能以-次之測量確實地檢查設有 致個電路兀件載置區域的電路基板之良否。 此外,可將從氣密室之上_漏至氣密室之下側的漏 ^為5Pa以下者判定為良品。藉此,就連產生於電路基板 1〇#m以下之微小缺陷也會被確實地檢測出,因此,可 ^先防範在附著用以被覆電路元件之保護樹脂詹的步驟 ’保護樹脂流入至貫穿孔電極内而附著在外部電極所產 321097 7 200950630 生的不良。 再者’在本發明之製造方法中,係可使用受光元件作 為電路7L件’保護樹脂層係可使用透明之環氧樹脂。因此, 於習知之製造方法無法發現針孔等之所有缺陷,且因亦無 法發現在被覆時從缺陷部分流入之透明的環氧樹脂,故無 法使党光7L件之不良達到零,但藉由採用上述之製造方 法,即可製造僅使用良品之電路基板之受光元件,即便利 - 用透光性佳之透明環氧樹脂作為保護樹脂層,亦不會有從 . 缺陷流入之虞,故可僅提供良品之受光元件。 ❹ 【實施方式】 以下’參照第1圖至第5圖說明本發明之實施形態。 首先’第1圖及第2圖係顯示以本發明之製造方法完 成之電路基板。第1圖係其俯視圖,第2圖(A)係表面之局 部放大圖’第2圖(B)係背面之局部放大圖。 本實施形態之電路基板1係由絕緣基板10、導電圖案 13、接合墊14、電路元件載置區域15、貫穿孔電極16、 阻劑層18及保護樹脂層20所構成。 絕緣基板10係為由FR4(環氧化物織玻璃布)、BT(雙 馬來醯亞胺-三氮雜苯,bismaleimide-triazineresin)樹 脂所成之基板、玻璃環氧基板、玻璃聚醯亞胺基板等。就 本實施形態之一例而言,係採用由BT樹脂所成之基板。絕 緣基板10之厚度係例如0. 5随左右。 在絕緣基板10之兩面,以接著劑壓接貼附有第1導電 箔11及第2導電箔12。就第1導電箔11及第2導電箔12 8 321097 200950630 而言,只要是可蝕刻之金屬即可。在本實施形態中,係採 用由銅所構成之金屬箱。該等導電落係構成配線之一部分。 亦即,該等導電箔之厚度係選擇所需之厚度作為配 線。配線之厚度係可依所安裝之電路元件之電流容量等而 任意地決定。第1導電箔11與第2導電箔12之膜厚為同 等,例如在9/zm至35/zm之範圍選擇,在此為18/im。 導電圖案13係將第1導電箔11及第2導電箔12蝕刻 « 形成為預定之形狀,在中央部設置有電路元件載置區域 ® 15,以圍繞該電路元件載置區域15之方式接近各邊而設置 接合墊14,並設置從接合墊14曲折延伸至後述之貫穿孔 電極16的配線路13a。 貫穿孔電極16係在包含以多數個行列狀排列在絕緣 基板10上之電路元件載置區域15的個別電路裝置21之周 邊配置有多數個。該貫穿孔電極16係在絕緣基板10設置 貫穿孔,並對其内面進行貫穿孔鍍覆,而以連接第1導電 Q 箔11及第2導電箔12之方式設置,以構成個別電路裝置 之外部電極。再者,如圖所示,個別電路裝置21係指包含 電路元件載置區域15且由貫穿孔電極16圍繞四周的内側。 " 阻劑層18係以覆蓋貫穿孔電極16上之方式附著,且 具有防止樹脂等流入貫穿孔電極之功能。就阻劑層18而 言,可採用乾式薄膜阻劑。 在電路元件載置區域15上’固定有受光7G件等電路元 件19,且多數個配置在絕緣基板10上之預定位置。 保護樹脂層20係為了保護電路元件19及接合引線而 9 321097 200950630 附著在整體絕緣基板10。再者,保護樹脂層20係採用透 明環氧樹脂等,俾在形成受光元件時可使光通過。 接著,說明安裝基板之圖案。 第1圖所示之電路基板i,具體而言為使用15如軟 100mm之玻璃環氧基板10。在周邊設置有複數個定位孔2, 在内部以行列狀配置有多數個個別電路裝置。 在本實施形態中作為一例,係以13列^〗行之行列狀 配置個別電路裝置21。藉此,在丨個電路基板丨中,可取 得12x13=156個個別電路裝置。再者,貫穿孔電極16係 相對於1個個別電路裝置,縱向排列7個橫向排列8個。 藉此,在1個電路基板1之列方向配置有门個“幻以以列 + 1)=1176個貫穿孔電極16,在丨個電路基板丨之行方向 配置有(8個χ13)χ(12行+ 1)= 1352個貫穿孔電極16,共配 置有全部2528個貫穿孔電極。再者,在第i圖中,係比實 際個數少而簡略圖示。 接著,第2圖(A)係顯示電路基板丨之表面放大圖。各 個別電路裝置21之大小係極微小至例如8mmx6_。鄰接之 各個別電路裝置21係共有貫穿孔電極16。 接合墊14係接近圍繞電路元件载置區域15之各邊, 且形成為比配線路13a更寬幅。 導電圖案13係由接合墊14、及從接合墊14曲折延伸 至貫穿孔電極16的配線路13a所構成。 電路元件載置區域15係對應載置之電路元件19而適 當地設計’例如形成為3. 5mmx3. 5mm。 321097 . 10 200950630 貫穿孔電極16係圍繞包含電路元件載置區域15之個 別電路裝置之周邊而形成。貫穿孔電極16係藉由路由器 (router)等而形成直徑0. 5mm。 阻劑層18係圍繞電路元件載置區域15而貼附在貫穿 孔電極16上。以阻劑層18被覆第1導電箔11及第2導電 箔12,在第1導電箔11進行曝光顯影第2圖(A)所示之圖 案,將剩餘之阻劑層作為遮罩,以進行蝕刻。例如,阻劑 層18之寬度為1. 5mm,厚度為55//m。再者,在曝光顯影 ® 時若細微之塵埃等位於曝光面,則會成為產生針孔之原 因。在10/z m以下之針孔時,由於連光也不會穿透,因此 利用習知之檢查方法無法發現針孔,而漏看出缺陷。 再者,第2圖(B)顯示電路基板1之背面放大圖。使貫 穿孔電極16及連接在貫穿孔電極之成為背面電極的導電 圖案13之一部分殘留,而露出絕緣基板10。 接著,參照第3圖,說明使用本發明之電路基板之製 n造方法的電路基板之檢查方法。 第3圖係顯示進行本發明之電路基板之檢查的檢查機 之剖視圖。 ' 檢查機30係以上侧殼體31及下侧殼體32構成氣密室 33,在兩者之間夾持電路基板1,並以與上側殼體31及下 侧殼體32相對向設置之墊片34保持氣密狀態。在上側殼 體31設置有加壓孔,經加壓之空氣係被供給至氣密室33 之上側。以差壓計35測量氣密室33之上侧與下側之差壓。 在該檢查機30中,將被阻劑層18所覆蓋的電路基板 11 321097 200950630 1之貫穿孔電極16朝向下側,並以檢查機將電路基板1之 終端部予以夹住。在電路基板1上之全部的個別電路裝置 被收納在檢查機30之氣密室33後,從氣密室33之上侧送 入經加壓之空氣,使氣密室33上側的壓力上昇。再者,氣 密室33下侧係由電路基板1所遮蔽,因此不會被加壓,而 以氣密室33之上側及下側來保持預定之氣壓差,並以差壓 計3 5測量該氣壓差。 然而,在連接於貫穿孔電極16的阻劑層18存在有剝 落、破裂或針孔等缺陷時,空氣會從該等缺陷部分洩漏至 〇 氣密室33下側。因此,氣密室33上侧的空氣會通過缺陷 部一下子流入氣密室33之下側,因此氣密室33之上侧與 下側之壓力差會急速減少。藉此,可確實地瞬間檢測出連 光也無法通過之細微缺陷。 具體而言,在氣密室33之上側維持一定時間之加壓狀 態後,以差壓計35測量氣密室33上侧與下側之差壓。差 壓為200pa(帕斯卡)且在30秒鐘茂漏5pa以上時,顯然在 @ 阻劑層18產生有缺陷,因此判定電路基板1為不良,在之 後的步驟中一律不使用。 另一方面,30秒鐘洩漏5pa以下時,判定為在阻劑層 _ 1無缺陷之良品的電路基板1。 接著,參照第4圖及第5圖,說明本發明之電路基板 之製造方法。 本發明之製造方法,係由下述方式所構成:在電路基 板配列多數個電路元件載置區域,在該電路元件載置區域 12 321097 200950630 之周邊形成多數個貫穿孔電極,並以阻劑層覆蓋前述貫穿 孔電極之至少一端,對前述電路基板進行加壓而測定壓力 之變化,並檢測在連接於前述貫穿孔電極的前述阻劑層是 否有剝落、破裂或針孔等缺陷,將前述電路元件組裝在前 述無缺陷之前述電路基板,附著用以被覆前述電路元件之 保護樹脂層,以防止前述保護樹脂從前述阻劑層流入至前 述貫穿孔電極。 本發明之第1步驟係如第4圖(A)所示,準備在兩面貼 ® 著有銅等第1導電箔11及第2導電箔12的絕緣基板10。 就絕緣基板10而言,係以採用玻璃環氧基板或玻璃聚 醯亞胺基板為佳,但依情況亦可採用氟基板、玻璃ΡΡ0基 板或陶莞基板等。此外,亦可為可撓薄片、薄膜等。在本 實施形態中,係採用厚度0. 5mm之玻璃環氧基板。 就第1導電箔11及第2導電箔12而言,只要是可蝕 刻之金屬即可。在本實施形態中,係採用由銅所構成之金 U屬箔,該等金屬箔係構成配線之一部分。亦即,配線之厚 度係可由安裝之電路元件之電流容量等而任意決定。第1 導電箔11及第2導電箔12之膜厚為同等,例如為18//m 左右。 本發明之第2步驟如第4圖(B)所示,將用以貫穿絕緣 基板及導電箔之貫穿孔形成在預定位置。 在本步驟中,用以形成貫穿孔電極16之貫穿孔16a係 使用NC工作機並以鑽孔機等貫穿第1導電箔11、第2導 電箔12及絕緣基板10而開孔。貫穿孔16a係在第2圖(A) 13 321097 200950630 路70件載置區域15之個別電路裝置周邊配 ::例如,貫穿孔之直徑係形成為〇· 5丽。 在列方向配置有1176個,在行方向配置有 ^ 2528個貫穿孔電極16係形成在i個電路 扳1。 極,= : 3步驟係如第4圖(C)所示,形成貫穿孔電 極該貫穿孔電極係藉由貫穿孔鑛覆將貫穿孔予以電性連 接。 在本步財,將整體料在把溶液,[Technical Field] The present invention relates to a method of manufacturing a circuit board, and more particularly to providing a plurality of circuit component mounting regions on a circuit board, and forming a majority around each circuit component mounting region a through-hole electrode, which covers one end of the through-hole electrode with a resist layer, pressurizes the circuit board to measure a pressure change, and checks whether there is a pinhole or the like in the resist layer connected to the through-hole electrode, and then protects the resin A method of manufacturing a circuit board on which a layer is attached to a circuit board. [Prior Art] In recent years, the manufacturing method of the circuit board is mainly based on a material-saving manufacturing method, in which a plurality of circuit elements such as semiconductor elements are closely assembled and assembled in a protective resin. After molding, cutting is performed to divide. The method of inspecting the circuit board is generally performed by a visual inspection method, and a method of detecting a defect such as a pinhole or a burr on a substrate by visually observing the pattern shape of the substrate through a magnifying glass; or A method in which a light source is irradiated onto the entire substrate and the defect is detected by whether or not there is light leaking from a defective portion such as a pinhole or a burr. — Furthermore, there is also an optical pattern inspection method that checks the presence or absence of defects on one side while matching the pre-registered pattern. Patent Document 1 discloses a foreign matter and a defect inspection device that detect light, foreign matter, defects (pinholes), and the like on the substrate by irradiating light onto the substrate. The foreign matter and defect inspection device is composed of a light source that illuminates the incident light oblique to the substrate with respect to the substrate; and for the objective lens, the 321097 4 200950630 from the substrate: concentrating; the pinhole 'disposed on the substrate surface The optical point of the reflection point is two, the optical detecting element detects the reflected light passing through the pinhole; and moves the plate toward the direction in which the pupil axis is inclined with respect to the normal line of the substrate, that is, in the X-axis direction or scans the incident light. Agency. While the light is moving in the X-axis direction, the incident " ::::: is measured by foreign matter on the substrate or by the reflected light to reflect foreign matter or defects. (Patent Document 1) Japanese Patent Laid-Open No. 5.395 © [Summary of the Invention] ^ (Problems to be Solved by the Invention) However, the conventional circuit board method is a method for checking the circuit board in the case of clothing. Due to omissions for visual inspections by humans. Further, due to the miniaturization and complication of the inspection object, the problem arises that the material is increased and the work efficiency is lowered. (4) When there is work in 匕 π, 'there is a problem in the optical map', but it must be registered beforehand. ^: Although it can solve the above increase, it increases the pre-treatment 2 and the type of the object to be inspected, in the foreign object and Defect check = problem. The board moves on the substrate while the center is placed, and since the fundamental reflected light is irradiated, the problem of detecting the reflected light by the foreign matter or the defect is detected. In the case of a small pinhole that reflects light, there is no such thing as a circuit board or a circuit board that is assembled and a device is not reliably detected. Therefore, when the rear side electrode side of the path device is attached to the moon layer, the resin is protected. It will flow into the back electrode, and in the case where welding 321097 200950630 is impossible, contact failure occurs. In particular, with the miniaturization of the circuit elements, the number of components mounted on the circuit board has been greatly increased, and a method of reliably checking the reliability of the circuit board in a short time regardless of the size of the circuit board to be inspected is desired. MEANS FOR SOLVING THE PROBLEMS The present invention has been made in view of the above problems, and the above problems are solved by arranging a plurality of circuit component mounting regions on a circuit board and forming a plurality of peripheral portions of the circuit component mounting regions. a through hole electrode, and covering at least one end of the through hole electrode with a resist layer, pressurizing the circuit substrate to measure a change in pressure, and detecting a connection to the through hole electrode Whether the resist layer has defects such as peeling, cracking or pinholes, and the circuit component is assembled on the aforementioned circuit substrate without defects, and a protective resin layer for covering the circuit component is attached to prevent the protective resin from the resist The layer flows into the aforementioned through hole electrode. Furthermore, in the present invention, when measuring the change in the pressure, the upper surface and the lower surface of the circuit board are sandwiched to form an airtight chamber, and pressurized air is supplied from the upper side of the airtight chamber for a certain period of time to measure the foregoing. The differential pressure between the upper side and the lower side of the airtight chamber. Further, in the present invention, it is determined that the leakage pressure from the upper side of the airtight chamber to the lower side of the airtight chamber is 5 Pa or less. Further, in the present invention, a light-receiving element is used as the circuit element, and a transparent epoxy resin is used as the protective resin layer. 6 321097 200950630 (Effects of the Invention) According to the present invention, at least one end of a plurality of through-hole electrodes formed around the circuit element mounting region of the circuit board is covered with a resist layer, and the circuit board is pressurized to measure the pressure. The change is connected to the resist layer of the through-hole electrode for peeling, cracking or pinhole collapse. Thereby, it is possible to reliably check the presence or absence of defects of the circuit substrate in a short time. • The circuit component is assembled only on the circuit substrate without defects, and the lining layer for the circuit component is attached, thereby preventing the grease layer from being protected. From the defect of the resistance θ, it flows into the through-hole electrode. Furthermore, since the method of inspecting the pinhole by the reflection of the continuous material cannot be detected, the micro pinhole under the 10 (four) can easily detect the flaw, and the matching of the pattern inspection method is not required, so that it is necessary to register the pattern in advance. And the advantage of reducing the trouble of the work. In addition, a pressure of 10 燹 is used to clamp the upper surface of the circuit board and the female surface to form a reduced chamber, and the upper side and the lower side of the airtight chamber are measured after being pressurized for a certain period of time from the upper side of the airtight chamber. When the difference layer is touched, the resistance of the resist 2 attached to the plurality of through-hole electrodes can be instantly checked. Thus, it is possible to reliably check the circuit substrate having the mounting area of the circuit element by the measurement of the second time. Good or not. Further, it can be judged that the leak from the upper side of the airtight chamber to the lower side of the airtight chamber is 5 Pa or less. As a result, even the minute defects generated on the circuit board 1 〇 #m or less are reliably detected. Therefore, the step of protecting the resin from flowing to the circuit component for covering the circuit component can be prevented. The hole electrode is attached to the external electrode and the defect produced by the 321097 7 200950630. Further, in the manufacturing method of the present invention, a light-receiving element can be used as the circuit 7L. The protective resin layer can be made of a transparent epoxy resin. Therefore, in the conventional manufacturing method, all defects such as pinholes and the like cannot be found, and since the transparent epoxy resin flowing from the defective portion at the time of coating cannot be found, the defect of the party light 7L cannot be made zero, but by According to the above-described manufacturing method, it is possible to manufacture a light-receiving element of a circuit board using only a good product, that is, it is convenient to use a transparent epoxy resin having good light transmittance as a protective resin layer, and there is no inflow of defects. Provide good light receiving components. [Embodiment] Hereinafter, embodiments of the present invention will be described with reference to Figs. 1 to 5 . First, the first and second drawings show a circuit board which is completed by the manufacturing method of the present invention. Fig. 1 is a plan view, and Fig. 2(A) is an enlarged view of a portion of the surface. Fig. 2(B) is a partially enlarged view of the back surface. The circuit board 1 of the present embodiment is composed of an insulating substrate 10, a conductive pattern 13, a bonding pad 14, a circuit element mounting region 15, a through hole electrode 16, a resist layer 18, and a protective resin layer 20. The insulating substrate 10 is a substrate made of FR4 (epoxy woven glass cloth), BT (bismaleimide-triazine resin) resin, a glass epoxy substrate, and a glass polyimide. Substrate, etc. In an embodiment of the present embodiment, a substrate made of a BT resin is used. 5左右左右左右。 The thickness of the insulating substrate 10 is, for example, 0.5. The first conductive foil 11 and the second conductive foil 12 are attached to the both surfaces of the insulating substrate 10 by pressure bonding. The first conductive foil 11 and the second conductive foil 12 8 321097 200950630 may be any metal that can be etched. In the present embodiment, a metal case made of copper is used. These conductive drops form part of the wiring. That is, the thickness of the conductive foils is selected as the wiring thickness. The thickness of the wiring can be arbitrarily determined depending on the current capacity of the circuit component to be mounted or the like. The film thickness of the first conductive foil 11 and the second conductive foil 12 is the same, for example, in the range of 9/zm to 35/zm, which is 18/im. The conductive pattern 13 is formed by etching the first conductive foil 11 and the second conductive foil 12 into a predetermined shape, and the circuit component mounting region ® 15 is provided at the center portion so as to be close to each other around the circuit component mounting region 15 The bonding pad 14 is provided on the side, and a wiring 13a extending from the bonding pad 14 to the through-hole electrode 16 to be described later is provided. The through hole electrodes 16 are arranged in a plurality of ways around the individual circuit devices 21 including the circuit element mounting regions 15 arranged in a plurality of rows and columns on the insulating substrate 10. The through-hole electrode 16 is provided with a through hole in the insulating substrate 10, and is plated through the inner surface of the insulating substrate 10, and is provided to connect the first conductive Q foil 11 and the second conductive foil 12 to form an external portion of the individual circuit device. electrode. Further, as shown in the figure, the individual circuit device 21 is referred to as an inner side including the circuit component mounting region 15 and surrounded by the through hole electrode 16. < The resist layer 18 is attached so as to cover the through-hole electrode 16, and has a function of preventing resin or the like from flowing into the through-hole electrode. As the resist layer 18, a dry film resist can be used. Circuit elements 19 such as light-receiving elements 7G are fixed to the circuit element mounting region 15 and are disposed at predetermined positions on the insulating substrate 10. The protective resin layer 20 is adhered to the entire insulating substrate 10 in order to protect the circuit component 19 and the bonding wires 9 321097 200950630. Further, the protective resin layer 20 is made of a transparent epoxy resin or the like, and allows light to pass therethrough when the light receiving element is formed. Next, the pattern of the mounting substrate will be described. The circuit board i shown in Fig. 1 specifically uses a glass epoxy substrate 10 such as a soft 100 mm. A plurality of positioning holes 2 are provided in the periphery, and a plurality of individual circuit devices are arranged in a matrix. In the present embodiment, as an example, the individual circuit devices 21 are arranged in a matrix of 13 columns. Thereby, 12 x 13 = 156 individual circuit devices can be obtained in one circuit board. Further, the through-hole electrodes 16 are arranged in a horizontal direction and arranged in eight horizontal directions with respect to one individual circuit device. Thereby, in the column direction of one circuit board 1, a gate "intelligent column + 1" = 1176 through-hole electrodes 16 are arranged, and (8 χ 13) 配置 are arranged in the row direction of one circuit board χ ( 12 rows + 1) = 1352 through-hole electrodes 16, all of which are arranged with 2,528 through-hole electrodes. In addition, in the figure i, it is less than the actual number and is simply illustrated. Next, Figure 2 (A) The surface of the circuit board 丨 is shown in an enlarged view. The size of each of the circuit devices 21 is extremely small, for example, 8 mm x 6 _. The adjacent circuit devices 21 share the through hole electrodes 16. The bonding pads 14 are close to the surrounding circuit component mounting regions. Each of the sides 15 is formed to be wider than the distribution line 13a. The conductive pattern 13 is composed of a bonding pad 14 and a wiring line 13a that is bent from the bonding pad 14 to the through-hole electrode 16. The circuit component mounting region 15 The through-hole electrode 16 is formed around the periphery of the individual circuit device including the circuit component mounting region 15 by appropriately designing, for example, 3. 5 mm x 3. 5 mm. 321097 . 10 200950630. Electrode 16 is connected by router (router) The resist layer 18 is attached to the through-hole electrode 16 around the circuit component mounting region 15. The first conductive foil 11 and the second conductive foil 12 are covered with the resist layer 18, 5毫米的厚度为55/ The thickness of the resist layer 18 is 1. 5mm, the thickness is 55 / / / / / / / / / / / / / / / / / / / / / / / / / / / / /m. In addition, if fine dust or the like is placed on the exposure surface during Exposure Developer®, it may cause pinholes. When the pinhole is 10/zm or less, it will not penetrate because of the light. In the conventional inspection method, the pinhole is not found, and the defect is seen. Further, Fig. 2(B) shows an enlarged view of the back surface of the circuit board 1. The through hole electrode 16 and the conductive electrode connected to the through hole electrode are used as the back surface electrode. One of the patterns 13 remains and the insulating substrate 10 is exposed. Next, a method of inspecting a circuit board using the method for fabricating the circuit board of the present invention will be described with reference to Fig. 3. Fig. 3 is a view showing a circuit board on which the present invention is applied. A cross-sectional view of the inspection machine. 'Check machine 30 The upper case 31 and the lower case 32 constitute an airtight chamber 33, and the circuit board 1 is sandwiched between the two, and is kept airtight by a spacer 34 provided to face the upper case 31 and the lower case 32. The upper casing 31 is provided with a pressurizing hole, and the pressurized air is supplied to the upper side of the airtight chamber 33. The differential pressure between the upper side and the lower side of the airtight chamber 33 is measured by a differential pressure meter 35. In the machine 30, the through-hole electrode 16 of the circuit board 11 321097 200950630 1 covered by the resist layer 18 is directed downward, and the end portion of the circuit board 1 is sandwiched by an inspection machine. After all the individual circuit devices on the circuit board 1 are housed in the airtight chamber 33 of the inspection machine 30, the pressurized air is supplied from the upper side of the airtight chamber 33, and the pressure on the upper side of the airtight chamber 33 is increased. Further, since the lower side of the airtight chamber 33 is shielded by the circuit board 1, the predetermined air pressure difference is maintained by the upper side and the lower side of the airtight chamber 33 without being pressurized, and the air pressure is measured by a differential pressure meter 35. difference. However, when the resist layer 18 connected to the through-hole electrode 16 has defects such as peeling, cracking or pinholes, air leaks from the defective portions to the lower side of the hermetic chamber 33. Therefore, the air on the upper side of the airtight chamber 33 flows into the lower side of the airtight chamber 33 through the defective portion at a time, so that the pressure difference between the upper side and the lower side of the airtight chamber 33 is rapidly reduced. Thereby, it is possible to reliably detect minute defects that the continuous light cannot pass. Specifically, after the upper side of the airtight chamber 33 is maintained in a pressurized state for a predetermined period of time, the differential pressure between the upper side and the lower side of the airtight chamber 33 is measured by a differential pressure meter 35. When the differential pressure is 200 Pa (Pascal) and the leakage is 5 Pa or more in 30 seconds, it is apparent that the resist layer 18 is defective, so that the circuit substrate 1 is judged to be defective, and it is not used in the subsequent steps. On the other hand, when leaking 5 Pa or less in 30 seconds, it was judged that the resist layer _1 was not defective in the circuit board 1. Next, a method of manufacturing the circuit board of the present invention will be described with reference to Figs. 4 and 5. The manufacturing method of the present invention is configured such that a plurality of circuit component mounting regions are arranged on a circuit board, and a plurality of through-hole electrodes are formed around the circuit component mounting region 12 321097 200950630, and a resist layer is provided. Covering at least one end of the through-hole electrode, pressurizing the circuit board to measure a change in pressure, and detecting whether the resist layer connected to the through-hole electrode has defects such as peeling, cracking, or pinhole, and the circuit The element is assembled on the circuit board having no defects described above, and a protective resin layer for covering the circuit element is attached to prevent the protective resin from flowing from the resist layer to the through-hole electrode. In the first step of the present invention, as shown in Fig. 4(A), the insulating substrate 10 on which the first conductive foil 11 and the second conductive foil 12 such as copper are adhered is prepared. The insulating substrate 10 is preferably a glass epoxy substrate or a glass polyimide substrate, but a fluorine substrate, a glass substrate or a ceramic substrate may be used depending on the case. Further, it may be a flexible sheet, a film or the like. 5毫米玻璃玻璃基板板。 In this embodiment, a thickness of 0. 5mm glass epoxy substrate. The first conductive foil 11 and the second conductive foil 12 may be any metal that can be etched. In the present embodiment, a metal U-based foil made of copper is used, and these metal foils constitute a part of the wiring. That is, the thickness of the wiring can be arbitrarily determined by the current capacity of the mounted circuit component or the like. The film thicknesses of the first conductive foil 11 and the second conductive foil 12 are equivalent, and are, for example, about 18/m. In the second step of the present invention, as shown in Fig. 4(B), a through hole for penetrating the insulating substrate and the conductive foil is formed at a predetermined position. In this step, the through hole 16a for forming the through hole electrode 16 is opened by using an NC working machine and passing through the first conductive foil 11, the second conductive foil 12, and the insulating substrate 10 with a drill or the like. The through hole 16a is provided in the vicinity of the individual circuit device of the 70-piece mounting area 15 in Fig. 2 (A) 13 321097 200950630. For example, the diameter of the through hole is formed as 〇·5 丽. 1176 are arranged in the column direction, and ^ 2528 through-hole electrodes 16 are arranged in the row direction to form i circuit boards 1. The poles, =: 3 steps are as shown in Fig. 4(C), and the through-hole electrodes are formed. The through-hole electrodes are electrically connected to the through-holes through the through-holes. In this step, the whole material is put in the solution,

及第2導電箔12作為雷搞,斑—命 守电泊U 霜蔣約1…e 藉 無電解鍍覆或電解鍍 &quot; 15/Zm之膜厚的貫穿孔電極16形成在貫穿孔 16a之内壁。 〜乂牡貝芽孔 及第trc驟係如第4圖(D)所示’對第1導電箱 ”v白進订細J,而形成多數個用以載置各電路元 件之電路元件載置區域。 在本步驟中’以阻劑層(未圖示)被覆絕緣基板2之第 ^導電泊11及第2導電羯12,使第2圖(A)及⑻所示之圖 二曝光&quot;4,y,將剩餘之阻劑層作為遮罩,以進行第1導電 Π?導電泊12之钱刻。藉此,以行列狀形成多數 載置各電路元件之電路元件載置區域。第1導電箔 第2導f们2為銅時,係採用氯化鐵作核刻溶液。 接著,進行阻劑層之剝離去除。針對各單元之圖案形狀, 已參照第2圖(A)及⑻進行說明過,因此在此省略其說明。 本發明之第5步驟係如第4圖⑻所示,藉由錢覆將可 321097 14 200950630 接合之導電性金屬層附著在貫穿孔電極、導電圖案及接合 墊之表面。 本步驟係將導電性金屬層17積層在電性連接之第1導 電箔11、第2導電箔12及貫穿孔電極16上。亦即,藉由 電解鍍覆將可接合之導電性金屬層17附著在導電圖案13 及接合墊14。導電性金屬層17係可選擇金或鎳之任一者。 為金鍍覆時,係設置0. 5/im至1 之金鍍覆層,於鎳鍍 * 覆時,係設置5//m至15/zm之錄鑛覆層,而作成可進行接 ® 合引線之接合。此外,在進行放熱時,亦可藉由電解鍍覆 使導電性金屬層17附著在電路元件載置區域15之表面。 本發明之第6步驟係如第4圖(F)所示,以阻劑層覆蓋 貫穿孔電極之一端。 在本步驟中,使阻劑層18貼附於貫穿孔電極16之一 端。阻劑層18係用以防止保護樹脂流入貫穿孔電極16者, 只要比貫穿孔電極16之開口寬度更寬廣即可。在本實施形 q 態中,阻劑層18係採用乾式薄膜阻劑。具體而言,阻劑層 18之寬度係1. 5mm,厚度為5 5 /z m。 再者,在本步驟後,使用第3圖所示之檢查機30,進 &quot; 行在電路基板1之連接於貫穿孔電極16之阻劑層18是否 有針孔等缺陷的檢查。 具體而言,在電路基板1形成有全部2528個之貫穿孔 電極16。以阻劑層18被覆第1導電箔及第2導電箔,並 利用曝光顯影而形成圖案。在曝光顯影時有塵埃等時,會 成為在阻劑層形成10#m以下之針孔的原因。10//m以下 15 321097 200950630 之針孔雖不會使光通過,但依據本步驟之檢查機30,可瞬 間檢查2000個以上之檢查對象,就連10 gm以下之針孔亦 可確實地檢測出。針對檢查方法,已參照第3圖進行說明 過,因此在此省略其說明。 本發明之第7步驟係如第5圖(A)所示,在各個別電路 裝置之電路元件載置區域上固著有電路元件。 在本步驟中,以絕緣性之環氧樹脂等接著劑將電路元 件19之晶片固著在電路元件載置區域15。在電路元件19 之上表面具有陽極及陰極電極,且固著有底面。電路元件 19之固著係使用晶片座。 本發明之第8步驟係如第5圖(A)所示,藉由接合引線 之接合來連接電路元件19之電極與接合墊14。 在本步驟中,係使用金之接合引線並以接合機一邊圖 案辨識電極之位置,一邊藉由超音波熱壓接,連接電路元 件19之電極、與以貫穿孔電極16及導電圖案13所連接之 接合墊14上的導電性金屬層。 本發明之第9步驟係如第5圖(B)所示,以保護樹脂層 20被覆電路元件19及接合引線。 本步驟中,係藉由灌注(pott ing)方式以保護樹月旨層 20被覆電路元件19及接合引線,以保護其不受外部空氣 破壞,且在發光元件之情形時,亦可發揮作為導出光之凸 透鏡的作用0在本實施形態中,係採用透明環氧樹脂作為 保護樹脂層2 0。 在本步驟中,經灌注之液狀的保護樹脂層20係以阻劑 16 321097 200950630 亦可完全地防止其從電 16。結果,貫穿孔電極 因此可維持在可銲接之 層18阻止其流入貫穿孔電極ι6, 路基板1之背面繞入各貫穿孔電極 16皆未附著透明的保護樹脂層 狀態。 圖本發明之第10步驟係對貫穿孔電極16上進行切割(未 圖示),依各個別電路裝置21進行個別分巧。 ❹ 列狀==基上進蝴,將以行 個別地完成之個別電路裝置21。分裝貫置穿二:f6 係作為各個外部電極。 穿電極16 著在U步驟係以銲心式將個別電路裳置接 者在印刷基板上的導電圖案。 在本步驟中,個別電路裝置91 Λ 邻雷搞,/㈣w 2之貫穿孔電極16為外 口Ρ電極’在載置於印刷基板23上 料22進行連接。 〈導電㈣24後,以銲 在本步驟中,在貫穿孔電極16 保護樹脂層2_著,_進行;^麟物之 【圖式簡單說明】 第1圖係以本發明之製造方法完成之電路基板的俯視 圃。 第2 ®仙本發日狀製造方法完成之電路基板之⑴ 表面放大圖,(Β)背面放大圖。 第3圖係說明本發明之製造方法的剖視圖。 第4圖(Α)至〇τ)係用以說明本發明之製造方法的剖視 321097 17 200950630 圖。 第5圖(A)至(C)係用以說明本發明之製造方法的剖視 圖。 【主要元件符號說明】 1 電路基板 2 對位孔 10 絕緣基板 11 第1導電箔 12 第2導電箔 13、 24導電圖案 13a 配線路 14 接合墊 15 電路元件載置區域 16 貫穿孔電極 16a 貫穿孔 17 導電性金屬層 18 阻劑層 19 電路元件 20 保護樹脂層 21 個別電路裝置 22 銲料 23 印刷基板 30 檢查機 31 上側殼體 32 下側殼體 33 氣密室 34 墊片 35 差壓計 18 321097And the second conductive foil 12 is used as a lightning strike, and the through-hole electrode 16 having a film thickness of 15/Zm is formed in the through hole 16a by the electroless plating or electrolytic plating. Inner wall. ~ 乂 贝 芽 及 及 第 第 第 第 第 第 第 第 第 第 第 第 第 第 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如In this step, the first conductive layer 11 and the second conductive layer 12 of the insulating substrate 2 are covered with a resist layer (not shown), and the second graph shown in Figs. 2(A) and (8) is exposed. 4, y, the remaining resist layer is used as a mask to perform the first conductive conductive layer 12, thereby forming a plurality of circuit element mounting regions on which the circuit elements are placed in a matrix. When the second lead of the conductive foil 2 is copper, ferric chloride is used as the core engraving solution. Next, the resist layer is removed and removed. The pattern shape of each unit is described with reference to Figs. 2(A) and (8). Although the description has been omitted here, the fifth step of the present invention is as shown in Fig. 4 (8), in which the conductive metal layer joined by the 321097 14 200950630 is adhered to the through-hole electrode, the conductive pattern, and the bonding. The surface of the pad. In this step, the conductive metal layer 17 is laminated on the first conductive foil 11 and the second conductive foil 12 which are electrically connected. The conductive metal layer 17 is adhered to the conductive pattern 13 and the bonding pad 14 by electrolytic plating. The conductive metal layer 17 may be either gold or nickel. For plating, a gold plating layer of 0.5/mm to 1 is provided, and when nickel plating is applied, a recording coating of 5//m to 15/zm is provided, and the wiring can be made. Further, when the heat is radiated, the conductive metal layer 17 may be adhered to the surface of the circuit component mounting region 15 by electrolytic plating. The sixth step of the present invention is as shown in Fig. 4(F). In this step, the resist layer 18 is attached to one end of the through-hole electrode 16. The resist layer 18 is used to prevent the protective resin from flowing into the through-hole electrode 16, as long as The thickness of the resist layer 18 is 1. 5mm, the thickness is 5, and the thickness of the resist layer 18 is 1. 5mm, the thickness is 5, the thickness of the resist layer 18 is 1. 5mm, the thickness is 5 5 /zm. Further, after this step, using the inspection machine 30 shown in Fig. 3, the line is connected to the circuit board 1. Whether or not the resist layer 18 connected to the through-hole electrode 16 has defects such as pinholes. Specifically, all of the 2,528 through-hole electrodes 16 are formed on the circuit board 1. The resist layer 18 is coated with the first conductive foil and The second conductive foil is patterned by exposure and development. When there is dust or the like during exposure and development, pinholes of 10 #m or less are formed in the resist layer. Pinholes of 15 321097 200950630 below 10//m Although the light is not passed, according to the inspection machine 30 of this step, it is possible to instantly inspect 2000 or more inspection objects, and even pinholes of 10 gm or less can be reliably detected. The inspection method has been described with reference to Fig. 3, and therefore the description thereof is omitted here. In the seventh step of the present invention, as shown in Fig. 5(A), circuit elements are fixed to the circuit element mounting regions of the respective circuit devices. In this step, the wafer of the circuit element 19 is fixed to the circuit component mounting region 15 with an adhesive such as an insulating epoxy resin. An anode and a cathode electrode are provided on the upper surface of the circuit component 19, and a bottom surface is fixed. The fixing of the circuit component 19 uses a wafer holder. In the eighth step of the present invention, as shown in Fig. 5(A), the electrodes of the circuit component 19 and the bonding pads 14 are joined by bonding of bonding wires. In this step, the gold bonding wire is used and the position of the electrode is recognized by the bonding machine side pattern, and the electrode of the circuit component 19 is connected to the through hole electrode 16 and the conductive pattern 13 by ultrasonic thermocompression bonding. A conductive metal layer on the bond pad 14. In the ninth step of the present invention, as shown in Fig. 5(B), the circuit element 19 and the bonding leads are covered with the protective resin layer 20. In this step, the circuit element 19 and the bonding leads are covered by the potting layer 20 to protect them from external air damage, and in the case of the light-emitting element, it can also be used as an export. In the present embodiment, a transparent epoxy resin is used as the protective resin layer 20 in the present embodiment. In this step, the perfused liquid protective resin layer 20 is also completely prevented from being electrically discharged by the resist 16 321097 200950630. As a result, the through-hole electrode can be maintained in the solderable layer 18 to prevent it from flowing into the through-hole electrode ι6, and the back surface of the substrate 1 is wound around each of the through-hole electrodes 16 without adhering to the transparent protective resin layer. In the tenth step of the present invention, the through-hole electrodes 16 are cut (not shown), and are individually divided by the respective circuit devices 21. ❹ List == The base is turned on, and the individual circuit devices 21 will be individually completed in rows. Dispense and wear through two: f6 is used as each external electrode. The through electrode 16 is in the U step to electrically connect the individual circuits to the conductive pattern on the printed substrate. In this step, the individual circuit devices 91 are adjacent to each other, and the through-hole electrodes 16 of /(iv)w 2 are external electrodes, and the electrodes 22 are placed on the printed substrate 23 for connection. <Electrical (4) 24, after soldering in this step, the resin layer 2 is protected at the through-hole electrode 16, and the _ is performed; [The simple description of the figure] The first figure is the circuit completed by the manufacturing method of the present invention. The top view of the substrate. (1) Surface enlarged view of the circuit board completed by the 2nd centrifugation method, (Β) enlarged view of the back side. Fig. 3 is a cross-sectional view showing the manufacturing method of the present invention. 4 (Α) to 〇τ) are sectional views for explaining the manufacturing method of the present invention 321097 17 200950630. Fig. 5 (A) to (C) are cross-sectional views for explaining the manufacturing method of the present invention. [Description of main components] 1 circuit board 2 registration hole 10 insulating substrate 11 first conductive foil 12 second conductive foil 13, 24 conductive pattern 13a wiring 14 bonding pad 15 circuit component mounting region 16 through hole electrode 16a through hole 17 Conductive metal layer 18 Resistive layer 19 Circuit element 20 Protective resin layer 21 Individual circuit device 22 Solder 23 Printed substrate 30 Inspection machine 31 Upper side case 32 Lower side case 33 Airtight chamber 34 Gasket 35 Differential pressure gauge 18 321097

Claims (1)

200950630 七、申請專利範圍: 1. 一種電路基板之製造方法,係在電路基板配列多數個電 路元件載置區域’在該電路兀件載置區域之周邊形成多 數個貫穿孔電極, 並以阻劑層覆蓋前述貫穿孔電極之至少一端, 對前述電路基板進行加壓而測定壓力之變化,並檢 測在連接於前述貫穿孔電極的前述阻劑層是否有剥 落、破裂或針孔等缺陷, ® 將前述電路元件組裝在前述無缺陷之前述電路基 板,附著用以被覆前述電路元件之保護樹脂層,以防止 前述保護樹脂從前述阻劑層流入至前述貫穿孔電極。 2. 如申請專利範圍第1項之電路基板之製造方法,其中, 在測量前述壓力之變化時,夾持前述電路基板之上表面 及下表面而形成氣密室,從前述氣密室之上側送入加壓 過之空氣並保持一定時間,以測量前述氣密室之上側與 Q 下侧之差壓。 3. 如申請專利範圍第2項之電路基板之製造方法,其中, 係將從前述氣密室之上側洩漏至前述氣密室之下側的 ' 漏壓為5Pa以下者判定為良品。 4. 如申請專利範圍第1項之電路基板之製造方法,其中, 係使用受光元件作為前述電路元件,前述保護樹脂層係 使用透明之環氧樹脂。 19 321097200950630 VII. Patent application scope: 1. A method for manufacturing a circuit board, wherein a plurality of circuit component mounting regions are arranged on a circuit substrate, and a plurality of through-hole electrodes are formed around the circuit component mounting region, and a resist is used. The layer covers at least one end of the through-hole electrode, pressurizes the circuit board to measure a change in pressure, and detects whether the resist layer connected to the through-hole electrode has defects such as peeling, cracking, or pinholes. The circuit element is assembled on the circuit board having no defects described above, and a protective resin layer for covering the circuit element is attached to prevent the protective resin from flowing from the resist layer to the through-hole electrode. 2. The method of manufacturing a circuit board according to claim 1, wherein when the change in the pressure is measured, the upper surface and the lower surface of the circuit board are sandwiched to form an airtight chamber, and the airtight chamber is fed from the upper side of the airtight chamber. The pressurized air is held for a certain period of time to measure the differential pressure between the upper side of the airtight chamber and the lower side of the Q. 3. The method of manufacturing a circuit board according to the second aspect of the invention, wherein the leakage pressure from the upper side of the airtight chamber to the lower side of the airtight chamber is determined to be 5 Pa or less. 4. The method of manufacturing a circuit board according to claim 1, wherein a light-receiving element is used as the circuit element, and a transparent epoxy resin is used as the protective resin layer. 19 321097
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TWI395534B (en) 2013-05-01
JP2009283546A (en) 2009-12-03
CN101587843A (en) 2009-11-25
KR20090121193A (en) 2009-11-25
JP4567073B2 (en) 2010-10-20

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