KR20220136533A - Printed circuit board structure, and methods of manufacturing the same - Google Patents

Abstract

A printed circuit board according to an embodiment comprises: a test support substrate which includes a test hole; and a circuit structure substrate which is disposed on the test support substrate, and which includes at least one circuit pattern as a path of an electrical signal, and an insulating layer disposed to insulate between the circuit patterns and to expose a portion of the circuit pattern. The test hole is disposed in the test support substrate, and is configured to expose a portion of the circuit pattern by passing through the test support substrate so that the probe of a probe test device can be connected to the circuit pattern.

Description

A printed circuit board structure, a method for manufacturing a printed circuit board using the same, and a method for manufacturing a package {Printed circuit board structure, and methods of manufacturing the same}

The present application relates to a thin printed circuit board (PCB) structure capable of electrically inspecting circuit patterns, a method of manufacturing a printed circuit board using the same, and a method of manufacturing a package.

In general, a printed circuit board (PCB) is a basic component used in electronic communication devices, etc., and in accordance with the recent trend of miniaturization, thin plate, high density, packaging, and light, thin and compact, a plurality of circuit layers are formed in multi-layered electronic products. , micro-patterning, miniaturization, and packaging in which circuit patterns are refined are progressing at the same time. Due to this trend, the demand for a thin printed circuit board is increasing, but its implementation is difficult due to the limitations of materials and equipment. In addition, even after the thin printed circuit board is manufactured, there is a demand for an effective electrical test method due to its thin thickness.

An object of the present invention is to provide a printed circuit board (PCB) structure capable of electrical inspection, a method of manufacturing a printed circuit board using the same, and a method of manufacturing a package.

A printed circuit board structure according to an aspect of the present application includes a test support substrate including a test hole; and a circuit structure substrate disposed on the test support substrate and including at least one circuit pattern as a passage for an electrical signal and an insulating layer disposed to insulate between the circuit patterns and to expose a portion of the circuit pattern do. The test hole may be disposed in the test support substrate, and may be configured to penetrate through the test support substrate to expose a portion of the circuit pattern so that a probe of a test apparatus can contact the circuit pattern.

In one embodiment, the test support substrate includes a core insulating layer; a copper layer disposed on an upper surface and a lower surface of the core insulating layer, respectively; and a through hole serving as the test hole penetrating the core insulating layer and the copper layer.

In one embodiment, the test support substrate comprises a prepreg; a copper clad laminate (CCL) in which copper foil is attached to both surfaces of the prepreg (PRG); and a through hole serving as the test hole penetrating the prepreg and the copper clad laminate.

In an embodiment, an adhesive layer disposed between the carrier substrate and the circuit pattern structure may be further included.

A method of manufacturing a printed circuit board according to another aspect of the present application is a circuit structure board comprising at least one layer of a circuit pattern and at least one insulating layer formed to insulate between the circuit patterns and to expose a part of the circuit pattern to prepare; bonding a test support substrate to one surface of the circuit structure substrate; forming a rest hole penetrating the test support substrate and exposing a portion of the circuit pattern; and contacting a probe of a probe test apparatus to the exposed circuit pattern through the test hole, and performing a probe test to perform an electrical test on the circuit structure board.

In one embodiment, preparing the circuit structure substrate comprises: preparing a base substrate; At least one layer of circuit patterns on the upper and lower surfaces of the base substrate by forming a circuit pattern on the upper and lower surfaces of the base substrate and forming an insulating layer exposing a part of the circuit pattern at least once, forming an insulating layer exposing a portion of the circuit pattern while insulating between the circuit patterns; and forming a solder resist film to expose a portion of the circuit pattern, wherein the base substrate may be removed after bonding the test support substrate.

In an embodiment, the forming of the circuit pattern may include: forming a resist pattern on the base substrate to expose a region where the circuit pattern is to be formed; forming a conductive layer pattern in a region exposed by the resist pattern using a plating method; and removing the resist pattern.

In one embodiment, the base substrate includes a core insulating layer; and a copper layer disposed on an upper surface and a lower surface of the core insulating layer, respectively.

In one embodiment, the test support substrate comprises a prepreg; A copper clad laminate (CCL) in which copper foil is attached to both surfaces of the prepreg (PRG) may be included.

In one embodiment, the test support substrate includes a core insulating layer; and a copper layer disposed on an upper surface and a lower surface of the core insulating layer, respectively, and before bonding the carrier substrate, further comprising the step of forming an adhesive layer on one surface of the circuit pattern structure, the test support substrate The forming of the test hole may include removing the copper layer formed on the lower surface of the core insulating layer by selectively etching; selectively removing the core insulating layer; and selectively removing the copper layer and the adhesive layer formed on the upper surface of the core insulating layer to expose the circuit pattern.

In an embodiment, the adhesive layer may be made of a material that can be removed together in an etching process for removing the copper layer.

In an embodiment, the core insulating layer may be removed using a laser, and the copper layer and the adhesive layer may be removed by an etching method using an etchant.

In a method for manufacturing a package according to another aspect of the present application, a circuit structure substrate comprising at least one layer of a circuit pattern and an insulating layer of at least one layer formed to insulate between the circuit pattern and expose a part of the circuit pattern; preparing; bonding a test support substrate to one surface of the circuit structure substrate; forming a rest hole penetrating the test support substrate and exposing a portion of the circuit pattern; contacting a probe of a probe test apparatus to the exposed circuit pattern through the test hole, and performing a probe test to perform an electrical test on the circuit structure board; after the electrical test is completed, mounting the device chip on the circuit structure substrate; forming a molding layer covering the device chip on the circuit structure substrate; and removing the test support substrate from the circuit structure substrate.

In an embodiment, the step of mounting the device chip on the circuit structure substrate may be performed in a state in which the test support substrate is bonded to the circuit structure substrate.

According to the present invention, a test support substrate is bonded to one surface of a circuit structure substrate comprising at least one circuit pattern and at least one insulating layer insulating them, and a probe test for the circuit pattern is possible, the test A test hole for exposing a portion of the circuit pattern may be formed in the support substrate. Since the test support substrate can perform an electrical test on the circuit pattern through the test hole while serving as a support, the reliability of the manufactured printed circuit board can be improved. In addition, when a package is manufactured using such a printed circuit board, the reliability of the package can be improved, and defects due to electrical defects of the printed circuit board can be prevented in advance after packaging, thereby reducing the package manufacturing period and manufacturing cost. can

1 is a cross-sectional view schematically showing a printed circuit board structure according to an embodiment of the present application.
2 to 9 are cross-sectional views schematically illustrating a method for manufacturing a printed circuit board and a packaging method using the same according to an embodiment of the present application.

Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the present disclosure may be implemented in several different forms and is not limited to the embodiments described herein. In the drawings, in order to clearly express the components of each device, the sizes of the components such as width and thickness are somewhat enlarged. In the description of the drawings as a whole, it has been described from an observer's point of view, and when an element is referred to as being positioned on another element, this means that the element may be positioned directly on the other element or an additional element may be interposed between the elements. include

The same reference numerals in the plurality of drawings refer to elements that are substantially the same as each other. In addition, the singular expression should be understood to include the plural expression unless the context clearly indicates otherwise, and terms such as 'comprise' or 'have' are used to refer to the described feature, number, step, operation, component, or part. or a combination thereof, but it is to be understood that it does not preclude the possibility of the existence or addition of one or more other features or numbers, steps, operations, components, parts, or combinations thereof.

In addition, in performing the method or the manufacturing method, each process constituting the method may occur differently from the specified order unless a specific order is clearly described in context. That is, each process may occur in the same order as the specified order, may be performed substantially simultaneously, and in some cases, a case in which the process is performed in the reverse order is not excluded.

The present application relates to a printed circuit board structure and a method for manufacturing a printed circuit board using the same, wherein a test hole is formed so that a probe of a probe test device can contact a test support substrate bonded to the circuit structure board to allow the circuit structure It is possible to provide a printed circuit board structure that enables electrical inspection of a substrate, and a method of manufacturing a printed circuit board using the same. In addition, by using such a printed circuit board structure and a method for manufacturing the same, it is possible to provide a method for manufacturing a reliable package.

1 is a cross-sectional view schematically showing a printed circuit board structure 1 according to an embodiment of the present application. Referring to FIG. 1 , a printed circuit board structure 1 according to an embodiment of the present application includes a test support substrate 200 and at least one or more layered circuit patterns 131 arranged on the test support substrate 200 , 132, 133) and at least one insulating layer 141, 142 disposed to expose a portion of the circuit pattern while electrically separating the circuit patterns 131, 132, 133, and the circuit pattern ( It may include an upper solder resist layer 170 and a lower solder resist layer 150 disposed to expose at least a portion of the 133 . In this case, at least one or more circuit patterns 131 , 132 , and 133 are disposed on the test support substrate 200 , at least one or more insulating layers 141 and 142 , and upper and lower solder resist films 150 and 170 . A circuit structure including a circuit structure may be referred to as a circuit structure substrate.

The test support substrate 200 may include a core insulating layer 201 and copper layers 212a and 212b respectively disposed on upper and lower surfaces of the core insulating layer 201 . The core insulating layer 201 may include, for example, epoxy or prepreg (PPG). The test support substrate 200 may include, for example, a prepreg and a copper clad laminate (CCL) in which copper foil is attached to both surfaces of the prepreg (PRG). A release layer may be further included between the core insulating layer 201 and the copper layers 212a and 212b. The release layer adheres to, for example, the core insulating layer 201 disposed below and the copper layers 212a and 212b disposed above when a peeling factor is not provided, but when the peeling factor is provided in the release layer At least the release layer and the core insulating layer may be separated from each other, and peeling may occur. Accordingly, when a chip such as an integrated circuit is mounted on the printed circuit board structure and packaged, the test support substrate 200 may be easily removed. The peeling factor may be various factors such as heat, ultraviolet (UV) light, or laser.

An adhesive layer 160 for bonding the test support substrate and the lower solder resist layer may be disposed between the test support substrate 200 and the lower solder resist layer 150 . The adhesive layer 160 may be a layer of various materials capable of bonding the test support substrate 200 and the lower solder resist film to each other. Preferably, the adhesive layer 160 may be made of a material that can be removed together with the copper layer 212a in the process of forming the test hole 220 in the test support substrate.

The test support substrate 200 is provided with a test hole 220 penetrating the test support substrate 200 as shown, and the test hole 220 is disposed between the test support substrate 200 and the circuit pattern. A portion of the circuit pattern 133 is exposed through the adhesive layer 160 . The test hole 220 may be sized to allow a probe of a test apparatus to be connected to the exposed circuit pattern. Since the circuit pattern is exposed by the test hole 220 , the circuit patterns stacked on the test support substrate 200 may be electrically tested through the test hole 220 . For example, a current is passed through a circuit pattern exposed to one surface of the printed circuit board by the upper solder resist film 170 and exposed through the test hole 220 on the opposite side using the probe of the probe test apparatus. By measuring in the circuit pattern, a short circuit or a connection defect between the circuit patterns can be inspected.

Conventionally, electrical inspection of the printed circuit board was impossible because there was no test hole in the carrier substrate to be attached to implement the printed circuit board. Since it is possible to perform an electrical inspection on the printed circuit board, it is possible to improve the reliability of the printed circuit board.

Next, a method of manufacturing a printed circuit board according to an embodiment of the present application will be described with reference to FIGS. 2 to 9 .

2 to 9 are cross-sectional views schematically illustrating a method of manufacturing a printed circuit board according to an embodiment of the present application.

Referring to FIG. 2 , the core insulating layer 101 , the release layers 110a and 110b disposed on the core insulating layer 101 , and the base copper layers 120a and 120b disposed on the release layers 110a and 110b . ) to prepare a base substrate having As shown, the release layers 110a and 110b may be formed on both surfaces of the core insulating layer 101 , and the base copper layers 120a and 120b may be formed on both surfaces of the release layers 110a and 110b. can

The core insulating layer 101 may include, for example, epoxy or prepreg (PPG). The base substrate may include, for example, a prepreg (PRG) and a copper clad laminate (CCL) in which copper foil is attached to both surfaces of the prepreg. The release layers 110a and 110b adhere to, for example, the core insulating layer 101 disposed below and the base copper layers 120a and 120b disposed thereon when a peeling factor is not provided, but the peeling factor is When provided in the release layer, at least the release layers 110a and 110b and the core insulating layer 101 are separated from each other and peeling may occur. Accordingly, it is possible to easily remove the base substrate from the structure including the circuit pattern in the intermediate stage of the printed circuit board manufacturing process. The peeling factor may be various factors such as heat, ultraviolet (UV) light, or laser.

Referring to FIG. 3 , first circuit patterns 131a and 131b are formed on the surfaces of the base copper layers 120a and 120b. The first circuit patterns 131a and 131b may be formed by a plating method using the base copper layers 120a and 120b as a seed layer. Specifically, a resist pattern (not shown) defining an area in which a circuit pattern is to be formed is formed by sequentially applying a resist, exposing, and developing a resist on the surface of the base copper layers 120a and 120b, and the resist pattern is applied to the resist pattern. After forming the first circuit patterns 131a and 131b by performing a plating process using the base copper layers 120a and 120b exposed by the electrode as a seed layer, the resist pattern is removed. As a method of forming the first circuit patterns 131a and 131b, as an example, a semi-additive process (SAP) or a modified semi-additive process (MSAP) may be applied.

Referring to FIG. 4 , insulating layers 141a , 141b , 142a , 142b covering the circuit patterns on upper and lower surfaces of the structure of FIG. 3 in which the first circuit patterns 131a and 131b are formed, and the first circuit pattern Second circuit patterns 132a and 132b connected to 131a and 131b and third circuit patterns 133a and 133b are sequentially formed. Specifically, first insulating layers 141a and 141b exposing at least a portion of the first circuit patterns 131a and 131b are formed on the upper and lower surfaces of the structure of FIG. 3 in which the first circuit patterns 131a and 131b are formed. and second circuit patterns 132a and 132b connected to the exposed first circuit patterns are formed. The second circuit patterns 132a and 132b may be formed by plating using the exposed portions of the first circuit patterns 131a and 131b as a seed layer. In this case, a resist pattern (not shown) may be formed by applying a resist, exposing, and developing to define a region where the second circuit patterns 132a and 132b are to be formed.

Next, the second insulating layers 142a and 142b exposing at least a portion of the second circuit pattern while covering the structure in which the second circuit patterns 132a and 132b are formed are connected to the second circuit patterns 132a and 132b a first solder resist film 150a, which forms the third circuit patterns 133a and 133b to be 150b). The first solder resist layers 150a and 150b are for protecting circuit patterns from external environments and improving electrical strength, and may be formed of, for example, solder resist such as epoxy resin. .

The third circuit patterns 133a and 133b may be formed by plating in the same manner as the first circuit patterns 131a and 131b and the second circuit patterns 132a and 132b. In this embodiment, the case where the first to third circuit patterns are respectively formed on the upper and lower surfaces of the base substrate has been described as an example, but the number of circuit pattern layers and insulating layers formed on the upper and lower surfaces of the base substrate depends on the embodiment may vary depending on In addition, the circuit pattern and the insulating layer may be formed only on the upper surface or the lower surface of the base substrate. Accordingly, the circuit structure board according to an embodiment of the present application may be manufactured.

Referring to FIG. 5 , test support substrates 200a and 200b are bonded to upper and lower surfaces of the circuit structure substrate of FIG. 4 on which the first solder resist films 150a and 150b are formed. Specifically, adhesive layers 160a and 160b are formed on the upper and lower surfaces of the structure on which the first solder resist films 150a and 150b are formed. The adhesive layers 160a and 160b are for bonding the structure on which the first solder resist layers 10a and 150b are formed and the test support substrates 200a and 200b, and may be, for example, an adhesive metal layer. The adhesive layers 160a and 160b may be formed of a material that can be removed together with the base copper layers 120a and 120b in the process of forming a test hole in the test support substrate in a subsequent step to simplify the process.

Next, test support substrates 200a and 200b including core insulating layers 201a and 201b on the surface of the adhesive layers 160a and 160b, and copper layers 210a and 210b respectively formed on the upper and lower surfaces of the core insulating layer. join The test support boards 200a and 200b may serve to support the printed circuit board when an electronic chip is mounted on the printed circuit board in a subsequent packaging step.

The core insulating layers 201a and 201b may include, for example, epoxy or prepreg (PPG). The test support substrates 200a and 200b may include, for example, a prepreg (PRG) and a copper clad laminate (CCL) in which copper foil is attached to both surfaces of the prepreg. A release layer may be further formed between the core insulating layers 201a and 201b and the copper layers 210a and 210b. The release layer adheres to, for example, the core insulating layers 201a, 201b and the copper layers 210a, 210b when a release factor is not provided, but at least the release layer and the core insulation when a release factor is provided in the release layer. As the layers 201a and 201b separate from each other, peeling may occur. Accordingly, the test support substrate can be easily removed when packaging a semiconductor chip or the like on a subsequent printed circuit board. The peeling factor may be various factors such as heat, ultraviolet (UV) light, or laser.

Referring to FIG. 6 , the base substrate is separated from the structure of FIG. 5 to which the test support substrate 200b is bonded. Specifically, a peeling factor is applied to the release layer (110a, 110b in FIG. 5) to separate the interface between the core insulating layer (101 in FIG. 5) and the base copper layer (120a, 120b in FIG. 5), and the base copper layer (120a, 120b in FIG. 5) is removed. The peeling factor may be various factors such as heat, ultraviolet (UV) light, or laser. As a result, two intermediate structures of the upper and lower printed circuit boards may be manufactured, and the first circuit patterns 131a and 131b are exposed by removing the base substrate. 5 and 6 together, the two printed circuit board intermediate structures include core insulating layers 201a and 201b and copper layers 210a, 210b, 212a, and 212b respectively formed on the upper and lower surfaces of the core insulating layer. the test support substrates 200a and 200b, the adhesive layers 160a and 160b disposed on the test support substrate, the solder resist films 150a and 150b, and the circuit patterns 131a, 132a, 133a, 131b, 132b, 133b ), and insulating layers 141a, 142b, 141b, and 142b disposed to electrically insulate between the circuit patterns. In FIG. 6 , for convenience, a lower printed circuit board intermediate structure is shown among upper and lower printed circuit board intermediate structures separated from FIG. 5 . Hereinafter, a method of manufacturing a printed circuit board using the lower printed circuit board intermediate structure will be described. A method of manufacturing a printed circuit board using the upper printed circuit board intermediate structure is substantially the same.

Subsequently, referring to FIG. 6 , a second solder resist layer 170 exposing a portion of the first circuit pattern 131b is formed. The second solder resist film 170 may be made of substantially the same material as the first solder resist film 150b.

Referring to FIG. 7 , a part of a circuit pattern is exposed on the test support substrate 200b to form a test hole 220 for a probe test on the circuit pattern. Specifically, a part of the copper layer 212b formed on the lower surface of the core insulating layer 201b is removed, and a part of the core insulating layer 201b is removed. A region overlapping at least a portion of the circuit pattern 133b to be tested may be selectively removed from the copper layer 212b and the core insulating layer 201b. The copper layer 212b may be removed by, for example, an etching method, and the core insulating layer 201b including epoxy or prepreg (PPG) may be selectively removed using, for example, a laser. can be removed with Next, the test hole 220 exposing the circuit pattern 133b in the region to be tested is formed by selectively removing the copper layer 212a and the adhesive layer 160b formed on the upper surface of the core insulating layer. When the adhesive layer 160b is made of a material having the same or similar etch rate as the copper layer 212a in the etching process for removing the copper layer 212a, the copper layer 212a and the adhesive layer 160b may be removed together. Therefore, the process can be simplified.

As a result, a test hole 220 penetrating through the test support substrate 200b and exposing a portion of the circuit pattern 133b is formed in the test support substrate 200b. As a result, the printed circuit board structure of FIG. 7 in which the test support substrate 200b and the circuit structure disposed on the test support substrate 200b are coupled may be manufactured.

In the printed circuit board structure, since the circuit pattern is exposed by the test hole 220 , an electrical test may be performed on the circuit patterns stacked on the test support substrate 200b. For example, by passing a current through the circuit pattern 131b exposed to one surface of the printed circuit board structure and measuring the circuit pattern 133b exposed through the test hole 220 on the opposite side, an electrical short between circuit patterns Alternatively, a connection defect or the like may be inspected. Conventionally, electrical inspection of the printed circuit board was impossible because one side of the printed circuit board was blocked due to the test support board attached to implement the printed circuit board, but according to the present invention, the test support board serves as a support. Since the electrical test can be performed on the circuit pattern through the test hole 220 while performing the test, the reliability of the printed circuit board can be improved.

When the manufacturing of the printed circuit board is completed, an electrical test is performed on the printed circuit board through the test hole 220 , and when it is confirmed that the printed circuit board is good, it can be classified as a normal product.

According to the method of manufacturing a printed circuit board of an embodiment of the present application described above, by manufacturing a printed circuit board structure using a test support substrate, an electrical test on the printed circuit board (ie, circuit structure board including a circuit pattern) is performed can proceed effectively. Specifically, after forming a circuit pattern structure including at least one or more circuit patterns and at least one insulating layer for insulating the circuit patterns, bonding to the test support substrate using an adhesive layer and removing the base substrate, the probe test A test hole is formed in the test support substrate to expose the circuit pattern in the region to be formed. Since the test support board can perform a probe test on the circuit pattern through the test hole while serving as a support, the reliability of the printed circuit board can be improved.

On the other hand, in this embodiment, it has been described that the circuit pattern and the insulating layer are formed on both sides of the base substrate and then separated, but this is only an example. can do.

Subsequently, an example of a process of forming a package using the printed circuit board structure according to an embodiment of the present application will be described.

Referring to FIG. 8 , the device chip is mounted on the printed circuit board structure manufactured in FIG. 7 . The device chip may include a chip body 300 and a chip pad 310 disposed on one surface of the chip body 300 . The connection structure 310 may be, for example, a bump or a solder material, and the device chip may be, for example, an active device. The device chip may be electrically connected to the circuit pattern 131b formed on the printed circuit board through the chip pad 310 . A connection pad (not shown) for connection to the device chip may be formed on the surface of the circuit pattern 131b.

A molding layer 320 covering the device chip is formed by injecting a molding material onto the resulting structure in which the device chip is mounted. The molding layer 320 serves to protect the device chip from the external environment, and may be formed of, for example, an epoxy mold compound (EMC).

Referring to FIG. 9 , the second solder resist film 150 and the circuit pattern 133 are removed by removing the test support substrate (200b in FIG. 8) and the adhesive layer (160b in FIG. 8) from the structure of FIG. 8 on which the device chip is mounted. This exposes Next, a package using a printed circuit board may be manufactured by forming, for example, a solder ball 330 as a connection structure on the exposed circuit pattern 133 .

According to the above-described embodiment of the present application, a test support substrate is bonded to one surface of a circuit pattern structure including at least one circuit pattern and at least one insulating layer insulating them, and the test is performed on the test support substrate. By forming the test hole exposing the circuit pattern, the test support substrate can perform an electrical inspection on the circuit pattern through the test hole while serving as a support, thereby improving the reliability of the printed circuit board. When a package is manufactured using the printed circuit board, the reliability of the package can be improved and defects due to electrical defects of the printed circuit board can be prevented in advance after packaging, thereby reducing the package manufacturing period and manufacturing cost.

Although the above has been described with reference to the drawings and embodiments, those skilled in the art can variously modify and change the embodiments disclosed in the present application within the scope not departing from the technical spirit of the present application described in the claims below. You will understand that it can be done.

1: printed circuit board
101, 201a, 201b: core insulating layer
110a, 110b: release layer
120a, 120b, 212a, 212b: copper layer
131a, 131b, 132a, 132b, 133a, 133b: circuit pattern
141a, 141b, 142a, 142b: insulating layer
150a, 150b, 170: solder resist film
160: adhesive layer
220: test hall
300: device chip
310, 330: connection structure
320: molding layer (EMC)

Claims (14)

a test support substrate including a test hole; and
A circuit structure substrate disposed on the test support substrate and including at least one or more layers of circuit patterns as passages of electrical signals and an insulating layer disposed to insulate between the circuit patterns and to expose a portion of the circuit patterns, ,
wherein the test hole is disposed in the test support substrate and configured to penetrate through the test support substrate to expose a portion of the circuit pattern to enable contact of a probe of a probe test apparatus with respect to the circuit pattern;
Printed circuit board structure.
According to claim 1,
The test support substrate,
core insulating layer;
a copper layer disposed on an upper surface and a lower surface of the core insulating layer, respectively; and
a through hole as the test hole penetrating the core insulating layer and the copper layer;
Printed circuit board structure.
According to claim 1,
The test support substrate is
prepreg;
a copper clad laminate (CCL) in which copper foil is attached to both surfaces of the prepreg (PRG); and
including a through hole as the test hole penetrating the prepreg and the copper clad laminate;
Printed circuit board structure.
4. The method of claim 2 or 3,
Further comprising an adhesive layer disposed between the test support substrate and the circuit structure substrate,
Printed circuit board structure.
preparing a circuit structure substrate including at least one circuit pattern and at least one insulating layer formed to insulate between the circuit patterns and to expose a portion of the circuit pattern;
bonding a test support substrate to one surface of the circuit structure substrate;
forming a test hole penetrating the test support substrate and exposing a portion of the circuit pattern; and
Contacting a probe of a probe test apparatus with respect to the exposed circuit pattern through the test hole, and performing a probe test to perform an electrical test on the circuit structure board,
A method for manufacturing a printed circuit board.
6. The method of claim 5,
The step of preparing the circuit structure substrate,
preparing a base substrate;
At least one layer of circuit patterns on the upper and lower surfaces of the base substrate by forming a circuit pattern on the upper and lower surfaces of the base substrate and forming an insulating layer exposing a part of the circuit pattern at least once, forming an insulating layer exposing a portion of the circuit pattern while insulating between the circuit patterns; and
forming a solder resist film to expose a portion of the circuit pattern;
The base substrate is removed after bonding the test support substrate,
A method for manufacturing a printed circuit board.
7. The method of claim 6,
Forming the circuit pattern comprises:
forming, on the base substrate, a resist pattern exposing a region where the circuit pattern is to be formed;
forming a conductive layer pattern in a region exposed by the resist pattern using a plating method; and
Comprising the step of removing the resist pattern,
A method for manufacturing a printed circuit board.
7. The method of claim 6,
The base substrate is
core insulating layer; and
Containing a copper layer respectively disposed on the upper surface and the lower surface of the core insulating layer,
A method for manufacturing a printed circuit board.
6. The method of claim 5,
The test support substrate is
prepreg;
Comprising a copper clad laminate (CCL) having copper foil attached to both sides of the prepreg (PRG)
A method for manufacturing a printed circuit board.
6. The method of claim 5,
The test support substrate is
core insulating layer; and
a copper layer disposed on an upper surface and a lower surface of the core insulating layer, respectively;
Before bonding the test support substrate, further comprising the step of forming an adhesive layer on one surface of the circuit pattern structure,
The step of forming a test hole in the test support substrate,
removing the copper layer formed on the lower surface of the core insulating layer by selectively etching;
selectively removing the core insulating layer; and
Exposing the circuit pattern by selectively removing the copper layer and the adhesive layer formed on the upper surface of the core insulating layer,
A method for manufacturing a printed circuit board.
11. The method of claim 10,
The adhesive layer is made of a material that can be removed together in an etching process for removing the copper layer,
A method for manufacturing a printed circuit board.
11. The method of claim 10,
The core insulating layer is removed using a laser,
The copper layer and the adhesive layer are removed by an etching method using an etchant,
A method for manufacturing a printed circuit board.
preparing a circuit structure substrate including at least one circuit pattern and at least one insulating layer formed to insulate between the circuit patterns and to expose a portion of the circuit pattern;
bonding a test support substrate to one surface of the circuit structure substrate;
forming a test hole penetrating the test support substrate and exposing a portion of the circuit pattern; and
contacting a probe of a probe test apparatus to the exposed circuit pattern through the test hole, and performing a probe test to perform an electrical test on the circuit structure board;
after the electrical test is completed, mounting the device chip on the circuit structure substrate;
forming a molding layer covering the small chip on the circuit structure substrate; and
removing the test support substrate from the circuit structure substrate;
How to make a package.
14. The method of claim 13,
The step of mounting the device chip on the circuit structure substrate
The test support substrate proceeds in a state in which it is bonded to the circuit structure substrate
How to make a package.

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