KR20120137300A - Method of manufacturing multilayer wiring substrate, and multilayer wiring substrate - Google Patents

Abstract

PURPOSE: A method for manufacturing a multilayer wiring substrate and the multilayer wiring substrate are provided to prevent the thickness imbalance of a chip component connection terminal by including a plating layer forming process for forming a dummy plating layer around product plating layers. CONSTITUTION: Resin insulating layers(20-27) and a conductor layer(28) are formed on a support substrate. Multiple IC chip connection terminals(41) and multiple condenser connection terminals(42) are formed on an upper surface(31) of a wiring lamination part. Multiple openings(37) are formed within the outermost resin insulating layer. A via conductor(34) connects the IC chip connection terminal, the condenser connection terminal and a mother board connection terminal.

Description

METHOD OF MANUFACTURING MULTILAYER WIRING SUBSTRATE, AND MULTILAYER WIRING SUBSTRATE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board in which a plurality of chip component connection terminals capable of connecting chip components are disposed on a substrate main surface, and a manufacturing method thereof.

BACKGROUND ART [0002] Semiconductor integrated circuit chips (IC chips) used as microprocessors for computers, etc. have recently become faster and higher in functionality, and as a result, the number of terminals increases and the pitch between terminals narrows. In general, a plurality of terminals are densely arranged on the bottom of the IC chip in an array shape, and such terminal groups are connected in the form of flip chips with respect to the motherboard side terminal group. However, in the IC chip terminal group and the motherboard side terminal group, there is a large difference in pitch between the terminals, so that it is difficult to directly connect the IC chip on the motherboard. Therefore, a method is usually adopted in which a semiconductor package including an IC chip mounted on an IC chip mounting wiring board is manufactured, and the semiconductor package is mounted on a motherboard.

As the IC chip mounting wiring board constituting this package, a multilayer wiring board formed by laminating a plurality of resin insulating layers and a plurality of conductor layers is used. Then, a plurality of IC chip connection terminals for connecting IC chips are provided on the main surface of the multilayer wiring board, and a plurality of mother board connection terminals for connecting to the mother board (mother board) are provided on the substrate back surface. have. In this kind of multilayer wiring board, the wiring pattern of the conductor layer and the IC chip connection terminal are formed of copper plating to achieve fine pitch (see Japanese Patent Laid-Open No. 2005-272874, for example). Further, in this kind of multilayer wiring board, an identification mark (alignment mark) for aligning the IC chip is formed on the side of the substrate main surface (see, for example, Japanese Patent Laid-Open No. 2002-204057).

Patent Document 1: Japanese Patent Laid-Open No. 2005-272874 Patent Document 2: Japanese Patent Application Laid-Open No. 2002-204057

However, in the multilayer wiring board, the area ratio (area ratio of the conductor layer) of the copper plating layer formed on the inner layer side is usually about 60% to 80%, whereas the area ratio of the copper plating layer on the main surface of the substrate (each IC chip connection terminal). Area ratio) may be less than 10%. In general, the IC chip connection terminals are arranged in a center of the substrate main surface. In this case, when the copper plating layer of the IC chip connecting terminal is formed, concentration of the plating current occurs and an imbalance occurs in the thickness of the copper plating layer. As a result, the connection reliability of each IC chip connection terminal and IC chip of a multilayer wiring board falls. In addition, connection terminals for connecting chip components such as chip capacitors, etc., are provided on the substrate main surface of the multilayer wiring board, but these connection terminals also have thickness imbalances.

Japanese Patent Laid-Open No. 2005-272874 discloses a method of increasing the current density of plating from the initial current density in order to suppress the shape and height imbalance of conductor bumps. Even if this method is adopted, when the IC chip connection terminals are disposed in the center of the substrate main surface, the concentration of the plating current cannot be avoided, resulting in an unbalance in the thickness of the copper plating layer. Let the said subject be a 1st subject.

The first aspect of the present invention has been made in view of the first problem, and an object thereof is to provide a method for manufacturing a multilayer wiring board which can suppress the thickness unbalance of the chip component connection terminal and increase the connection reliability with the chip component. .

By the way, in the conventional multilayer wiring board, the recognition mark is formed by forming an opening in the resin insulating layer of the outermost layer and plating the exposed conductor layer. This recognition mark is a mark recognized by the difference in light reflectance on the surface of the plating layer and the surface of the resin insulating layer. In addition to the IC mark alignment mark, a multilayer wiring board having a positioning mark for positioning the wiring board itself as a recognition mark, a recognition mark such as a product number and a manufacturing rod number, has also been put into practical use. When forming such a recognition mark, the formation process of a conductor layer, an opening part, or a plating process is needed. In addition, plating on the recognition mark is generally performed by the same plating process as plating on the IC chip connecting terminal. In this plating process, in order to secure soldering property, gold plating etc. which are comparatively expensive may be performed. For this reason, the problem that the manufacturing cost of a multilayer wiring board rises. Let the said subject be a 2nd subject.

The second aspect of the present invention has been made in view of the second problem, and an object thereof is to provide a multi-layered wiring board which can form a recognition mark on the substrate main surface at low cost. Another object is to provide a method for producing a multilayer wiring board suitable for manufacturing the multilayer wiring board.

According to the first aspect of the present invention, the means (means 1) for solving the above problems includes a substrate main surface and a substrate back surface, and has a structure in which a plurality of resin insulating layers and a plurality of conductor layers are laminated. A method of manufacturing a multilayer wiring board in which a plurality of chip component connection terminals connectable to the substrate are disposed on the main surface of the substrate, wherein the plurality of chip component connection terminals are formed on the surface of the resin insulating layer of the outermost layer exposed from the main surface of the substrate. And a plating layer forming step of forming a product plating layer to be formed and forming a dummy plating layer around the product plating layer (first method).

According to the invention described in the means 1, by performing the plating layer forming step, a dummy plating layer is formed around the product plating layer in addition to the product plating layer which becomes the chip component connection terminal on the substrate main surface of the multilayer wiring board. In this case, the area ratio of the plating layer on the substrate main surface can be increased, and the concentration of the plating current is avoided, and the thickness imbalance of the product plating layer is eliminated. As a result, each chip part connection terminal can be formed in a uniform thickness on the board | substrate main surface of a multilayer wiring board, and the connection reliability of each chip part connection terminal and a chip component can be improved.

In the manufacturing method of the multilayer wiring board (first method), a resist forming step of forming an etching resist so as to cover the product plating layer on the substrate main surface side, and a plating layer removal for removing the dummy plating layer exposed on the substrate main surface side by etching. It is preferable to further include a process. In this case, only the product plating layer which becomes a chip component connection terminal remains on the board | substrate main surface of a multilayer wiring board. For this reason, the plating for improving solder wettability can be reliably formed only on the surface of a product plating layer. In addition, the problem that the chip component is incorrectly connected to the dummy plating layer is avoided.

In the plating layer formation process, it is preferable to form a dummy plating layer so that the area ratio of the plating layer with respect to the surface area of a board | substrate main surface may be 60% or more and 95% or less. In this way, concentration of the plating current can be reliably avoided, and the product plating layer can be formed with a uniform thickness.

In the case of manufacturing a multilayer wiring board having no core board, a lamination step of laminating a plurality of resin insulating layers and a plurality of conductor layers on the support substrate through metal foil, and separating the support substrate at the interface of the metal foil, And a substrate separation step of exposing the metal foil to the side. When the plating layer removing step is performed after the substrate separation step, the dummy plating layer on the substrate main surface side can be removed by etching, and the metal foil on the substrate lower surface side can be removed by etching. For this reason, compared with the conventional manufacturing method, a multilayer wiring board can be manufactured by the same process number, and manufacturing cost can be held low.

On the main board surface of the multilayer wiring board, a plurality of IC chip connection terminals capable of connecting IC chips and a plurality of capacitor connection terminals capable of connecting chip capacitors may be provided as chip component connection terminals. In this case, the product plating layers of the plurality of IC chip connection terminals and the plurality of capacitor connection terminals can be formed to have a uniform thickness, and the connection reliability with the IC chip or the chip capacitor can be improved.

The pattern shape of a dummy plating layer is not specifically limited, It can change suitably according to the shape, area ratio, etc. of a product plating layer. Specifically, the dummy plating layer may be a plain pattern (solid pattern) having a large area, or may be a plane pattern having a mesh. In addition, the dummy plating layer may have a pattern corresponding to the shape and size of the adjacent product plating layer.

In the plating layer forming step, it is preferable to form a field via for connecting the inner layer side conductor layer and the chip component connecting terminal simultaneously with the product plating layer and the dummy plating layer.

Moreover, it is preferable to form a dummy plating layer so that a dummy plating layer may have an area ratio of 10 times or more of a product plating layer. In this way, even when the area ratio of the product plating layer is small, by forming the dummy plating layer having a large area, it is possible to reliably avoid current concentration during plating.

The product plating layer and the dummy plating layer are preferably formed of copper plating. Thus, when the product plating layer is formed by copper plating, the electrical resistance of the chip component connection terminal can be suppressed low.

In the plating layer forming step, the area ratio of the dummy plating layer occupied by the dummy plating layer forming region determined by the outer edge of the dummy plating layer can be arbitrarily set. For example, it may be set to 30% or more and 100% or less. In this case, it is preferable to form a dummy plating layer so that the distance of a product plating layer and a dummy plating layer may be 0.1 mm or more and 10 mm or less. By doing in this way, current concentration at the time of plating can be avoided more reliably. In addition, when the area ratio of the dummy plating layer is relatively large, it is better to set the distance slightly larger. On the contrary, when the area ratio of the dummy plating layer is relatively small, it is better to set the distance slightly smaller.

It is assumed here that the plurality of chip component connection terminals are a plurality of IC chip connection terminals capable of connecting IC chips as chip components. In addition, the vertical dimension of the rectangular chip mounting area formed by arranging the plurality of IC chip connection terminals in an array shape is X (cm) and the horizontal dimension is Y (cm), and the product plating layer of the plurality of IC chip connection terminals It is assumed that the design value of the thickness is Z (µm). At this time, the standard deviation (?) (Μm) of the measured value of the thickness of the product plating layer is represented by the following equation. In addition, the design value Z (micrometer) can also be represented by the average value (micrometer) of the thickness of the product plating layer in several IC chip connection terminal.

According to the second aspect of the present invention, the means for solving the above problems (means 2) has a substrate main surface and a substrate back surface, and has a structure in which a plurality of resin insulating layers and a plurality of conductor layers are laminated. A multi-layered wiring board having a plurality of chip component connection terminals which can be connected to each other. There is a multilayer wiring board which is characterized by the above-mentioned.

According to the invention described in the means 2, a recognition mark is formed on the substrate main surface serving as the mounting surface of the chip component by the difference in color shade of the resin surface. In this case, since the recognition mark can be recognized without forming the conductor layer or the opening as in the prior art, the manufacturing cost of the multilayer wiring board can be reduced.

The conductor portion may be exposed at the outer peripheral side of the substrate main surface, and may further include a positioning mark recognized by the difference in light reflectance between the resin surface of the resin insulating layer of the outermost layer and the surface of the conductor portion. In this case, the recognition mark due to the difference in color shade and the positioning mark due to the difference in light reflectance can be formed according to the use. Further, if the number of formation of the positioning marks due to the difference in the light reflectance is minimized and other recognition marks are formed by the difference in the color shades, the increase in the manufacturing cost of the multilayer wiring board can be suppressed low. In addition, the recognition mark formed by the difference in color shade can also be used as a positioning mark such as a chip component.

In the resin insulating layer of the outermost layer exposed at the substrate main surface side, a pattern formed by a difference in color shade of the resin surface and may be provided with a pattern in which a pattern of a predetermined pattern is regularly arranged. As described above, by forming a pattern on the main surface of the substrate, the designability of the multilayer wiring board can be improved.

In addition, as another means (means 3) for solving the above problems, a method of manufacturing the multilayer wiring board according to the means 2, wherein the plurality of chip components are formed on the surface of the resin insulating layer of the outermost layer exposed from the main surface of the substrate. A plating layer forming step of forming a product plating layer serving as a connection terminal and forming a dummy plating layer having a shape corresponding to the recognition mark, and heat-treating the resin insulating layer of the outermost layer to prepare the surface of the resin insulating layer of the outermost layer. And a dummy plating layer removal step of removing the recognition mark forming process of discoloring, and removing the dummy plating layer by etching after forming an etching resist to cover the product plating layer on the substrate main surface side. There is a manufacturing method (second method).

According to the invention described in the means 3, when the dummy plating layer is formed in the plating layer forming step and then the resin insulating layer of the outermost layer is heat treated in the recognition mark forming step, the surface of the exposed resin insulating layer of the outermost layer is discolored. The surface of the resin insulating layer covered with the dummy plating layer does not discolor. Thereafter, the dummy plating layer is etched away by the dummy plating layer removing step to expose the surface of the resin insulating layer that is not discolored. As a result, a difference in color shades occurs on the resin surface depending on the pattern shape of the dummy plating layer, and a recognition mark can be formed by the difference in shades.

The recognition mark forming process preferably serves as annealing of the resin insulating layer. Specifically, the heat treatment in the recognition mark forming step is a process of blowing hot air on the exposed surface of the resin insulating layer. In this case, the annealing process and the recognition mark forming process, which have been performed in the conventional substrate manufacturing, do not need to be performed by separate heat treatment, so that the manufacturing cost of the multilayer wiring board can be kept low.

In addition, it is preferable to apply the manufacturing method (second method) of the present invention as a manufacturing method of a coreless wiring board having no core board. Specifically, a method for manufacturing a coreless wiring board includes a lamination step of laminating a plurality of resin insulating layers and a plurality of conductor layers on a support substrate through a metal foil, and separating the support substrate at the interface of the metal foil to form a metal foil on the back side of the substrate. It further includes a substrate separation process to expose. When the plating layer removing step is performed after the substrate separation step, the dummy plating layer on the substrate main surface side can be removed by etching, and the metal foil on the substrate lower surface side can be removed by etching. Therefore, the wiring board can be manufactured by the same number of steps as the conventional manufacturing method, and the manufacturing cost can be kept low.

The resin insulating layer constituting the multilayer wiring board is preferably formed using a buildup material mainly composed of a thermosetting resin. Specific examples of the material for forming the resin insulating layer include thermosetting resins such as epoxy resins, phenol resins, urethane resins, silicone resins, and polyimide resins. In addition, resins obtained by impregnating thermosetting resins, such as epoxy resins, with a composite material of these resins and organic fibers such as glass fibers (glass woven or glass nonwoven fabrics), polyamide fibers, or three-dimensional mesh-like fluorine resin substrates such as continuous porous PTFE- You may use a resin composite material.

The conductor layer constituting the multilayer wiring board is mainly made of copper, and is formed by a known method such as a subtractive method, a semiadditive method, a full additive method, and the like. Specifically, for example, a method of etching copper foil, electroless copper plating or electrolytic copper plating is applied. It is also possible to form a conductor layer by etching after forming a thin film by a method such as sputtering or CVD, or to form a conductor layer by printing such as a conductive paste.

Examples of chip components include electronic components such as chip resistors and chip inductors in addition to IC chips and chip capacitors. Examples of IC chips include IC chips used as microprocessors of computers, IC chips such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory).

1 is a cross-sectional view showing a schematic configuration of a multilayer wiring board according to the first embodiment.
Fig. 2 is a plan view showing a schematic configuration of a multilayer wiring board in the first embodiment.
3 is an explanatory diagram showing a method for manufacturing a multilayer wiring board in the first and third embodiments;
4 is an explanatory diagram showing a method for manufacturing a multilayer wiring board in the first and third embodiments;
5 is an explanatory diagram showing a method for manufacturing a multilayer wiring board in the first and third embodiments;
FIG. 6 is an explanatory diagram showing a method for manufacturing a multilayer wiring board in the first and third embodiments. FIG.
FIG. 7 is an explanatory diagram showing a method for manufacturing a multilayer wiring board in the first and third embodiments. FIG.
8 is an explanatory diagram showing a method for manufacturing a multilayer wiring board according to the first embodiment.
9 is an explanatory diagram showing a method for manufacturing a multilayer wiring board according to the first embodiment.
10 is an explanatory diagram showing a method for manufacturing a multilayer wiring board according to the first embodiment;
FIG. 11 is an explanatory diagram showing a method for manufacturing a multilayer wiring board in the first embodiment
FIG. 12 is an explanatory diagram showing a method for manufacturing a multilayer wiring board in the first embodiment
13 is a graph showing a measurement result of thickness imbalance of the product plating layer in the manufacturing method of the first embodiment.
14 is a graph showing measurement results of thickness imbalance of product plating layers in a prior art manufacturing method.
Fig. 15 is a graph showing the relationship between the size of the IC chip mounting area and the thickness imbalance of the product plating layer in each of the manufacturing method of the first embodiment and the manufacturing method of the prior art.
Fig. 16 is a sectional view showing a schematic configuration of a multilayer wiring board according to the second embodiment.
FIG. 17 is an explanatory diagram showing a method for manufacturing a multilayer wiring board in the second and fourth embodiments. FIG.
18 is an explanatory diagram showing a method for manufacturing a multilayer wiring board according to the second embodiment.
Fig. 19 is an explanatory diagram showing a method for manufacturing a multilayer wiring board in the second embodiment.
20 is a sectional view showing a schematic configuration of a multilayer wiring board according to the third embodiment.
FIG. 21 is a plan view showing a schematic configuration of a multilayer wiring board in a third embodiment
FIG. 22 is an explanatory diagram showing a method for manufacturing a multilayer wiring board in a third embodiment
Fig. 23 is an explanatory diagram showing a method for manufacturing a multilayer wiring board in the third embodiment.
FIG. 24 is an explanatory diagram showing a method for manufacturing a multilayer wiring board in the third embodiment
FIG. 25 is an explanatory diagram showing a method for manufacturing a multilayer wiring board according to the third embodiment. FIG.
Fig. 26 is an explanatory diagram showing a method for manufacturing a multilayer wiring board in the third embodiment.
FIG. 27 is an explanatory diagram showing a method for manufacturing a multilayer wiring board according to the third embodiment. FIG.
Fig. 28 is a sectional view showing a schematic configuration of a multilayer wiring board in the fourth embodiment.
Fig. 29 is an explanatory diagram showing a method for manufacturing a multilayer wiring board in the fourth embodiment.
30 is an explanatory diagram showing a method for manufacturing a multilayer wiring board in the fourth embodiment.
Fig. 31 is an explanatory diagram showing a method for manufacturing a multilayer wiring board in the fourth embodiment.
32 is an explanatory diagram showing a method for manufacturing a multilayer wiring board according to the fourth embodiment.

EMBODIMENT OF THE INVENTION The form for implementing the 1st characteristic of this invention.

[First Embodiment]

EMBODIMENT OF THE INVENTION Hereinafter, the 1st Embodiment which actualized the 1st characteristic of this invention on the multilayer wiring board is demonstrated in detail based on drawing. 1 is an enlarged cross-sectional view showing a schematic configuration of a multilayer wiring board according to the present embodiment, and FIG. 2 is a plan view of the multilayer wiring board seen from an upper surface side.

As shown in Figs. 1 and 2, the multilayer wiring board 10 of this embodiment is a coreless wiring board formed without including a core board. The multilayer wiring board 10 alternates a plurality of resin insulating layers 20, 21, 22, 23, 24, 25, 26 and 27 mainly composed of the same resin insulating material and a plurality of conductor layers 28 made of copper. It has the wiring laminated part 30 laminated | stacked and multilayered. Each resin insulating layer 20 to 27 is formed using a buildup material mainly composed of a thermosetting epoxy resin.

In the multilayer wiring board 10 of the present embodiment, a plurality of IC chip connection terminals 41 whose connection target is an IC chip (chip component) are connected to the upper surface 31 side (substrate main surface side) of the wiring laminated portion 30. (Chip Component Connection Terminal) and a plurality of Capacitor Connection Terminals 42 (Chip Component Connection Terminal), in which a connection target is a chip capacitor (chip component), are arranged. On the upper surface 31 side of the wiring stacking portion 30, the plurality of IC chip connection terminals 41 are arranged in an array in the chip mounting region 43 formed in the center portion of the substrate. The capacitor connecting terminal 42 is a connecting terminal having a larger area than the IC chip connecting terminal 41 and is disposed on the outer circumferential side of the chip mounting region 43. As shown in Fig. 2, the chip mounting area 43 of the present embodiment is a rectangular chip mounting area 43 having a vertical dimension of X (cm) and a horizontal dimension of Y (cm).

The plurality of IC chip connection terminals 41 and the plurality of capacitor connection terminals 42 are convexly provided on the resin insulating layer 27 of the outermost layer. These IC chip connection terminals 41 and capacitor connection terminals 42 are mainly composed of a copper layer, and the upper and side surfaces of the copper layer are formed of a plating layer 46 (specifically, a nickel-gold plating layer) other than copper. It has a covered structure.

On the other hand, on the lower surface 32 side (substrate back surface side) of the wiring laminated part 30, the some mother board connection terminal 45 which is a motherboard (mother substrate) is arrange | positioned at array shape. These mother board connection terminals 45 are connection terminals larger in area than the IC chip connection terminal 41 and the capacitor connection terminal 42 on the upper surface 31 side.

A plurality of openings 37 are formed in the resin insulating layer 20 of the outermost layer on the lower surface 32 side of the wiring stacking portion 30, and the mother substrate connection terminal (corresponding to the plurality of openings 37) 45) are arranged. Specifically, the mother substrate connecting terminal 45 is disposed in the opening 37 so that the height of the terminal outer surface becomes lower than the surface of the resin insulating layer 20, and the outer peripheral portion of the terminal outer surface is the resin insulating layer of the outermost layer. It is covered by 20. The mother substrate connecting terminal 45 is mainly composed of a copper layer, and has a structure in which only the lower surface of the copper layer exposed in the opening 37 is covered with a plating layer 48 (specifically, a nickel-gold plating layer) other than copper. Have

Via holes 33 and field-via conductors 34 are formed in the resin insulating layers 21 to 27, respectively. Each of the via conductors 34 has a shape of increasing diameter in the same direction (from the lower surface side to the upper surface side in Fig. 1), and each conductor layer 28, IC chip connection terminal 41, and capacitor connection terminal. The 42 and the mother substrate connecting terminal 45 are electrically connected to each other.

The multilayer wiring board 10 of the above structure is produced, for example in the following procedure.

First, a supporting substrate 50 (such as a glass epoxy substrate) having sufficient strength is prepared, and a resin insulating layer 20 to 27 and a conductor layer 28 are built up on the supporting substrate 50 to form a wiring laminate portion. 30 is formed.

In detail, as shown in FIG. 3, the base resin insulating layer 51 is formed by adhering a sheet-like insulating resin substrate made of epoxy resin on the support substrate 50 to form the base substrate 50 and base resin. The base material 52 which consists of the insulating layers 51 is obtained. Then, the laminated metal sheet body 54 is disposed on the upper surface of the base resin insulating layer 51 of the base material 52. Here, by arranging the laminated metal sheet body 54 on the base resin insulating layer 51, adhesiveness is such that the laminated metal sheet body 54 does not peel off from the base resin insulating layer 51 in a subsequent manufacturing process. Secured. The laminated metal sheet body 54 is formed by bringing two copper foils 55 and 56 into close contact with each other in a peelable state. Specifically, the laminated metal sheet body 54 in which the copper foil 55 and the copper foil 56 are arranged is formed through metal plating (for example, chromium plating, nickel plating, titanium plating, or a combination plating thereof).

Next, the sheet-shaped resin insulating layer 20 is disposed on the base 52 so as to surround the laminated metal sheet body 54, and the resin insulating layer 20 is adhered. Here, the resin insulating layer 20 is in close contact with the laminated metal sheet body 54 and in close contact with the base resin insulating layer 51 in the peripheral region of the laminated metal sheet body 54. Seal (see FIG. 4). For example, an opening 37 for exposing a part of the copper foil 55 at a predetermined position of the resin insulating layer 20 is formed by performing laser processing using an excimer laser, a UV laser, a CO ₂ laser, or the like. Thereafter, electroless copper plating is performed to form an entire surface plating layer covering the openings 37 and the resin insulating layer 20.

Then, a plating film for forming a plating resist is laminated on the upper surface of the resin insulating layer 20, and the plating resist is formed on the resin insulating layer 20 by exposing and developing the dry film. Thereafter, electrolytic copper plating is selectively performed in a state where a plating resist is formed to form the metal conductor portion 58 on the copper foil 55 of the laminated metal sheet body 54, and on the resin insulating layer 20. After the conductor layer 28 is formed, the plating resist is peeled off (see FIG. 5). Furthermore, the whole surface plating layer exposed by peeling of a plating resist and covering the resin insulating layer 20 is removed.

A sheet-like resin insulating layer 21 is disposed on the upper surface of the resin insulating layer 20 on which the metal conductor portion 58 and the conductor layer 28 are formed, and the resin insulating layer 21 is attached. For example, the via hole 33 is formed at a predetermined position (upper position of the metal conductor portion 58) of the resin insulating layer 21 by performing laser processing using an excimer laser, a UV laser, a CO ₂ laser, or the like. do. Next, the desmear process which removes the smear in each via hole 33 using etching liquid, such as potassium permanganate solution, is performed. In addition, the desmear process as, for example, in addition to treatment using an etching solution may be performed the processing in a plasma ashing by O ₂ plasma.

After the desmear process, electroless copper plating and electrolytic copper plating are performed according to a conventionally known method, thereby forming a via conductor 34 in each via hole 33. In addition, the conductor layer 28 is pattern-formed on the resin insulating layer 21 by etching by a conventionally well-known method (for example, a semiadditive method) (refer FIG. 6).

The other resin insulating layers 22 to 27 and the conductor layer 28 are also formed by the same method as the resin insulating layer 21 and the conductor layer 28 described above and laminated on the resin insulating layer 21. Going. The via hole 33 is formed by performing laser hole processing on the resin insulating layer 27 of the outermost layer (see FIG. 7). Next, the desmear process which removes the smear in each via hole 33 using etching liquid, such as potassium permanganate solution, is performed. Further, electroless copper plating is performed to form the entire surface plating layer covering the resin insulating layer 27 and the via hole 33 of the resin insulating layer 27.

Then, a plating film for forming a plating resist is laminated on the upper surface of the resin insulating layer 27, and the plating resist is formed on the resin insulating layer 27 by exposing and developing the dry film. Thereafter, electrolytic copper plating is selectively performed in a state where a plating resist is formed (plating layer forming step). As a result, as shown in FIG. 8, the via conductor 34 is formed in the via hole 33 of the resin insulating layer 27, and the IC chip connection terminal 41 and the capacitor connection are formed on the via conductor 34. The product plating layer 61 used as the copper layer of the terminal 42 is formed. In addition, a dummy plating layer 62 is formed around the product plating layer 61. Thereafter, the entire surface plating layer is removed while leaving the product plating layer 61 and the dummy plating layer 62 on the upper surface of the resin insulating layer 27. As the IC chip connecting terminal 41, there are other connecting terminals that are not connected to the inner layer conductor layer, in addition to the connecting terminal connected to the inner layer conductor layer 28 via the via conductor 34. Although only the IC chip connection terminal 41 connected to the via conductor 34 is shown in FIG. 8, the IC chip connection terminal 41 not connected to the via conductor 34 also has a chip mounted on the resin insulating layer 27. It is formed in the region 43.

As shown in Fig. 9, the dummy plating layer 62 of the present embodiment has a formation region (chip mounting region 43) or a capacitor connection terminal of the IC chip connection terminal 41 on the upper surface of the resin insulating layer 27. It forms as a conductor layer of a plain pattern (solid pattern) so that it may cover almost the whole surface except the formation area of (42). Here, the area ratio of the product plating layer 61 (IC chip connection terminal 41 and capacitor connection terminal 42) to the surface of the resin insulating layer 27 (upper surface 31 serving as the substrate main surface) is about 7%. The dummy plating layer 62 is formed so that the area ratio of the whole plating layer which added the dummy plating layer 62 to the product plating layer 61 is 90% or more.

After the above-described plating layer forming step, a heat treatment may be applied to the resin surface of the resin insulating layer 27 of the outermost layer, for example, hot air at 180 ° C from above. When this heat treatment is performed, the resin surface of the exposed resin insulating layer 27 is discolored. On the other hand, the resin surface of the resin insulating layer 27 covered with the dummy plating layer 62 does not discolor. Therefore, for example, when a predetermined pattern shape is formed in the dummy plating layer 62, a difference in color shades matching the pattern shape can be caused on the resin surface. In addition, since the heat treatment at this stage also serves as annealing, there is a merit that the resin insulating layer 27 can be cured and the internal stress applied to the product plating layer 61 can be released.

By carrying out the above build-up process, the laminated metal sheet body 54, the resin insulating layers 20 to 27, the conductor layer 28, the product plating layer 61 and the dummy plating layer 62 are laminated on the base material 52. One wiring laminated body 60 is formed.

Then, by etching the dry film for etching resist formation on the upper surface of the wiring laminated body 60 and exposing and developing the dry film, the etching resist 65 (FIG. 10) so as to cover the surface of the product plating layer 61. (Resist formation step).

After formation of the etching resist 65, the wiring laminated body 60 is cut | disconnected by a dicing apparatus (not shown), and the peripheral area of the part used as the wiring laminated part 30 is removed. By this cutting, the outer edge portion of the laminated metal sheet body 54 sealed with the resin insulating layer 20 is exposed. That is, the adhesion between the base resin insulating layer 51 and the resin insulating layer 20 is eliminated by removing the surrounding area. As a result, the wiring laminated part 30 and the base material 52 are connected only through the laminated metal sheet body 54.

Here, as shown in FIG. 11, the base material 52 is removed from the wiring laminated portion 30 by peeling at the interface of the pair of copper foils 55 and 56 in the laminated metal sheet body 54, and the wiring laminated portion. The copper foil 55 on the lower surface 32 of (30) is exposed (substrate separation process).

Thereafter, the wiring laminated portion 30 is etched to remove the dummy plating layer 62 exposed on the upper surface 31 side of the wiring laminated portion 30 (plating layer removing step). At the same time, the copper foil 55 exposed from the lower surface 32 side of the wiring laminated portion 30 as a whole is removed, and a part of the lower side of the metal conductor portion 58 is removed. As a result, the opening 37 is formed in the resin insulating layer 24, and the metal conductor portion 58 remaining in the opening 37 becomes the mother substrate connecting terminal 45 (see FIG. 12).

In addition, the etching resist 65 formed on the upper surface 31 of the wiring laminated portion 30 is removed. Thereafter, electroless nickel plating and electroless gold plating are sequentially performed on the surface of the IC chip connecting terminal 41, the surface of the capacitor connecting terminal 42, and the surface of the mother substrate connecting terminal 45. As a result, plating layers 46 and 48 are formed on the surfaces of the connection terminals 41, 42 and 45. Through the above steps, the multilayer wiring board 10 of FIG. 1 is manufactured.

In the multilayer wiring board 10 manufactured as described above, the inventors have described the thickness of each product plating layer 61 in the IC chip connection terminal 41 and the capacitor connection terminal 42 formed on the substrate main surface 31 side. Imbalance was measured. The result is shown in FIG. In addition, the thickness imbalance of each product plating layer 61 was measured also in the case of the conventional manufacturing method in which the product plating layer 61 was formed without forming the dummy plating layer 62. The result is shown in FIG. In addition, the thickness imbalance of four measuring places (P1-P4) was measured here.

Specifically, the first measurement point P1 is the product plating layer 61 of the IC chip connection terminal 41 which is not connected to the via conductor 34 in the outer peripheral portion of the chip mounting area 43, and the second measurement point P2 is a product plating layer 61 of the IC chip connection terminal 41 connected to the via conductor 34 in the outer peripheral portion of the chip mounting region 43. The third measuring point P3 is the product plating layer 61 of the IC chip connecting terminal 41 at the center portion of the chip mounting area 43, and the fourth measuring point P4 is the capacitor connecting terminal 42. The product plating layer 61 of. Moreover, about the 1st-3rd measuring point P1-P3, the thickness imbalance is measured with respect to the product plating layer 61 of 60 IC chip connection terminals 41. As shown in FIG. In addition, the thickness imbalance was measured with respect to the product plating layer 61 of 48 capacitor | condenser connection terminals 42 in the 4th measurement location.

As shown in Fig. 14, in the conventional manufacturing method, since the dummy plating layer 62 is not formed, the thickness imbalance of each product plating layer 61 is increased. Specifically, the average value of the plating thickness of the first measurement point P1 was 24.72 µm, and the standard deviation was 2.50. The average value of the plating thickness of the second measurement point P2 was 20.99 µm, and the standard deviation was 5.20. The average value of the plating thickness of the third measurement point P3 was 10.08 µm, and the standard deviation was 2.31. The average value of the plating thickness of the fourth measurement point P4 was 36.58 µm, and the standard deviation was 8.92.

As described above, in each product plating layer 61 (measurement points P1 to P3) serving as the IC chip connection terminal 41, thickness imbalance occurs depending on the presence or absence of the via conductor 34 to be connected. In addition, the product plating layer 61 (measurement point P4) serving as the capacitor connecting terminal 42 is formed on the outer circumferential side of the substrate main surface so that current concentration tends to occur. Therefore, the plating thickness of the product plating layer 61 became relatively thick, and the thickness imbalance also became large.

On the other hand, as shown in FIG. 13, in the manufacturing method of this embodiment, the thickness imbalance of each product plating layer 61 became small. Specifically, the average value of the plating thicknesses of the first measurement sites P1 was 12.85 µm, and the standard deviation was 1.16. The average value of the plating thickness of the second measurement point P2 was 12.51 μm, and the standard deviation was 1.53. The average value of the plating thickness of the third measurement point P3 was 12.90 µm, and the standard deviation was 1.47. The average value of the plating thickness of the fourth measurement point P4 was 12.51 μm, and the standard deviation was 1.21. Thus, by forming the dummy plating layer 62 around the product plating layer 61, the thickness imbalance of each product plating layer 61 was suppressed.

In addition, the present inventors performed the following in order to investigate the relationship between the size of the IC chip mounting area 43 and the thickness imbalance of the product plating layer 61. Here, a plurality of multilayer wiring boards 10 were manufactured by the manufacturing method of the first embodiment by changing the size of the IC chip mounting region 43 (that is, changing the values of X and Y). In addition, the design value of the thickness of the product plating layer 61 in the IC chip connection terminal 41 formed in the board | substrate main surface 31 side was set to Z (micrometer). More specifically, the product plating layer 61 was formed by setting Z = 15 μm. In addition, the area ratio of the dummy plating layer 62 in the dummy plating layer forming region is set within the range of 30% to 100%, and the distance between the product plating layer 61 and the dummy plating layer 62 is 0.1 mm to 10 mm. It set in the range. And the thickness (micrometer) of the product plating layer 61 was measured five points in the corner part and center part of the IC chip mounting area 43, respectively. The standard deviation (?) (Μm) of the measured value of the thickness of the product plating layer 61 at this time was obtained. The results are shown in the graph of FIG. In the graph of FIG. 15, the vertical axis represents the standard deviation σ, and the horizontal axis represents the half length of the diagonal of the IC chip mounting region 43 (in other words, the separation distance between the corner portion and the center portion of the IC chip mounting region 43). It is.

As shown in FIG. 15, in the multilayer wiring board 10 produced by the manufacturing method of the first embodiment, the value of the standard deviation? Is expressed by the following relational expression regardless of the size of the IC chip mounting region 43. It became clear that he was satisfied.

On the other hand, several multilayer wiring boards 10 were manufactured by the conventional manufacturing method which formed only the product plating layer 61, without forming the dummy plating layer 62. FIG. And the thickness (micrometer) of the product plating layer 61 was measured 5 points in the corner part and center part of the IC chip mounting area 43 by the same method, and the standard of the measured value of the thickness of the product plating layer 61 was measured. The deviation (σ) (mu m) was obtained. The results are also shown in the graph of FIG. According to this, in the case of the conventional manufacturing method, it is clear that the value of the standard deviation? Becomes large and the thickness imbalance increases. Therefore, these relations do not satisfy the above relation.

Therefore, according to the 1st Embodiment by the 1st characteristic of this invention, the following effects can be acquired.

(1) In the first embodiment, the product plating layer 61 in addition to the product plating layer 61 serving as the IC chip connection terminal 41 and the capacitor connection terminal 42 on the upper surface 31 of the multilayer wiring board 10. ), A dummy plating layer 62 is formed. In this case, the area ratio of the plating layers 61 and 62 on the upper surface 31 of the multilayer wiring board 10 can be increased, so that the concentration of plating current is avoided and the thickness imbalance of the product plating layer 61 is eliminated. As a result, in the multilayer wiring board 10, the plurality of IC chip connection terminals 41 and the plurality of capacitor connection terminals 42 can be formed to have a uniform thickness. Therefore, by using the multilayer wiring board 10, it is possible to improve the connection reliability of the IC chip, the chip capacitor, and each of the connection terminals 41 and 42.

(2) In the first embodiment, after the etching resist is formed to cover the product plating layer 61 in the resist forming step, the dummy plating layer is removed by etching in the plating layer removing step. In this case, only the product plating layer 61 which becomes each connection terminal 41 and 42 remains on the upper surface of the multilayer wiring board 10. Therefore, the plating layer 46 for improving solder wettability can be reliably formed only on the surface of the product plating layer 61. In addition, since the dummy plating layer 62 is removed, the problem that the IC chip or the chip capacitor is incorrectly connected to the dummy plating layer 62 is also avoided.

(3) In the first embodiment, the plating layer removing step is performed after the substrate separation step. In this case, the upper surface 31 side dummy plating layer 62 of the multilayer wiring board 10 can be removed by etching, and the copper foil 55 on the lower surface 32 side can be removed by etching. Therefore, the multilayer wiring board 10 can be manufactured by the same process number as the conventional manufacturing method, and manufacturing cost can be suppressed low.

(4) In the first embodiment, the area of the product plating layer 61 of the IC chip connecting terminal 41 and the capacitor connecting terminal 42 with respect to the upper surface 31 of the resin insulating layer 27 is about 7%. The area ratio of 61 is relatively small. Therefore, the dummy plating layer 62 having a large area is formed so that the area ratio of the plating layer on the upper surface 31 of the resin insulating layer 27 is 90% or more. In this case, the dummy plating layer 62 is formed so as to have an area ratio of 10 times or more of the product plating layer 61. In this way, concentration of plating current can be reliably avoided, and the product plating layer 61 of each connection terminal 41 and 42 can be formed to a uniform thickness.

Second Embodiment

EMBODIMENT OF THE INVENTION Hereinafter, the 2nd Embodiment which actualized the 1st characteristic of this invention on the multilayer wiring board is demonstrated in detail based on drawing. 16 is an enlarged cross-sectional view showing a schematic configuration of a multilayer wiring board of this embodiment. In the first embodiment, the embodiment is embodied in a coreless wiring board formed without including the core board, but in the present embodiment, the multilayer wiring board having a core board is embodied.

As shown in FIG. 16, the multilayer wiring board 100 of the present embodiment includes a rectangular plate-shaped core board 101 and a first build-up layer 111 formed on the core main surface 102 of the core board 101. And a second build-up layer 112 formed on the core surface 103 of the core substrate 101.

The core substrate 101 of the present embodiment is made of, for example, a resin insulating material (glass epoxy material) formed by impregnating an epoxy resin in a glass cloth as a reinforcing material. The core substrate 101 is formed with a plurality of through hole conductors 106 penetrating through the core main surface 102 and the core surface 103. In addition, the inside of the through-hole conductor 106 is filled with a blocker 107 such as an epoxy resin. In addition, a conductor layer 121 made of copper is formed on the core main surface 102 and the core surface 103 of the core substrate 101, and each conductor layer 121 is electrically connected to the through hole conductor 106. Connected.

The first build-up layer 111 formed on the core main surface 102 of the core substrate 101 has three layers of resin insulating layers 133, 135, and 137 made of a thermosetting resin (epoxy resin) and a conductor layer made of copper. It has a structure in which 122) is alternately laminated. On the upper surface 141 (substrate main surface) of the resin insulating layer 137 of the outermost layer, a plurality of IC chip connection terminals 41 (chip component connection terminals) are arranged in an array shape at the center of the substrate as in the first embodiment. In addition, a plurality of capacitor connection terminals 42 (chip component connection terminals) are disposed outside the IC chip connection terminals 41. These IC chip connection terminals 41 and capacitor connection terminals 42 are mainly composed of a copper layer, and have a structure in which the upper and side surfaces of the copper layer are covered with the plating layer 46. In addition, via holes 33 and field-via conductors 34 are formed in the resin insulating layers 133, 135, and 137, respectively. Each via conductor 34 is electrically connected to the conductor layers 121 and 122 and each of the connection terminals 41 and 42.

The second buildup layer 112 formed on the core surface 103 of the core substrate 101 has a structure substantially the same as that of the first buildup layer 111 described above. That is, the second buildup layer 112 has a structure in which three resin insulating layers 134, 136, and 138 and the conductor layer 122 are alternately stacked. A plurality of mother substrate connecting terminals 45 are formed on the lower surface 142 (substrate back surface) of the resin insulating layer 138 of the outermost layer. These mother substrate connection terminals 45 mainly consist of a copper layer, and have the structure which covered the plating layer 48 under and the side surface of a copper layer. The via holes 33 and the via conductors 34 are also formed in the resin insulating layers 134, 136, and 138. Each via conductor 34 is electrically connected to the conductor layers 121 and 122 and the connection terminal 45.

Next, the manufacturing method of the multilayer wiring board 100 of this embodiment is demonstrated.

First, the copper clad laminated board which copper foil adhered to both surfaces of the base material which consists of glass epoxy is prepared. Then, a punching process is performed using a drill, and a through hole (not shown) penetrating the front and back surfaces of the copper clad laminate is formed in a predetermined position in advance. Then, the through hole conductor 106 is formed in the through hole by performing electroless copper plating and electrolytic copper plating on the inner surface of the through hole of the copper clad laminate. Thereafter, the cavity of the through hole conductor 106 is filled with an insulating resin material (epoxy resin) to form the occluded body 107.

Further, after the electroless copper plating and the electrolytic copper plating, a copper plating layer is formed on the surface of the copper clad laminate including the exposed portion of the occluder 107, and then the copper plating layer and the copper foil are formed by, for example, a subtractive method. Pattern. As a result, as shown in FIG. 17, the core substrate 101 in which the conductor layer 121 and the through-hole conductor 106 were formed is obtained.

Then, by performing the same build-up process as in the first embodiment, the first build-up layer 111 is formed on the core main surface 102 of the core substrate 101 and the core of the core substrate 101 is formed. The second buildup layer 112 is also formed on the 103. At this time, the product plating layer 61 serving as each of the connection terminals 41 and 42 is formed on the upper surface 141 of the resin insulating layer 137 that is the outermost layer of the first build-up layer 111. A dummy plating layer 62 is formed around 61 (see FIG. 18). In this step, the product plating layer 61 serving as the mother substrate connecting terminal 45 is formed on the lower surface 142 of the resin insulating layer 138 serving as the outermost layer of the second build-up layer 112. The dummy plating layer 62 is formed also around the product plating layer 61 (refer FIG. 18).

Thereafter, the dry film for etching resist formation is laminated on the surface of the first build-up layer 111 (upper surface 141 of the resin insulating layer 137), and the product plating layer (exposed and developed) is subjected to exposure and development. An etching resist 65 covering the surface of 61 is formed (see FIG. 19). In addition, a dry film for forming an etching resist is laminated on the surface of the second build-up layer 112 (the lower surface 142 of the resin insulating layer 138), and the product plating layer 61 is exposed and developed for the dry film. The etching resist 65 which covers the surface of) is formed (refer FIG. 19).

By etching after the etching resist 65 is formed, the dummy plating layer 62 exposed on the surfaces of the respective buildup layers 111 and 112 is removed, and then the etching resist 65 is removed. Electroless nickel plating and electroless gold plating are sequentially performed on the surface of the IC chip connecting terminal 41, the surface of the capacitor connecting terminal 42, and the surface of the mother substrate connecting terminal 45. As a result, plating layers 46 and 48 are formed on the surfaces of the connection terminals 41, 42 and 45. By passing through the above steps, the multilayer wiring board 100 of FIG. 16 is manufactured.

Therefore, according to the second embodiment according to the first aspect of the present invention, the following effects can be obtained.

(1) Also in the second embodiment, the product plating layer 61 in addition to the product plating layer 61 serving as the IC chip connection terminal 41 and the capacitor connection terminal 42 on the upper surface 141 of the resin insulating layer 137. ), A dummy plating layer 62 is formed. In this case, the area ratio of the plating layers 61 and 62 on the upper surface 141 of the resin insulating layer 137 can be increased, so that the concentration of the plating current is avoided and the thickness imbalance of the product plating layer 61 is eliminated. As a result, in the multilayer wiring board 100, the plurality of IC chip connection terminals 41 and the plurality of capacitor connection terminals 42 can be formed to have a uniform thickness. Therefore, by using the multilayer wiring board 100, it is possible to improve the connection reliability between the chip components of the IC chip and the chip capacitor and the connection terminals 41 and 42.

(2) In the second embodiment, the dummy plating layer 62 is formed around the product plating layer 61 serving as the mother substrate connecting terminal 45 on the lower surface 142 of the resin insulating layer 138. In this way, concentration of plating current is avoided and thickness unevenness of the product plating layer 61 of each connection terminal 45 can be suppressed. As a result, in the multilayer wiring board 100, the plurality of mother substrate connection terminals 45 can be formed to have a uniform thickness, so that the connection reliability with the mother substrate connection terminals 45 can be improved.

In addition, 1st and 2nd embodiment of this invention can also be changed as follows.

In each of the above embodiments, the dummy plating layer 62 is etched away, but the multilayer wiring boards 10 and 100 can be completed with the dummy plating layer 62 left. In this case, since the dummy plating layer 62 is not electrically connected to the conductor layers 28 and 122 on the inner layer side, the electrical performance of the multilayer wiring boards 10 and 100 deteriorates even when the dummy plating layer 62 is present. It doesn't work. In addition, in the multilayer wiring boards 10 and 100, since the dummy plating layer 62 having a relatively large area is provided, heat dissipation can be improved. In the multilayer wiring board 10 having no core as in the multilayer wiring board 10 of the first embodiment, the substrate strength is weakened. However, the substrate strength can be increased by forming the dummy plating layer 62. As a result, the warpage of the multilayer wiring board 10 can be suppressed.

In each of the above embodiments, the product plating layer 61 serving as the capacitor connecting terminal 42 in addition to the product plating layer 61 serving as the IC chip connecting terminal 41 on the upper surfaces 31 and 141 of the multilayer wiring boards 10 and 100. Although the dummy plating layer 62 was formed around the periphery, it is not limited to this. For example, even if the capacitor connection terminal 42 has a thickness imbalance, the chip capacitor can be connected, and the thickness imbalance of the connection terminal is more problematic than the capacitor connection terminal 42 at the IC chip connection terminal 41. Therefore, in the plating layer forming step, the dummy plating layer 62 is formed only around the product plating layer 61 serving as the IC chip connection terminal 41, and the dummy plating layer 62 is formed around the product plating layer 61 serving as the capacitor connecting terminal 42. The plating layer 62 is not formed. In this way, thickness unbalance of the IC chip connection terminal 41 can be suppressed, and connection reliability with the IC chip can be sufficiently secured.

In each of the above embodiments, the dummy plating layer 62 formed in the plating layer forming step was a solid pattern without a mesh, but is not limited thereto. For example, a dummy plated layer 62 on a plane having a mesh may be formed. Thus, by forming the plain-shaped dummy plating layer 62 which has a mesh, the area ratio of a plating layer can be adjusted more correctly.

In each of the above embodiments, each of the connection terminals 41 and 42 having the same thickness (thickness of about 10 μm) as the inner conductor layers 28 and 122 is provided, but is not limited thereto. For example, it is possible to form a post-shaped connecting terminal (post electrode) that is thicker than the inner layer side conductor layers 28 and 122, for example, having a thickness of 30 μm or more. Even in the case where a relatively thick connection terminal is formed in this way, the connection terminals can be formed to have a uniform thickness by forming the dummy plating layer 62.

Next, the technical idea grasped | ascertained by each embodiment mentioned above besides the technical idea described in the claim is enumerated below.

(1) The multi-layered wiring board according to the means 1, wherein a plurality of IC chip connection terminals capable of connecting IC chips and a plurality of capacitor connection terminals capable of connecting chip capacitors are provided on the substrate main surface as the chip component connection terminals. Manufacturing method.

(2) The method for producing a multilayer wiring board according to means 1, wherein the dummy plating layer is a plain pattern.

(3) The method for producing a multilayer wiring board according to means 1, wherein the dummy plating layer is a plane pattern having a mesh.

(4) The method for producing a multilayer wiring board according to means 1, wherein the dummy plating layer has a pattern corresponding to the shape and size of the adjacent product plating layer.

(5) The method for producing a multilayer wiring board according to means 1, wherein in the plating layer forming step, field vias connected to the inner layer side conductor layer and the chip component connection terminal are formed simultaneously with the plating layer.

(6) The method for producing a multilayer wiring board according to means 1, wherein in the plating layer forming step, the dummy plating layer is formed so that the dummy plating layer has an area ratio of 10 times or more of the product plating layer.

(7) The method for producing a multilayer wiring board according to means 1, wherein the product plating layer and the dummy plating layer are formed of copper plating.

(8) The method for producing a multilayer wiring board according to means 1, wherein the resin insulating layer is formed using a buildup material mainly composed of a thermosetting resin.

[Mode for Carrying Out the Second Aspect of the Present Invention]

[Third Embodiment]

The third embodiment in which the second aspect of the invention is embodied on a multilayer wiring board will be described in detail with reference to the drawings. 20 is an enlarged cross-sectional view showing a schematic configuration of the multilayer wiring board of the present embodiment, and FIG. 21 is a plan view of the multilayer wiring board as seen from the upper surface side.

As shown in Figs. 20 and 21, the multilayer wiring board 10 of this embodiment is a coreless wiring board formed without including the core board.

The basic configuration and the creation procedure of this multilayer wiring board are the same as those of the first embodiment. Therefore, only the structure and creation procedure different from 1st Embodiment are described below.

As shown in Fig. 21, in the multilayer wiring board 10, the outermost layer of the resin insulating layer 27 exposed from the upper surface 31 side has the recognition marks 71 and 72 formed by the difference in color shade of the resin surface. , 73). In this embodiment, a mark 71 of a letter indicating a company name or the like and a mark 72 of a number indicating a manufacturing number are formed on the outer edge portion (the upper edge portion in the upper left in Fig. 21) as the recognition mark, and the chip mounting area. An IC chip positioning mark 73 is formed in the vicinity of the corner portion of 43. In addition, the outermost resin insulating layer 27 is provided with a pattern 74 formed by a difference in color shade of the resin surface so that the mesh pattern is regularly arranged. This pattern 74 is formed on almost the entire surface of the resin insulating layer 27 exposed from the upper surface 31 side.

In addition, in the multilayer wiring board 10, the positioning mark 76 which exposes the conductor portion 75 to the substrate edge portion (the edge portion at the upper right side of the substrate in FIG. 21) which becomes the outer edge portion on the upper surface 31 side. Equipped with. In the present embodiment, the conductor portion 75 of the positioning mark 76 is formed by plating on the resin insulating layer 27 of the outermost layer. This positioning mark 76 is recognized by detecting a difference in light reflectance between the resin surface of the resin insulating layer 27 of the outermost layer and the surface of the conductor portion 75 by a detection device (not shown).

As described above, an exemplary manufacturing procedure of the multilayer wiring board 10 having the above configuration is basically the same as that of the first embodiment. Therefore, only exemplary production procedures different from the first embodiment are described below.

The same procedure as in the first embodiment is performed until the plating layer forming step. As a result, as shown in FIG. 22, the via conductor 34 is formed in the via hole 33 of the resin insulating layer 27, and the IC chip connecting terminal 41 and the capacitor connection are formed on the via conductor 34. The product plating layer 61 used as the copper layer of the terminal 42 is formed. Furthermore, the product plating layer 61 used as the conductor part 75 of the positioning mark 76 is formed in the position used as a board | substrate edge part. In addition, a dummy plating layer 62 is formed around each product plating layer 61. Thereafter, the entire surface plating layer is removed while leaving the product plating layer 61 and the dummy plating layer 62 on the upper surface of the resin insulating layer 27.

As shown in Fig. 23, the dummy plating layer 62 of the present embodiment has a formation region (chip mounting region 43) or a capacitor connection terminal of the IC chip connection terminal 41 on the upper surface of the resin insulating layer 27. It is formed as a conductor layer of a plain pattern so as to cover almost the whole surface except the formation area of (42). The dummy plating layer 62 is formed with a mesh 63 which is a mesh-shaped punching pattern corresponding to the pattern 74. Further, in the dummy plating layer 62, punching patterns 64 and 65a corresponding to the recognition mark 71 of the character or the recognition mark 72 of the number are formed at the position of the outer edge portion, and the chip mounting area 43 is formed. A punching pattern 66 suitable for the positioning recognition mark 73 is formed at a position near the edge of the.

After the plating layer forming step, a heat treatment is applied to the resin surface of the resin insulating layer 27 of the outermost layer by applying hot air 68 at 180 ° C. from above, for example (a recognition mark forming step). . By this heat treatment, the mesh surface 63 or the punching patterns 64 to 66 are formed in the dummy plating layer 62 to discolor the resin surface of the resin insulating layer 27 exposed. In addition, the heat treatment here serves as annealing to cure the resin insulating layer 27 and to release the internal stress applied to the product plating layer 61.

By carrying out the above build-up process, the laminated metal sheet body 54, the resin insulating layers 20 to 27, the conductor layer 28, the product plating layer 61 and the dummy plating layer 62 are laminated on the base material 52. One wiring laminated body 60 is formed.

Then, an etching resist forming dry film is laminated on the upper surface of the wiring laminate 60, and the etching resist 69 is covered so as to cover the surface of the product plating layer 61 by exposing and developing the dry film. Reference).

After formation of the etching resist 69, the wiring laminated body 60 is cut | disconnected with a dicing apparatus (not shown), and the peripheral region of the part used as the wiring laminated part 30 is removed. By this cutting, the outer edge portion of the laminated metal sheet body 54 sealed with the resin insulating layer 20 is exposed. That is, the adhesion between the base resin insulating layer 51 and the resin insulating layer 20 is eliminated by removing the surrounding area. As a result, the wiring laminated part 30 and the base material 52 are connected only through the laminated metal sheet body 54.

Here, as shown in FIG. 26, the base material 52 is removed from the wiring laminated portion 30 by peeling at the interface of the pair of copper foils 55 and 56 in the laminated metal sheet body 54, and the wiring laminated portion. The copper foil 55 on the lower surface 32 of (30) is exposed (substrate separation process).

Thereafter, the wiring laminated portion 30 is etched to remove the dummy plating layer 62 exposed on the upper surface 31 side of the wiring laminated portion 30 (dummy plating layer removing step). At the same time, the copper foil 55 exposed on the lower surface 32 side of the wiring laminated portion 30 as a whole is removed as well as the lower portion of the metal conductor portion 58 is removed. As a result, the opening 37 is formed in the resin insulating layer 24, and the metal conductor portion 58 remaining in the opening 37 becomes the mother substrate connecting terminal 45 (see FIG. 27). The surface of the resin insulating layer 27 which is not discolored is exposed on the upper surface 31 of the wiring laminated portion 30 (resin insulating layer 27) by etching away the dummy plating layer 62. As a result, a difference in color shade occurs depending on the shape of the mesh 63 or the punching patterns 64 to 66 of the dummy plating layer 62 on the surface of the resin. The pattern 74 is formed.

In addition, the etching resist 69 formed on the upper surface 31 of the wiring stacking portion 30 is removed. Thereafter, electroless nickel plating and electroless gold plating are sequentially performed on the surface of the IC chip connecting terminal 41, the surface of the capacitor connecting terminal 42, and the surface of the mother substrate connecting terminal 45. As a result, plating layers 46 and 48 are formed on the surfaces of the connection terminals 41, 42 and 45. Through the above steps, the multilayer wiring board 10 of FIG. 20 is manufactured.

Therefore, according to the 3rd Embodiment by the 2nd characteristic of this invention, the following effects can be acquired.

(1) In the multilayer wiring board 10 of the third embodiment, recognition marks 71 to 73 are formed on the upper surface 31 on which the IC chip is mounted due to the difference in color shade of the resin surface. In this case, since the recognition marks 71 to 73 can be recognized without forming the conductor layer or the opening as in the prior art, the manufacturing cost of the multilayer wiring board 10 can be reduced.

(2) In the multilayer wiring board 10 of the third embodiment, the conductor portion 75 is exposed at the outer edge portion of the upper surface 31 side, and the resin surface of the resin insulating layer 27 of the outermost layer is exposed. A positioning mark 76 further recognized by the difference in light reflectance on the surface of the conductor portion 75 is further provided. Thus, the recognition marks 71-73 by the difference in color shade and the positioning mark 76 by the difference in light reflectivity can be formed according to a use. In addition, the formation position of the positioning mark 76 can be recognized quickly and reliably by the difference in light reflectivity. Therefore, the multilayer wiring board 10 can be positioned more accurately. In addition, the recognition mark 73 is a mark for positioning an IC chip, and is formed in the vicinity of the chip mounting area 43. This recognition mark 73 is formed by the difference in color shade, and the conductor part 75 is not formed. Therefore, the problem that an IC chip is incorrectly connected to the conductor part 75 can be avoided.

(3) In the multilayer wiring board 10 of the third embodiment, the mesh pattern 74 formed by the difference in color shade of the resin surface in the resin insulating layer 27 of the outermost layer is provided. Since the pattern 74 is formed on the entire upper surface of the resin insulating layer 27 regularly, the design of the multilayer wiring board 10 can be improved.

(4) In the third embodiment, heat treatment is performed to discolor the resin surface of the resin insulating layer 27 in order to form the recognition marks 71 to 73. The heat treatment also serves as annealing of the resin insulating layer 27. . In this case, the conventional annealing process and the recognition mark forming process need not be performed by separate heat treatment, so that the manufacturing cost of the multilayer wiring board 10 can be reduced.

(5) In the third embodiment, the dummy plating layer removing step is performed after the substrate separation step. In this case, the dummy plating layer 62 on the upper surface 31 side of the multilayer wiring substrate 10 can be removed by etching, and the copper foil 55 on the lower surface 32 side can be removed by etching. In this way, the multilayer wiring board 10 can be manufactured with the same number of steps as the conventional manufacturing method, and the manufacturing cost can be kept low.

(6) Third Embodiment In this embodiment, in addition to the product plating layer 61 serving as the IC chip connecting terminal 41 and the capacitor connecting terminal 42 on the upper surface 31 of the multilayer wiring board 10, the product plating layer ( The dummy plating layer 62 is formed around the 61. By doing in this way, the area ratio of the plating layers 61 and 62 in the upper surface 31 of the multilayer wiring board 10 can be increased. Therefore, current concentration at the time of plating is avoided, and the thickness imbalance of the product plating layer 61 is eliminated. As a result, in the multilayer wiring board 10, the plurality of IC chip connection terminals 41 and the plurality of capacitor connection terminals 42 can be formed to have a uniform thickness. Therefore, by using the multilayer wiring board 10, it is possible to improve the connection reliability between the chip components of the IC chip and the chip capacitor and the connection terminals 41 and 42.

[Fourth Embodiment]

A fourth embodiment in which the second aspect of the invention is embodied on a multilayer wiring board will be described in detail with reference to the drawings. Fig. 28 is an enlarged cross sectional view showing a schematic configuration of a multilayer wiring board of this embodiment. In the third embodiment, the embodiment is embodied in a coreless wiring board formed without including the core board. In this embodiment, the embodiment is embodied in a multilayer wiring board having a core board. The structure of this multilayer wiring board and its manufacturing method are basically the same as those of the second embodiment. Therefore, only the features different from the second embodiment are described below.

Also in the multilayer wiring board 100 of the fourth embodiment, the resin insulating layer 137 of the outermost layer exposed from the upper surface side of the first build-up layer 111 is made of the same resin as the multilayer wiring board 10 of the third embodiment. Recognition marks 71, 72, and 73 (see Fig. 21) formed by the difference in color shade of the surface are formed. Moreover, the mesh pattern 74 formed by the difference of the color shade of the resin surface is formed in the resin insulating layer 137 of outermost layer.

The mesh pattern 74 formed by the difference in color shade of the resin surface is also formed in the resin insulating layer 138 of the outermost layer exposed on the lower surface side of the second build-up layer 112. In the multilayer wiring board 100, the mark 71 of the letter indicating the company name or the mark 72 of the number indicating the manufacturing number among the recognition marks 71, 72, and 73 are formed of the first build-up layer 111. It may be formed on the lower surface side of the second build-up layer 112 instead of the upper surface side.

Next, the manufacturing method of the multilayer wiring board 100 of 4th Embodiment is demonstrated. As described above, the manufacture of the multilayer wiring board 100 is basically the same as that of the second embodiment. Therefore, only the process different from 2nd Embodiment is described below.

The same procedure as in the second embodiment is performed until the step of forming the dummy plating layer 62 (see FIG. 29). In addition, the product plating layer 61 serving as the mother substrate connecting terminal 45 is formed on the lower surface 142 of the resin insulating layer 138 serving as the outermost layer of the second build-up layer 112, and the product plating layer 61 thereof. ), A dummy plating layer 62 is also formed (see Fig. 29).

Here, a mesh 63 corresponding to the pattern 74 is formed on the dummy plating layer 62 formed on the upper surface 141 of the resin insulating layer 137, and punching corresponding to each recognition mark 71 to 73 is performed. Patterns 64? 66 (see Fig. 23) are formed. In addition, a mesh 63 corresponding to the pattern 74 is formed on the dummy plating layer 62 formed on the lower surface 142 of the resin insulating layer 138.

After the formation of the plating layers 61 and 62, heat treatment is applied to the resin surface of the resin insulating layer 137, which is the outermost layer of the first build-up layer 111, to apply hot air 68 from above (see FIG. 30). ). By the heat treatment, the mesh surface 63 and the punching patterns 64 to 66 are formed in the dummy plating layer 62 to discolor the resin surface of the resin insulating layer 137 exposed. At the same time, a heat treatment is applied to the resin surface of the resin insulating layer 138 serving as the outermost layer of the second build-up layer 112 to apply hot air 68 from below (see FIG. 31). By this heat treatment, the mesh surface 63 is formed on the dummy plating layer 62 to discolor the resin surface of the resin insulating layer 138 that is exposed.

Thereafter, the dry film for etching resist formation is laminated on the top surface 141 of the resin insulating layer 137 in the first build-up layer 111, and the product plating layer 61 is exposed and developed for the dry film. The etching resist 69 which covers the surface of () is formed (refer FIG. 32). The product plating layer 61 is formed by laminating a dry film for forming an etching resist on the lower surface 142 of the resin insulating layer 138 in the second build-up layer 112 and exposing and developing the dry film. An etching resist 69 is formed to cover the surface of the film (see FIG. 32).

By etching after the etching resist 69 is formed, the dummy plating layer 62 exposed on the surfaces of the build-up layers 111 and 112 is removed, and then the etching resist 69 is removed. At this time, the surface of the resin insulating layer 137 which is not discolored is exposed on the upper surface 141 of the first build-up layer 111 by removing the dummy plating layer 62, and the lower surface of the second build-up layer 112 is exposed. The surface of the resin insulating layer 138 which is not discolored is also exposed at 142. As a result, a difference in color shades occurs on the resin surface of the resin insulating layer 137 depending on the shape of the mesh 63 or the punching patterns 64 to 66 of the dummy plating layer 62. 71? 73) and a mesh pattern 74 are formed. In addition, a difference in color shade occurs depending on the shape of the mesh 63 of the dummy plating layer 62 on the resin surface of the resin insulating layer 138, and a mesh pattern 74 is formed by the difference in shade.

Thereafter, electroless nickel plating and electroless gold plating are sequentially performed on the surface of the IC chip connecting terminal 41, the surface of the capacitor connecting terminal 42, and the surface of the mother substrate connecting terminal 45. As a result, plating layers 46 and 48 are formed on the surfaces of the connection terminals 41, 42 and 45. Through the above steps, the multilayer wiring board 100 of FIG. 17 is manufactured.

Therefore, according to the fourth embodiment according to the second aspect of the present invention, the following effects can be obtained.

(1) In the multilayer wiring board 100 of the fourth embodiment, the recognition marks 71 to 73 are formed on the upper surface 141 of the first build-up layer 111 on which the IC chip is mounted due to the difference in color shade of the resin surface. Is formed. In this case, since the recognition marks 71 to 73 can be recognized without forming the conductor layer or the opening as in the prior art, the manufacturing cost of the multilayer wiring board 100 can be reduced.

(2) In the multilayer wiring board 100 of the fourth embodiment, in addition to the upper surface 141 of the first build-up layer 111, the lower surface 142 of the second build-up layer 112 also has a difference in color shade of the resin surface. Thus, a mesh pattern 74 is formed. By doing in this way, the design of the multilayer wiring board 100 can fully be improved.

In addition, each of 3rd and 4th embodiment of this invention can also be changed as follows.

In the third and fourth embodiments, the dummy plating layer 62 is disposed on the surfaces of the resin insulating layers 27, 137, and 138 so as to cover almost the entire surface except for the formation areas of the connection terminals 41, 42, and 45. Although formed, it is not limited thereto. For example, the dummy plating layer 62 may be formed only in the region where the recognition marks 71 to 73 are formed. However, in the case of forming the plain-plated dummy plating layer 62 having a large area as in the third and fourth embodiments, the thickness imbalance of the product plating layer 61 serving as the connection terminals 41, 42, and 45 can be suppressed. Can be. In this case, the pattern 74 can be formed on the entire surface of the substrate by forming the mesh 63 on the dummy plating layer 62. The pattern 74 may be a pattern other than the mesh shape, for example, a pattern in which circles, polygonal patterns, floral patterns, etc. are regularly arranged.

In the third and fourth embodiments, the recognition mark 71 indicating the company name or the like and the recognition mark 72 indicating the manufacturing number are provided at the outer edges of the upper surfaces 31 and 141 of the multilayer wiring boards 10 and 100. Although formed, the formation position of these recognition marks 71 and 72 can be changed suitably. For example, a recognition mark 72 indicating a manufacturing number may be formed in the vicinity of the chip mounting area 43. In addition, when the pattern 74 is not formed, the recognition mark 71 which shows a company name etc. can also be formed using the whole exposed surface of the resin insulating layers 27 and 137. FIG. These recognition marks 71 and 72 are formed by the difference in the color shade of the resin surface. Therefore, even when the respective recognition marks 71 and 72 are formed in the vicinity of each connection terminal 41 and 42 or the positioning mark 76, the connection and positioning of each connection terminal 41 and 42 is used. The detection of the mark 76 is not affected.

In the multilayer wiring board 10 of the third embodiment, the positioning mark 76 recognized on the surface of the resin insulating layer 27 serving as the outermost layer by the difference in light reflectance between the resin surface and the surface of the conductor portion 75. ), But is not limited thereto. For example, the conductor portion 75 is formed on the surface of the resin insulating layer 26 of the second layer, and the opening portion for exposing the surface of the conductor portion 75 is formed on the resin insulating layer 27 of the outermost layer. It is also possible to form the positioning mark 76. Even in this way, the positioning mark 76 can be recognized by the difference in the light reflectance between the resin surface and the conductor portion 75 surface.

In each of the first to fourth embodiments, an IC chip connecting terminal 41 and a capacitor connecting terminal 42 are provided on the upper surfaces 31 and 141 of the multilayer wiring boards 10 and 100 as chip component connecting terminals. Although the capacitor connecting terminal 42 is omitted, only the IC chip connecting terminal 41 may be formed. In addition, on the upper surfaces 31 and 141 of the multilayer wiring boards 10 and 100, in addition to the IC chip connecting terminal 41 and the capacitor connecting terminal 42, other chip component connecting terminals for mounting chip components such as chip inductors are provided. It may be.

In each of the first to fourth embodiments, the product plating layer 61 and the dummy plating layer 62 are formed of copper plating, but the product plating layer 61 and the dummy plating layer 62 are formed by other plating such as tin plating or nickel plating. May be formed. However, when the product plating layer 61 and the dummy plating layer 62 are formed by copper plating, the electrical resistance of the IC chip connection terminal 41 and the capacitor connection terminal 42 can be reduced to be practically preferable.

Next, the technical idea grasped | ascertained by each of the 3rd and 4th embodiment mentioned above other than the technical idea described in the claim is enumerated below.

(1) Means 2, wherein the recognition mark is a positioning mark.

(2) The method for producing a multilayer wiring board according to means 3, wherein the product plating layer and the dummy plating layer are formed of copper plating.

(3) The method for producing a multilayer wiring board according to means 3, wherein the recognition mark forming step also serves as annealing.

(4) The method for producing a multilayer wiring board according to means 3, wherein the heat treatment in the recognition mark forming step is a process of blowing hot air on the exposed surface of the resin insulating layer.

(5) The method for producing a multilayer wiring board according to means 3, wherein the resin insulating layer is formed using a buildup material mainly composed of a thermosetting resin.

(6) A method of manufacturing the multilayer wiring board according to the means 2, comprising: a laminating step of laminating the plurality of resin insulating layers and the plurality of conductor layers on a support substrate through metal foil, and the outermost layer exposed from the main surface of the substrate. A plating layer forming step of forming a product plating layer constituting the plurality of chip component connection terminals on the surface of the resin insulating layer of the resin layer and forming a dummy plating layer having a shape corresponding to the recognition mark, and the resin insulating layer of the outermost layer A heat-treatment process to form a recognition mark for discoloring the surface of the resin insulating layer of the outermost layer and performing annealing, a resist forming step of forming an etching resist to cover the product plating layer on the main surface of the substrate, and the metal foil A substrate separation step of separating the support substrate at an interface to expose the metal foil on the bottom surface of the substrate; And a removing step of removing the dummy plating layer exposed at the side by etching and removing the metal foil exposed at the bottom surface of the substrate by etching.

10,100-Multilayer Wiring Substrates 20? 27,133? 138-Resin Insulation Layer
28,122-Conductor layer 31,141-Upper surface as substrate main surface
32,142-Bottom surface as substrate
41-IC chip connection terminal as chip component connection terminal
42-Capacitor connection terminal as chip component connection terminal
52-Support base 55-Copper foil as metal foil
61-Product Plating Layer 62-Dummy Plating Layer
65-Etch Resist 69-Etch Resist
71? 73-Recognition pattern 74-Pattern
75-conductor part 76-positioning mark

Claims (10)

It has a board | substrate main surface 31 and 141, and board | substrate back surface 32 and 142, Comprising: It laminated | stacked the some resin insulating layer 20-27, 133-138, and the some conductor layer 28, 122, As a manufacturing method of the multilayer wiring boards 10 and 100 in which the chip component connection terminals 41 and 42 which can connect a chip component are arrange | positioned on the said board main surface 31 and 141,
On the surface of the resin insulating layers 27 and 137 of the outermost layer exposed from the substrate main surfaces 31 and 141, a product plating layer 61 serving as the plurality of chip component connection terminals 41 and 42 is formed. And a plating layer forming step of forming a dummy plating layer (62) around the product plating layer (61).
The method according to claim 1,
A resist forming step of forming an etching resist 65 to cover the product plating layer 61 on the substrate main surfaces 31 and 141;
And a plating layer removing step of removing the dummy plating layer (62) exposed on the substrate main surface (31, 141) side by etching.
The method according to claim 1 or 2,
In the plating layer forming step, the dummy plating layer 62 is formed such that the area ratio of the plating layers 61 and 62 to the surface area of the substrate main surfaces 31 and 141 is 60% or more and 95% or less. Method of manufacturing a substrate.
The method according to claim 2,
A lamination step of laminating the plurality of resin insulating layers 20 to 27 and the plurality of conductor layers 28 on the support base 52 through the metal foil 55;
A substrate separation process of separating the metal foil 55 and the support base 52 to expose the metal foil 55 on the back surface 32 of the substrate,
Performing the plating layer removal step after the substrate separation step to remove the dummy plating layer 62 on the substrate main surface 31 side by etching and to remove the metal foil 55 on the substrate back side 32 by etching. A method of manufacturing a multilayer wiring board, characterized in that.
The method according to claim 1 or 2,
In the plating layer forming process, when the area ratio of the dummy plating layer 62 to 30% or more and 100% or less occupies in the dummy plating layer forming region defined by the outer edge of the dummy plating layer 62, the product plating layer 61 And the dummy plating layer (62) so that the distance between the dummy plating layer (62) and the dummy plating layer (62) is 0.1 mm or more and 10 mm or less.
The method according to claim 5,
The plurality of chip component connection terminals 41 are a plurality of IC chip connection terminals 41 that can connect an IC chip as the chip component, and the rectangular chip formed by arranging the plurality of IC chip connection terminals 41 in an array form. The vertical dimension of the chip mounting area 43 is X (cm) and the horizontal dimension is Y (cm), and the design value of the thickness of the product plating layer 61 in the plurality of IC chip connection terminals 41 is Z. (Μm), the standard deviation (?) (Μm) of the measured value of the thickness of the product plating layer 61 is expressed by the following formula.

It has a board | substrate main surface 31 and 141, and board | substrate back surface 32 and 142, Comprising: It laminated | stacked the some resin insulating layer 20-27, 133-138, and the some conductor layer 28, 122, As a multilayer wiring board in which a plurality of chip component connection terminals 41 and 42 that can connect chip components are disposed on the substrate main surfaces 31 and 141,
The multilayer resin layer characterized in that the resin insulating layers 27 and 137 of the outermost layer exposed from the substrate main surfaces 31 and 141 are provided with recognition marks 71 to 73 formed by the difference in color shade of the resin surface. Wiring board.
The method of claim 7,
It is made by exposing the conductor portion 75 at the outer edge portion of the substrate main surface 31 side, the difference in the light reflectance between the resin surface of the resin insulating layer 27 of the outermost layer and the surface of the conductor portion 75. And a positioning mark 76 recognized by the multilayer wiring board.
The method according to claim 7 or 8,
In the resin insulating layers 27 and 137 of the outermost layer exposed from the substrate main surfaces 31 and 141, patterns 74 formed by the difference in color shade of the resin surface, and the patterns of predetermined patterns are regularly arranged. Multi-layered wiring board further comprising).
A method of manufacturing the multilayer wiring board of claim 7,
On the surface of the resin insulating layers 27 and 137 of the outermost layer exposed from the substrate main surfaces 31 and 141, the product plating layer 61 serving as the plurality of chip component connection terminals is formed and the recognition mark 71 is formed. A plating layer forming step of forming a dummy plating layer 62 having a shape corresponding to? 73);
A recognition mark forming process of discoloring the surface of the resin insulating layers 27 and 137 of the outermost layer by heat-treating the resin insulating layers 27 and 137 of the outermost layer;
And forming a etching resist 69 to cover the product plating layer 61 on the substrate main surfaces 31 and 141, and then removing the dummy plating layer 62 by etching. A method of manufacturing a multilayer wiring board.

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