TWI412302B - Intermediate multilayer wiring board product, and method for manufacturing multilayer wiring board - Google Patents

Abstract

An intermediate multilayer wiring board product includes: a stack of a plurality of resin insulating layers, a first conductor layer, and a second conductor layer. The stack includes: a product forming region comprising a plurality of product portions arranged along a major surface of the stack, each of the plurality of product portions to become a product of the multilayer wiring board; and a frame portion surrounding the product forming region. The first conductor layer is formed on at least one of the plurality of resin insulating layers within each of the plurality of product portions. The second conductor layer is formed on at least one of the plurality of resin insulating layers within the frame portion. The frame portion has a plurality of cuts penetrating the frame portion in a thickness direction thereof, the plurality of cuts being arranged at substantially equal intervals.

Description

Intermediate multilayer wiring board product and method of manufacturing multilayer wiring board

The present application is based on and claims the priority of the Japanese Patent Application No. 2008-138885, filed on May 28, 2008, and the Japanese Patent Application No. 2008-142667, filed on May 30, 2008. This article is incorporated herein by reference in its entirety.

The present invention relates to an intermediate multilayer wiring board product (that is, a method of manufacturing an intermediate product of a multilayer wiring board, or an intermediate product of a multilayer wiring board), including a product forming region in which a plurality of product portions are arranged along a plane direction And a frame portion surrounding the article forming region, and a manufacturing method for obtaining a multilayer wiring board from an intermediate product of the multilayer wiring board.

Regarding the technology for efficiently manufacturing wiring boards, a plurality of wiring board products are obtained from one intermediate wiring board product. Such an intermediate article generally comprises: a product forming zone in which a plurality of article portions to be articles are disposed along a planar direction; and a frame portion surrounding the article forming region. The product side conductor layer is formed on the surface of the product portion to be the product, but no conductor layer is formed on the surface of the frame portion which does not become the product. In recent years, a conductor layer (frame side conductor layer) formed by plating is provided on the surface of the frame portion in a solid pattern in order to suppress warping or warpage. Further, another wiring board includes a frame side conductor layer having a mesh pattern instead of a solid pattern (for example, refer to JP-A-2007-180212).

Regarding the intermediate product of the wiring board, the intermediate multilayer wiring board product has been put into practical use. The intermediate multilayer wiring board article includes a core board and a buildup layer formed on each of the front and back sides of the core board. In the intermediate multilayer wiring board product, for example, a resin sheet (such as a glass epoxy board or the like) made by impregnating a resin with a reinforcing fiber is used as the core sheet. The accumulation layer is formed by alternately stacking a resin insulating layer and a conductor layer on each of the front and back surfaces of the core board, thereby utilizing the rigidity of the core board. Briefly, the core panel reinforces the intermediate multilayer wiring board article and has a thickness that is much thicker than the accumulation layer. The intermediate article includes an interconnect (particularly a via conductor, etc.) that passes through the core plate to establish an electrical connection between the buildup layers formed on the front and back sides of the core panel. The intermediate product allows a semiconductor integrated circuit component (IC chip) such as a microprocessor such as a computer to be mounted thereon.

Recently, as semiconductor integrated circuit components become faster, the frequency of signals used in the components gradually increases (i.e., becomes higher). In this case, the interconnects passing through the core board act as large inductances, which in turn cause transmission losses in high frequency signals and the occurrence of erroneous circuit operations. Therefore, an increase in the speed of the semiconductor integrated circuit component is hindered. In view of this deficiency, the present invention proposes a coreless multilayer wiring board (that is, the wiring board does not have any core board) (for example, refer to JP-B-3664720). Since the relatively thick core plate is omitted from the coreless wiring board, the overall length of the interconnect is shortened. Therefore, transmission loss in the high frequency signal can be reduced, and the semiconductor integrated circuit element can be operated at high speed.

However, since the coreless wiring board is manufactured without a core board, the strength of the coreless wiring board may be insufficient. When a multilayer wiring board is fabricated as a coreless wiring board, even if the dummy conductor layer is formed on the surface of the frame portion, the strength of the intermediate multilayer wiring board article is insufficient. Therefore, when a member such as a semiconductor integrated circuit component and a capacitor is adhered to an intermediate product, and when the solder for adhesion is cooled, under the influence of thermal stress caused by a difference in thermal expansion coefficient between the product forming region and the frame portion, The intermediate article may warp, thereby reducing the yield of the multilayer wiring board.

The present invention has been completed in consideration of the above circumstances. It is an object of the present invention to provide an intermediate multilayer wiring board article which prevents the occurrence of warpage and improves the yield of the article. Another object of the present invention is to provide a method of manufacturing a multilayer wiring board which can improve yield.

According to an aspect of the present invention, an intermediate multilayer wiring board article comprises: a stack of a plurality of resin insulating layers, a first conductor layer, and a second conductor layer. The stack includes: a product forming region comprising a plurality of article portions disposed along a major surface of the stack, each of the plurality of product portions becoming an article of the multilayer wiring board; and a frame portion surrounding the article forming region. The first conductor layer is formed on at least one of the plurality of resin insulating layers in each of the plurality of product portions. The second conductor layer is formed on at least one of the plurality of resin insulating layers in the frame portion. The frame portion has a plurality of cuts that pass through the frame portion in a thickness direction thereof, and the plurality of cut portions are disposed at substantially equal intervals.

Therefore, according to the aspect of the intermediate product of the multilayer wiring board, when the member is connected to the first conductor layer, even if a thermal stress caused by a difference in thermal expansion coefficient between the product forming region and the frame portion is applied to the intermediate multilayer wiring board The article deforms the plurality of cut portions to suppress the influence of thermal stress. The cut portions are disposed in the frame portion at substantially the same interval, wherein the frame portion can equalize the amount of deformation in the cut portions when thermal stress is applied to the intermediate product. Therefore, the influence of thermal stress is uniformly suppressed. Therefore, occurrence of warpage in the intermediate multilayer wiring board article can be prevented, and the yield of the article produced from the intermediate product can be improved.

When the multilayer wiring board does not include the core board and includes the resin insulating layer and the first conductor layer which are alternately stacked, wherein the resin insulating layers are the same type of resin insulating layer and the first conductor layers are transmitted in one direction The enlarged diameter via holes are connected, the multilayer wiring board cannot have sufficient strength, and the warpage of the intermediate multilayer wiring board article becomes more conspicuous. However, when the cut portions are provided in the multilayer wiring board which does not have the core board, warpage in the intermediate product can be more effectively prevented.

In this and subsequent aspects, the "intermediate wiring board article" refers to the complication of the final multilayer wiring board article. Specifically, the "intermediate product" is designated as a multilayer wiring board in which the separation process is not completed. The separating process is for separating the articles from each other by removing the frame portions from the article forming region and cutting the product forming regions along the tangent lines set by the contours of the product portions. In general, the intermediate multilayer wiring board product, the product forming region, and the product portion have a substantially rectangular shape when viewed from above (plan view). The area of the product portion is much smaller than the area of the product forming region. Thus, for example, tens to hundreds of article sections are disposed within the article forming zone.

By "frame portion" is meant an area that does not become an article and that separates and removes from the article forming region during processing and surrounds the periphery of the article forming region. A second conductor layer is formed in the frame portion as a so-called dummy conductor layer.

The intermediate multilayer wiring board article has a structure including a plurality of stacked resin insulating layers. The resin insulating layer can be selected, for example, in accordance with insulation properties (heat resistance and moisture resistance). The resin insulating layer may be formed of any of the following materials: a thermosetting resin such as an epoxy resin, a phenol resin, a urethane resin, a enamel resin, and a polyimide resin; and a thermoplastic resin such as a polycarbonate resin. Acrylic resin, polyacetal resin and polypropylene resin). In addition, it is also possible to use a composite material comprising any of these resins and inorganic fibers such as glass fibers (woven glass fabrics or non-woven glass fabrics), or organic resins such as polyimine fibers. A composite of fibers, or a resin-resin composite obtained by impregnating a three-dimensional mesh-like fluororesin material such as expanded PTFE with a thermosetting resin such as an epoxy resin. In order to form a via conductor for interlayer connection, via holes may be formed in the resin insulating layer in advance.

The first conductor layer and the second conductor layer may be patterned on the resin insulating layer, for example, by subtractive method, semi-additive method, full addition method, or the like. The first conductor layer and the second conductor layer are formed, for example, of a metal material such as copper, a copper alloy, nickel, a nickel alloy, tin, a tin alloy, or the like.

Solder bumps for connecting a member may be provided on the first conductor layer formed on the outermost resin insulating layer of the stack. The solder bumps are electrically connected between the first conductor layer and the member.

The metal material forming the solder bumps can be selected in accordance with a material forming a connection terminal of a member to be mounted, and the like. For example, any of the following materials may be used as the metal material for forming the solder ball: Pb-Sn-based solder (such as 90Pb-10Sn, 95Pb-5Sn, or 40Pb-60Sn); Sn-Sb-based solder; Sn -Ag-based solder; Sn-Ag-Cu-based solder; Au-Ge-based solder; and Au-Sn-based solder.

Examples of the member may be a capacitor fabricated in a semiconductor process, a semiconductor integrated circuit component (IC wafer), a MEMS (Micro Electro Mechanical System), and the like. Further, the IC chip may be a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory), or the like. The "semiconductor integrated circuit component" may mean an element used as a microprocessor of a computer, and the like.

The plurality of cut portions pass through the frame portion in the thickness direction thereof and open in the outer end of the frame portion. The cut may have a generally V-shape, a generally U-shape or other similar shape as viewed in the thickness direction. At least one of the plurality of cuts may also be a slit that is disposed along an extension of a tangent set by the contours of the article portions and that has substantially the same contour as the adjacent article portion The width of the spacing between lines. In this case, the plurality of cut portions are arranged in accordance with the product portions that are generally arranged at equal intervals, and thus it becomes easy to arrange the plurality of cut portions at equal intervals. Although the depth of the cut portion is not particularly limited, the depth may be set substantially equal to the width of the frame portion (the distance from the boundary between the frame portion and the article forming region to the outer end of the frame portion). In particular, the frame portion can also be separated by a plurality of segments. In other words, when the cut portions become deeper, the influence of the thermal stress applied to the intermediate multilayer wiring board article can be more effectively reduced. Therefore, warpage of the intermediate product can be prevented more reliably.

The frame portion may have an edge portin surrounding the article forming region and a plurality of corner portions, each corner portion connecting adjacent end portions. The plurality of cut portions may be disposed at the cut portions of the corner portions to remove the corner portions. According to the cut portions arranged in this manner, cut portions larger than the cut portions provided on the end portions can be formed in the corner portions. Therefore, the influence of the thermal stress applied to the intermediate multilayer wiring board article can be more reliably suppressed. As described above, warpage of the intermediate article can be prevented more reliably, and the product yield can be further improved.

The plurality of cut portions may be formed after the first conductor layer and the second conductor layer are formed. When the plurality of dicing portions are formed before the first conductor layer and the second conductor layer are formed, they will be patterned by transparent etching to form the first conductor layer and the second conductor layer It becomes difficult to attach a mask for etching.

According to another aspect of the present invention, an intermediate multilayer wiring board article comprises: a stack of a plurality of resin insulating layers, a first conductor layer, and a second conductor layer. The stack includes: a product forming region comprising a plurality of article portions disposed along a major surface of the stack, each of the plurality of product portions becoming an article of the multilayer wiring board; and a frame portion surrounding the article forming region. The first conductor layer is formed on at least one of the plurality of resin insulating layers in each of the plurality of product portions. Except for the plurality of non-formed regions disposed in the frame portion, the second conductive layer is formed on at least one of the plurality of resin insulating layers in the frame portion such that the first conductive layer forms a region for the article The first area ratio is substantially equal to the second area ratio of the second conductor layer to the frame portion.

According to the aspect of the intermediate multilayer wiring board product, the plurality of non-formed regions are disposed such that the first area ratio of the first conductor layer to the product forming region is substantially equal to the second area of the second conductor layer to the frame portion ratio. Therefore, it can reduce the difference between the coefficient of thermal expansion between the product forming regions and the coefficient of thermal expansion of the frame portion. Even when a thermal stress caused by a difference in thermal expansion coefficient is applied to the intermediate multilayer wiring board article when a member is attached to the first conductor layer, warpage hardly occurs in the intermediate product. Therefore, the yield of the articles produced by the intermediate products can be improved.

For the purposes of this description, the "first area ratio of the first conductor layer to the article formation region" refers to the known area occupied by the first conductor layer (when the known area is disposed on the surface of the article formation region) The ratio (exposure ratio). Similarly, the "area ratio of the second conductor layer to the frame portion" means the ratio of the known area occupied by the second conductor layer (when the known area is set on the surface of the frame portion) (exposing proportion). In addition, the expression "the first area ratio of the first conductor layer to the article formation region is equal to the second area ratio of the second conductor layer to the frame portion" is assumed to include the first and second area ratios substantially The case of being equal to each other, and including the case where the area ratios are completely equal to each other.

By arranging the plurality of non-formed regions on all of the resin insulating layers in the frame portion, the first area ratio of the first conductive layer to the article forming region in each layer of the stack may be equal to the frame side conductor layer The second area ratio of the frame. Therefore, it can reduce the difference in thermal expansion coefficient between the article forming region and the frame portion. Therefore, even if thermal stress caused by the difference in thermal expansion coefficient is applied to the intermediate product of the multilayer wiring board, warpage hardly occurs in the intermediate product.

When the multilayer wiring board is a wiring board that does not include a core board and alternately stacks a resin insulating layer and a first conductor layer, wherein the resin insulating layers are of the same type and the first conductor layers are only expanded in diameter by one direction The vias are connected, the strength of the multilayer wiring board is insufficient, and the warpage of the intermediate multilayer wiring board article may increase or become more apparent. However, when the non-formation regions are provided in a multilayer wiring board having no core board, warpage can be more effectively prevented from occurring in the intermediate product.

The plurality of non-formed regions are disposed on at least one of the resin insulating layers in the frame portion. The non-formed regions can have a generally V-shape, a generally U-shape, and the like. At least one of the plurality of non-formed regions may also be a slit-shaped region disposed along an extension of a tangent set by a contour of the article portion. In this case, the plurality of non-formed regions are arranged in accordance with the product portions that are generally arranged at equal intervals, and thus it becomes easy to arrange the plural non-formed regions at equal intervals. Therefore, it becomes easy to make the second conductor layer conform to the second area of the frame portion in any region in the frame portion. Therefore, it can reduce the difference in thermal expansion coefficient between the product forming region and the frame portion. Therefore, even if the thermal stress caused by the difference in thermal expansion coefficient is applied to the intermediate product of the multilayer wiring board, the warpage of the intermediate product hardly occurs. When the non-formation region is a slit-shaped region, although not particularly limited, the depth of the non-formation region may be set to be equal to, for example, the width of the frame portion (from the boundary between the frame portion and the article formation region) The distance to the outermost end of the frame). In particular, the second conductor layer can be separated by a plurality of non-formed regions.

The frame portion may have a plurality of ends that surround the article forming region and the plurality of corner portions, each corner portion connecting adjacent end portions. In the plurality of non-formed regions, the non-formed regions located at the corner portions may occupy the entire corner portion such that the first area ratio of the first conductor layer to the article forming region is equal to the second conductor layer to the frame The second area ratio of the department. The second conductor layer may have a mesh pattern such that a second area ratio of the second conductor layer to the frame portion is equal to a first area ratio of the first conductor layer to the article formation region. The method for configuring the non-formed region may be selected in accordance with a first area ratio of the first conductor layer to the article formation region.

When the second conductor layer is formed in a mesh pattern, the burden of pattern design can be alleviated. Therefore, it is easy to prevent an increase in cost. The mesh-shaped second conductor layer may be any layer as long as the region including the conductor layer and the region not including the conductor layer are continuously presented in a regular pattern. However, from the viewpoint of reducing the burden of pattern setting, it is preferable to arrange a plurality of line patterns that intersect each other. More specifically, the mesh-shaped second conductor layer is preferably formed by causing a plurality of first line patterns arranged at equal intervals and a plurality of second line patterns arranged at equal intervals to intersect each other at right angles. In this case, although the width of the line pattern is not particularly limited, it is preferable to set the width of the line pattern to, for example, a range from 0.1 mm to 1.5 mm; further, it may be set from 0.2 mm to 1.3. The range of mm, and more particularly, may range from 0.3 mm to 1.0 mm.

According to another aspect of the present invention, a method of manufacturing a multilayer wiring board includes: a preparation process including an intermediate product for preparing a multilayer wiring board; and a cut portion forming process. The intermediate article comprises: a stack of a plurality of resin insulating layers, a first conductor layer and a second conductor layer. The stack includes: a product forming region comprising a plurality of article portions disposed along a major surface of the stack, each of the plurality of product portions becoming an article of the multilayer wiring board; and a frame portion surrounding the article forming region. The first conductor layer is formed on at least one of the plurality of resin insulating layers in each of the plurality of product portions. The second conductor layer is formed on at least one of the plurality of resin insulating layers in the frame portion. The cut forming process includes forming a plurality of cuts in a frame portion of the intermediate article to pass through the frame portion in a thickness direction thereof.

According to the aspect of the method of manufacturing the multilayer wiring board, when a member is connected to the first conductor layer after the cutting portion forming process, if a difference in thermal expansion coefficient between the product forming region and the frame portion is applied The thermal stress is applied to the plurality of resin insulating layers, and the influence of the thermal stress can be suppressed by the deformation of the plurality of cut portions. Therefore, it can suppress the occurrence of warpage in the intermediate multilayer wiring board article, and thus the yield of the multilayer wiring board produced by the intermediate product can be improved.

The method of manufacturing the multilayer wiring board of this aspect will be described below.

In the preparation process, an intermediate multilayer wiring board product is prepared, the intermediate multilayer wiring board product comprising: a plurality of stacked resin insulating layers; a product forming area, wherein the plurality of product parts to be the product are arranged in the longitudinal direction and the horizontal direction; And surrounding the product forming region; the first conductor layer is formed on the resin insulating layer in the product portion; and the second conductor layer is formed on the resin insulating layer in the frame portion.

The preparation process includes a stacking process including stacking the plurality of resin insulating layers on a bottom component, one surface of the bottom component having a metal foil, and a bottom component removing process including removing the bottom component after the stacking process a first conductor layer forming process, comprising: patterning the metal foil after the bottom component removal process to fabricate the first conductor layer in the plurality of product portions on the outermost resin insulating layer; And a solder bump forming process, comprising: forming a solder bump for connecting a member on the first conductor layer formed on the outermost resin insulating layer after the first conductor layer forming process. By simultaneously performing the second conductor layer forming process (the second conductor layer is formed in the frame portion on the outermost resin insulating layer) and the first conductor layer forming process, the process for manufacturing the multilayer wiring board can be shortened .

For example, any one of silver, gold, platinum, copper, titanium, aluminum, palladium, nickel, and tungsten can be used as the metal foil. In particular, the metal foil is preferably made of copper. If the metal foil is made of copper, the electrical resistance of the metal foil can be lowered and the conductivity of the metal foil can be enhanced as compared with the metal foil being made of other materials.

In the subsequent dicing forming process, the plurality of dicing portions are formed in the frame portion through the frame portion in the thickness direction thereof. The cut portions can be formed by drilling the frame portion, subjecting the frame portion to a laser mechanical treatment, punching the frame portion with a punching die, and the like.

The cut forming process can be performed after the first conductor layer forming process. When the cut portion forming process is performed before the first conductor layer forming process, it becomes difficult to adhere to the mask for etching when performing patterning by etching in the first conductor layer forming process. In addition, the dicing process can be performed prior to the solder bump forming process. When the dicing process is performed after the solder bump forming process, the solder bumps, which are important for component bonding, may be damaged during formation of the dicing portions.

Thereafter, a separation process is performed for separating the articles by removing the frame portions from the article forming region and cutting the article forming regions along the tangent set by the contours of the article portions To obtain a plurality of products (multilayer wiring boards).

According to still another aspect of the present invention, a method of manufacturing a multilayer wiring board includes: a preparation process including preparing an intermediate multilayer wiring board article; and a separation process. The intermediate article comprises: a stack of a plurality of resin insulating layers; a first conductor layer and a second conductor layer. The stack includes: a product forming region comprising a plurality of article portions disposed along a major surface of the stack, each of the plurality of product portions becoming an article of the multilayer wiring board; and a frame portion surrounding the article forming region. The first conductor layer is formed on at least one of the plurality of resin insulating layers in the product portion. The second conductor layer is formed on at least one of the plurality of resin insulating layers in the frame portion, except for the plurality of non-formation regions disposed in the frame portion, such that the first conductor layer is the first region of the article formation region An area ratio is substantially equal to a second area ratio of the second conductor layer to the frame portion. The separating process includes removing the frame from the article forming region and cutting the article forming region along a tangential line to separate the plurality of article portions (i.e., the articles) from each other.

Therefore, according to the aspect of the manufacturing method of the multilayer wiring board, the plurality of non-formation regions are disposed in the preparation process such that the first area ratio of the first conductor layer to the article formation region is equal to the second conductor layer to the frame The second area ratio of the department. Therefore, it can reduce the coefficient difference of thermal expansion between the product forming region and the frame portion. Therefore, when a member is attached to the first conductor layer after the preparation process, even if thermal stress caused by a difference in thermal expansion coefficient is applied to the intermediate multilayer wiring board article, warpage hardly occurs in the intermediate product. . Therefore, the yield of the multilayer wiring board produced from the intermediate products can be improved.

The aspect of the method of manufacturing a multilayer wiring board in this aspect will be described below.

In the preparation process, an intermediate multilayer wiring board product is prepared, the intermediate multilayer wiring board product comprising: a plurality of stacked resin insulating layers; a product forming area, wherein the plurality of product parts to be the product are arranged in the longitudinal direction and the horizontal direction; a portion surrounding the product forming region; a first conductor layer formed on the resin insulating layer in the product portion; a second conductor layer formed on the resin insulating layer in the frame portion; and a plurality of non-formed regions, Disposed on at least one of the resin insulating layers in the frame portion, and wherein the second conductor layer is not formed, such that the first area ratio of the first conductor layer to the article forming region is equal to the second conductor layer pair The second area ratio of the frame.

Other features and advantages of the invention will be apparent from the description of the appended claims.

Exemplary embodiments of the present invention will be described in detail with reference to the drawings.

First exemplary embodiment

Fig. 1 is a cross-sectional view showing a coreless wiring board 101 (multilayer wiring board) of an exemplary embodiment. The coreless wiring board 101 is a wiring board having no core board, and has a conductor layer 51 made of copper alternately stacked and four layers of resin insulating layers 41, 42, 43 and 44 made of epoxy resin. The structure made. The resin insulating layers 41 to 44 are intermediate insulating layers having the same thickness and made of the same material (that is, the resin insulating layers 41 to 44 are the same type of resin insulating layers).

The terminal pad 52 is attached to the front surface 102 of the coreless wiring board 101 (the surface of the resin insulating layer 44 on the fourth layer from the bottom layer 41 of the stacked resin insulating layers 41 to 44) in an array pattern. Configuration. Further, the substantially integral surface of the resin insulating layer 44 is covered with the solder resist 128. An opening 129 for exposing the respective terminal pads 52 is formed in the solder resist 128. A plurality of solder bumps 130 are disposed on the surface of each of the terminal pads 52. The solder bumps 130 are electrically connected to respective connection terminals 132 of the IC wafer 131 (member) having a substantially rectangular shape. The area where the terminal pads 52 and the solder bumps 130 are formed is the IC wafer mounting region 133 in which the IC wafer 131 can be mounted.

As shown in Fig. 1, a BGA pad 53 is disposed on the back surface 103 of the coreless wiring board 101 (on the lower surface of the resin insulating layer 41 on the first layer of the stack) in an array pattern. The substantially integral surface of the resin insulating layer 41 is covered with the solder resist 142. An opening 145 for exposing the respective BGA pads 53 is formed in the solder resist 142. A plurality of solder bumps 155 are provided on the surface of each of the BGA pads 53, and the coreless wiring board 101 is mounted on a mother board (not shown) by the solder bumps 155.

The via hole 146 and the via conductor 147 are provided in the resin insulating layers 41 to 44. Each of the via holes 146 has an inverted truncated cone shape and is formed by passing through the resin insulating layers 41 to 44 through the use of a YAG laser or a carbon dioxide gas laser. The conductive conductors 147 are increased in diameter in one direction (upward direction in FIG. 1), and are electrically connected to the conductor layers 51, the terminal pads 52, and the BGA pads 53.

The intermediate product 11 of the coreless wiring board 101 will now be described.

As shown in Figs. 2 and 3, when the intermediate product 11 of the coreless wiring board 101 is viewed from above, it has a substantially rectangular shape. The intermediate article 11 includes a product forming region 28 and a frame portion 29 for surrounding the periphery of the article forming region 28. Five square product portions 27, which are products (the coreless wiring board 101), are disposed in the product forming region 28 along the direction of the main surface of the intermediate product 11. The frame portion 29 has four end portions 30 that are configured to surround the article forming regions 28, and four corner portions 31 that connect adjacent end portions 30.

As shown in FIG. 3, the conductor layers 51 as exemplified as the first conductor layers are formed on the surfaces of the resin insulating layers 41 to 44 in each of the product portions 27. The terminal pads 52 as exemplified as the first conductor layers are formed on the surface of the resin insulating layer 44 at the outermost layer in the stack in each of the product portions 27. The BGA pads 53 as exemplified as the first conductor layer are formed on the lower surface of the resin insulating layer 41 at the outermost layer in each of the product portions 27. A frame-side conductor layer 54 as an example of the second conductor layer is formed on each of the resin insulating layers 41 to 44 in each of the frame portions 29. The frame side conductor layer 54 is formed as a planar conductor having a substantially rectangular shape over a substantial integral area within each of the frame portions 29. None of the frame side conductor layers 54 remain in the final article and are referred to as dummy conductor layers.

As shown in FIGS. 2 and 3, the intermediate product 11 of the coreless wiring board 101 is cut along the outline 120 of each of the product portions 27. Lines extending along these contour lines 120 are defined as tangent lines 121. More specifically, the tangent lines 121 for dividing the product portions 27 are disposed between the contour lines of the adjacent product portions 27. In addition, other tangent lines 121 for separating the frame portion from the product forming region 28 are in the region between the contour line 120 of the product portion 27 and the inner edge of the frame side conductor layer 54, along the article. The boundary between the formation region 28 and the frame portion 29 is set.

As shown in Fig. 2, the frame portion 29 has a plurality of slits 61 (cut-out regions) each of which is substantially U-shaped when viewed in the thickness direction (planar view). The slits 61 are disposed at equal intervals in the end portions 30 and are disposed (or disposed) along the extending direction of the tangent line 121. Portions of the slits 61 are disposed on the boundary between the end portions 30 and the corner portions 31. The slits 61 are configured such that each of the regions defined between the adjacent slits 61 is smaller than a predetermined or known size. Each of the slits 61 passes through the frame portion 29 in a thickness direction (specifically, the resin insulating layers 41 to 44, the frame side conductor layer 54, and the solder resists 128 and 142). And formed, and the outer end of the frame portion 29 becomes open. The width of each of the slits 61 is substantially set equal to the interval between the contour lines 120 of the adjacent product portions 27, or between the outline 120 of the product portion 27 and the inner edge of the frame-side conductor layer 54. Interval. The depth of each of the slits 61 (i.e., the length of the slit 61 from its opening to its inner depth) is set to be slightly smaller than the width of the frame side conductor layer 54 (from the frame side conductor layer 54). The distance from the inner edge to the outer edge of the frame side conductor layer 54).

A method of manufacturing the coreless wiring board 101 will now be described.

In the preparation process, the intermediate product 11 of the coreless wiring board 101 shown in Figs. 2 and 3 is preliminarily produced and prepared. The intermediate product 11 of the coreless wiring board 101 is prepared in the following manner. As shown in Fig. 4, a support plate 70 exhibiting sufficient strength, such as a glass epoxy board, is first prepared. Next, a sheet-like insulating resin bottom member made of epoxy resin is attached to the support plate 70 partially in a hardened state to form a bottom resin insulating layer 71 to obtain a bottom portion including the support plate 70 and the substrate resin insulating layer 71. Component 69. As shown in Fig. 5, a multilayered metal sheet member 72 is provided on one surface of the bottom member 69 (specifically, the upper surface of the bottom resin insulating layer 71). The multilayered metal sheet member 72 is attached to the bottom resin insulating layer 71 which is partially in a hardened state. Therefore, it is possible to obtain sufficient adhesion so that the multilayered metal sheet member 72 does not peel off from the bottom resin insulating layer 71 during the subsequent process. The multilayer metal sheet assembly 72 includes two copper foils 73, 74 (metal foil) which are in a peelable state and adhere to each other. In particular, the multilayer metal sheet assembly 72 is formed by laminating a metal (e.g., chrome plating) by stacking sheets of copper foil 73 and 74.

Subsequently, as shown in FIG. 6, the sheet-like insulating resin bottom member 40 is stacked on the multilayered metal sheet assembly 72, and the bottom assembly 40 is added by vacuum in a vacuum by a vacuum heat press (not shown). The insulating resin base member 40 is cured by pressing and heating, whereby the resin insulating layer 41 is formed on the first layer (stacking process). As shown in FIG. 7, the via hole 146 is formed at a specific position in the resin insulating layer 41 by performing a laser mechanical treatment and a decontamination treatment for removing the contamination in each of the via holes 146. Subsequently, electroless copper plating or electrolytic copper plating is performed, for example, by a conventional technique, whereby the conduction conductor 147 is formed in each of the via holes 146. Further, etching is performed by, for example, a conventional technique (for example, a semi-additive method), whereby a conductor layer 51 is patterned on the resin insulating layer 41 (refer to Fig. 8).

As described above, the resin insulating layers on the second to fourth layers are formed by the same technique for forming the resin insulating layer 41 on the first layer and the conductor layer 51 formed thereon. 42 to 44 and the conductor layers 51 are also formed on the resin insulating layer 41 in a stacked manner. A photosensitive epoxy resin is applied over the resin insulating layer 44 at the terminal pads 52, and the resin thus applied is cured to form the solder resist 128. When the mask is disposed, the solder resist 128 is exposed and developed to form the openings 129 in the solder resist 128 by patterning. The multilayered metal sheet assembly 72, the resin insulating layers 41 to 44, and the layered product 80 of the conductor layers 51 are formed on the support plate 70 in accordance with the above-described process (see FIGS. 9 and 10). As shown in FIG. 9, the area on the multilayered article 80 on the multilayered metal sheet assembly 72 serves as a stacked wiring area 81 which will become the coreless wiring board 101. Intermediate product 11. Further, as shown in the 10th circle, two blocks 82 are disposed thereon along the main surface of the multilayer article 80, and the three intermediate products 11 are disposed in the regions along the direction of the main surface. Each of the blocks 82, and the periphery of the blocks 82, are surrounded by a peripheral portion 83.

In the next first separation process, the multilayered article 80 is cut by a microtome (omitted from the drawing) to remove the peripheral portion 83 of each of the blocks 82. At this time, as shown in FIG. 10, the bottom resin insulating layer 71 and the support plate 70 (which are all located below the stacked wiring area 81) are along the respective blocks 82 and its peripheral portion 83. The boundary is cut. Thereby, the blocks 82 are separated from each other to obtain two blocks 82 (refer to Fig. 11).

In each of the blocks 82, the bottom assembly 69 is removed to expose the copper foil 73 (bottom assembly removal process). More specifically, as shown in FIG. 12, the stacked wiring portion 81 is separated from the support plate 70 by peeling off the two copper foils 73 and 74 of the stacked metal sheets 72. As shown in Fig. 13, the copper foil 73 on the back surface 103 (lower surface) of the stacked wiring region 81 (the resin insulating layer 41) is patterned by etching to facilitate resin insulation of the outermost layer. A BGA pad 53 (first conductor layer forming process) is formed in the product portion 27 on the layer 41. Thereafter, as shown in FIG. 14, a photosensitive epoxy resin is applied over the resin insulating layer 41 on which the BGA pad 53 is formed, and the resin is cured, thereby forming the solder resist 142 to cover the stacked wiring portion. The back surface 103 of 81 (solder resist formation process). Next, when a mask is placed on the solder resist 142, the solder resist 142 is exposed and developed, thereby patterning the solder resist 142 to form the openings 145.

In the subsequent dicing forming process, the plurality of slits 61 are formed in the frame portions 29 of each of the intermediate products 11 forming the block 82 (refer to Fig. 15). Specifically, a region in which the frame portions 29 of the adjacent intermediate articles 11 in the frame portion 29 are in contact with each other is mechanically treated by a router to form the extending holes 60. The extension holes 60 serve as slits 61 for a particular intermediate article 11 and slits 61 adjacent the intermediate article 11 of the particular intermediate article 11. Further, the regions in which the frame portions 29 of the intermediate products 11 adjacent to each other in the grooved frame portion 29 are not in contact with each other are mechanically treated to form the slits 61. These slits 61 are formed after the conductor layers 51, the terminal pads 52, the BGA pads 53, and the frame side conductor layers 54 have been formed (after the first conductor layer forming process).

Next, solder bumps 130 (solder bump forming processes) for connecting IC chips are formed on the respective terminal pads 52 formed on the outermost resin insulating layer 44. The dicing forming process is performed prior to the solder bump forming process. In this process, solder balls are disposed on the respective terminal pads 52 by use of a solder ball assembly machine not shown, and the solder balls are then heated at a known temperature to cause solder reflow and the like. Solder bumps 130 are formed on the respective terminal pads 52. Similarly, the solder bumps 155 are also formed on the respective BGA pads 53 formed on the back surface 103 of the multilayer wiring region 81.

In a subsequent second separation process, the blocks 82 are cut along the boundary between the intermediate articles 11 by a microtome (not shown). The intermediate articles 11 are thus separated from one another in order to obtain the intermediate article 11 of the coreless wiring board 101 shown in Figures 2 and 3.

In the subsequent IC wafer assembly process, the IC wafer 131 is mounted on each of the IC wafer mounting regions 133 of the respective product portions 27 (the coreless wiring sheets 101) forming each of the intermediate products 11. . The surface connection terminals 132 formed on the IC wafer 131 are aligned with the respective solder bumps 130 formed on the product portion 27. The solder bumps 130 are heated to reflow such that the surface connection end 132 is adhered to the solder bumps 130. Therefore, the IC chip 131 is mounted on the product portion 27.

In a subsequent third separation process, the frame portions 29 are cut and removed from the article forming region 28 by a conventional cutter, and the article forming region 28 is cut along the tangent lines 121. The product portions 27 are separated from each other into a plurality of coreless wiring boards 101 (see Fig. 1).

According to the first exemplary embodiment, the following advantages can be obtained.

(1) The intermediate product 11 of the coreless wiring board 101 according to this exemplary embodiment, during cooling of the solder bumps 130 for connecting the IC wafer 131, even when the article forming region 28 and the frame portion 29 are applied When the thermal stress caused by the difference in thermal expansion coefficient is between the intermediate products 11, the influence of the thermal stress is reduced by the deformation of the plurality of slits 61. Further, the slits 61 are provided at substantially equal intervals in the frame portions 29, and when thermal stress is applied to the slits 61, a uniform amount of deformation can be provided in each of the slits 61. Therefore, the thermal stress is uniformly reduced. Therefore, the occurrence of warpage in the intermediate articles 11 can be prevented, so that the yield of the articles (these coreless wiring boards 101) obtained from the intermediate products 11 can be improved.

(2) In the first exemplary embodiment, the portion of the article forming region 28 is covered by the first conductor layers (the conductor layer 51 and the terminal pad 52), but the substantial integral region of the frame portion 29 The second conductor layer (frame side conductor layer 54) is covered. Therefore, there is a large difference between the area ratio of the first conductor layer to the product forming region 28 and the area ratio of the second conductor layer to the frame portion 29. When the IC wafer 131 is mounted on the terminal pad 52 and when the solder bumps 130 for connection are cooled, thermal stress caused by the difference in the area ratios is applied to the intermediate product 11. However, in the first exemplary embodiment, the influence of the thermal stress caused by the difference in the area ratio can be suppressed by the plurality of slits 61.

This first exemplary embodiment can be modified in the following manner.

In the intermediate product 11 of the coreless wiring board 101 of the first exemplary embodiment, each of the plurality of cut portions is formed by a slit 61. However, the intermediate article may contain cuts, wherein some of the cuts have a shape different from the slit 61. Figure 16 shows an intermediate article 111 modified in accordance with one of the first exemplary embodiments. In the intermediate product 111, the cut portions provided in the end portions 30 are formed by the slits 61 as described in the first exemplary embodiment. On the other hand, the cut portions provided on the corner portions 31 are formed by removing the cut portions 112 formed by the respective corner portions 31. In other words, the cut portions 112 are defined by the respective corner portions 31 that are removed. The cut portions 112 formed on the respective corner portions 31 can be formed to be larger than the cut portions (slits 61) provided on the end portions 30. Therefore, the influence of the thermal stress applied to the intermediate product 111 can be more reliably reduced. Therefore, it is possible to more reliably prevent the warpage in the intermediate product 111 from occurring, so that the product yield is further improved.

The slit 61 of the first exemplary embodiment is disposed in the frame portion 29 along the extension of the tangent line 121 set by the contour line 120 of the product portions 27. However, the slits 61 may also be disposed in a direction slightly offset from the extension of the tangential lines 121 in the direction of the major surface of the intermediate product 11.

The dicing forming process of the first exemplary embodiment is performed between the first conductor layer forming process and the solder bump forming process. However, the dicing forming process may be performed between the solder bump forming process and the second separating process, or between the second separating process and the IC wafer assembly process.

Second exemplary embodiment

A second exemplary embodiment of the present invention will be described with reference to the drawings. In the second exemplary embodiment, the non-formed regions are formed on an intermediate article in place of the cut portions 61 of the first exemplary embodiment. Similar or identical elements and operations associated with the first exemplary embodiment are denoted by the same reference numerals, and the description thereof will be omitted in this exemplary embodiment.

Fig. 17 is a plan view showing the intermediate product 12 of the coreless wiring board in accordance with the second exemplary embodiment. The cross-sectional view of the coreless wiring board of the present exemplary embodiment is the same as that shown in FIG. 1, and the cross-sectional view of the intermediate product 12 cut along the line AA of FIG. 17 is the same as that shown in FIG. Therefore, the relevant description is omitted.

As shown in Fig. 17, a plurality of non-formation regions 62 are disposed on each of the resin insulating layers 41 to 44 in the frame portion 29. In the non-formation region 62, the frame side conductor layer 54 is not formed. The non-formed region 62 has a slit shape that is disposed substantially at a uniform spacing in each of the end portions 30 and that is disposed (or disposed thereon) along an extension of each tangent line 121. Portions of the non-formed regions 62 are disposed along the boundary between the end portions 30 and the corner portions 31. Since the respective non-formation regions 62 are opened at the inner and outer edges of the frame portion 29, the length of each of the non-formation regions 62 is set equal to the width of the frame-side conductor layer 54 (from the The distance from the inner edge of the frame side conductor layer 54 to its outer edge). Specifically, the frame side conductor layer 54 is divided by the respective non-formation regions 62. Further, the width of the non-formation region 62 is set to be equal to the interval between the outlines 120 of the adjacent product regions 27 or the interval between the outline 120 of the product portion 27 and the inner side of the frame-side conductor layer 54.

The non-formation regions 62 are disposed on each of the resin insulating layers 41 to 44 in the frame portions 29 such that the first conductor layer (the conductor layers 51 or the terminal pads 52) The first area ratio of the product forming region 28 is equal to the area ratio of the second conductor layer (frame side conductor layer 54) to the frame portion 29 on each layer. More specifically, on the surface of the resin insulating layer 41 of the first layer, the first area ratio of the conductor layer 51 to the product forming region 28 and the second area of the frame portion 29 of the frame side conductor layer 54 are It is set to 67% more than both. On the surface of the resin insulating layer 42 of the second layer, the first area ratio of the conductor layer 51 to the product forming region 28 and the second area ratio of the frame side conductor layer 54 to the frame portion 29 are both provided. It is 86%. On the surface of the resin insulating layer 43 of the third layer, the first area ratio of the conductor layer 51 to the product forming region 28 and the second area ratio of the frame side conductor layer 54 to the frame portion 29 are both provided. It is 64%. On the surface of the resin insulating layer 44 of the fourth layer, the first area ratio of the conductor layer 51 and the terminal pads 52 to the product forming region 28 and the frame side conductor layer 54 occupy the second portion of the frame portion 29. The area ratio is set to 78%.

Next, a method of manufacturing a coreless wiring board according to the second exemplary embodiment will be described. First, as shown in Figures 4 and 5, the preparation process is performed. Next, the stacking process is performed as shown in FIG. 6, and then the via holes 146 are formed as shown in FIG. Thereafter, the conductive wires 147 and the conductor layers 51 are formed as shown in FIG.

In the second exemplary embodiment, the frame side conductor layer 54 is patterned on the resin insulating layer 41 in the frame portion 29 of the intermediate products 12 in the same process as the patterning of the conductor layer 51. And the plurality of non-formation regions 62 (in which the frame side conductor layer 54 is absent) are also formed in the frame portions 29.

Next, as shown in FIG. 9, the layered article 80 is formed on the support plate 70. Figure 18 is a plan view showing the layered article 80 of the second exemplary embodiment. Next, the first separation process is performed in the same manner as the first exemplary embodiment. Figure 19 is a plan view showing the block 82 of the second exemplary embodiment, wherein the block 82 is separated by the first separating process. Thereafter, the bottom assembly removing process shown in Fig. 12, the first conductor layer forming process shown in Fig. 13, and the solder resist forming process shown in Fig. 14 are performed. Further, the solder bump forming process and the second separating process are performed as in the first exemplary embodiment to obtain the intermediate article 12 shown in FIG. 17 (and FIG. 3). Thereafter, the first separation process is performed as in the first exemplary embodiment to obtain the plurality of coreless wiring boards 101 (Fig. 1).

A method for evaluating warpage in an intermediate product of a coreless wiring board and an evaluation result will now be described.

First, a sample (measurement sample) for measurement is prepared in the following manner: an intermediate product 12 which is the same as the intermediate product of the second exemplary embodiment is prepared as an example sample; and an intermediate product 151 (refer to Fig. 20) is prepared as In the sample of the comparative example, in the intermediate product 151, the non-formation region 62 is not formed in the frame portion 29 and the frame-side conductor layer 54 covers the substantial integral region of the frame portion 29.

Then, the measurement samples (of the example and the comparative example) are heated to cause the respective solder bumps 130 formed on the terminal pads 52 to reflow. The amount of warpage occurring in each of the measurement samples is measured. Specifically, each of the measurement samples is disposed on a support bed (not shown), and measures the height from the surface of the support base to the point at which the measurement sample has the maximum rising distance as the amount of warpage. .

As a result of the measurement of the warpage, the amount of warpage in the intermediate product 151 of the comparative example was 2.458 mm, whereas the amount of warpage in the intermediate product 12 of this example (that is, according to the second exemplary embodiment) was 0.464 mm. Therefore, the amount of warpage in the intermediate product 12 of this embodiment is determined to be smaller than the amount of warpage in the intermediate product 151 of the comparative example. Therefore, it is shown that the arrangement of the plurality of non-formation regions 62 in the frame portion 29 makes it difficult to cause warpage in the intermediate article.

According to this second exemplary embodiment, the following advantages can be obtained.

(1) In the intermediate product 12 of the coreless wiring board 101 of the second exemplary embodiment, the first area ratio of the first conductor layer to the product forming region 28 is made by arranging the plurality of non-formation regions 62 The second conductor layer (the frame side conductor layer 54) has the second area ratio of the frame portion 29 being equal to each other. Therefore, the difference in thermal expansion coefficient between the product forming region 28 and the frame portion 29 is lowered. Therefore, if thermal stress caused by the difference in thermal expansion coefficient is applied to the intermediate product 12 during cooling of the solder bumps 130 for connecting the IC wafer 131, warpage hardly occurs in the intermediate product 12. . Therefore, the yield of the article (the coreless wiring board 101) produced by the intermediate products 12 can be improved.

(2) In the second exemplary embodiment, the first conductor layers (the conductor layer 51 and the terminal pad 52) are patterned on each of the resin insulating layers 41 to 44, and the frames are The side conductor layers 54 (and the non-formation regions 62) are simultaneously patterned, and thus the process of manufacturing the coreless wiring board 101 can be shortened. Moreover, the non-formed regions 62 have a relatively simple shape, such as a slit shape. Therefore, the burden of pattern design can be alleviated, making it easy to prevent an increase in the cost of the coreless wiring board 101.

This second exemplary embodiment can also be changed in the following manner.

In the intermediate article 12 of the coreless wiring board 101 of the second exemplary embodiment, all of the plurality of non-formed regions 62 are formed as slit-shaped regions, each of the regions being extended by the respective tangent lines 121. extend. However, the non-formed regions provided on the corner portions 31 may have shapes different from the slit-shaped non-formed regions 62. Figures 21 and 23 show intermediate articles 110 and 161 in accordance with variations of the second exemplary embodiment. In the intermediate product 110 shown in Fig. 21, the non-formation regions 112 provided on the corner portions 31 extend over the entire region of the respective corner portions 31. Further, in the intermediate product 161 shown in Fig. 23, the non-formation regions 162 provided on the corner portions 31 extend into the entire region of the corner portions 31.

Although the non-formation region 62 of the second exemplary embodiment is disposed on the extension of the tangent 121 set along the outline 120 of the product portion 27 of the frame portion 29, portions of the non-formation regions 62 may also be configured. In the direction of the main surface of the intermediate article 110, 161 as shown in Figs. 21 and 23, the position where the tangential lines 121 extend is separated.

In the intermediate product 12 of the coreless wiring board 101 of the second exemplary embodiment, the frame side conductor layer 54 is formed in the frame portion 29 in a planar form. However, the frame side conductor layer may have a shape different from the frame side conductor layer 54. Figures 22 through 24 show intermediate articles 161, 171 and 181. In the intermediate product 171 shown in Fig. 22, a frame-side conductor layer 172 having a mesh-like pattern is formed in the frame portion 29. In the intermediate product 161 shown in Fig. 23, a frame-side conductor layer 163 having a brick form is formed in the frame portion 29. In the intermediate product 181 shown in Fig. 24, a frame-side conductor layer 182 having a wave pattern is formed in the frame portion 29.

Furthermore, the first and second exemplary embodiments can be modified as follows.

In the method of manufacturing the coreless wiring board 101 of the first and second exemplary embodiments, the solder bumps 130 for connecting the IC chips are respectively formed on the resin insulating layer 44 formed on the outermost layer. On the terminal pad 52. However, the terminal pads 52 can be BGA pads to be deviced to another connection component, such as a motherboard, and solder bumps can be formed on the respective BGA pads. In this case, a terminal pad for connecting the IC chip may be provided on the back surface 103 of the stacked wiring area 81.

In the first conductor layer forming process of the first and second exemplary embodiments, the copper foil 73 is patterned by etching to form the BGA pads 53. However, after the removal of the copper foil 73 by etching, the BGA pads 53 may be formed separately.

In the stacking process of the first and second exemplary embodiments, the resin insulating layer 41 may be formed after the metal layer of the BGA pads 53 has been formed on the copper foil 73. In this case, after the via holes 146 for exposing the metal layer are formed in the resin insulating layer 41, the via conductors 147 are formed in the respective via holes 146. As described above, after the conductive conductors are formed, the copper foil 73 is completely removed by etching to expose the metal layer, and the metal layer can be formed as the BGA pad 53.

Those skilled in the art will recognize that additional steps and architectures are possible without departing from the teachings of the present invention. The detailed description and specific details of the exemplary embodiments disclosed herein are intended to provide a The disclosure will become apparent to those skilled in the art, and may be made without departing from the spirit or scope of the claimed invention.

The scope of the invention, therefore, is defined by the scope of the appended claims

11, 12, 110, 151, 161, 171, 181. . . Intermediate product

27. . . Product department

28. . . Product formation area

29. . . Frame

30. . . Ends

31. . . Corner

40. . . Chip insulation resin bottom assembly

41~44. . . Resin insulation

51. . . Conductor layer

52. . . Terminal pad

53. . . BGA pad

54, 163, 172, 182. . . Frame side conductor layer

60. . . Extended hole

61. . . Slit

62. . . Non-formed zone

69. . . Bottom component

70. . . Support plate

71. . . Plate resin insulation

72. . . Multi-layer sheet metal assembly

73~74. . . Copper foil

80. . . Multilayer product

81. . . Stacked wiring area

82. . . Block

83. . . Surrounding part

101. . . Coreless patch panel

102. . . Front without core wiring board

103. . . Back of coreless patch panel

111. . . Intermediate product

112. . . Cut

120. . . contour line

121. . . Tangent

128. . . Solder resist

129, 145. . . Opening

130, 155. . . Solder bump

131. . . IC chip

132. . . Connection terminal

133. . . IC wafer assembly area

142. . . Solder resist

146. . . Via

147. . . Conduction conductor

1 is a schematic cross-sectional view showing a coreless wiring board of the first and second exemplary embodiments of the present invention;

2 is a plan view showing an intermediate product of a coreless wiring board according to the first exemplary embodiment;

Figure 3 is a cross-sectional view taken along line A-A shown in Figure 2;

4 is a structural view showing a member at a point in a method of manufacturing a coreless wiring board according to the first exemplary embodiment;

Figure 5 is a structural view showing a member at another point in the method of manufacturing a coreless wiring board according to the first exemplary embodiment;

6 is a structural view showing a member at another point in a method of manufacturing a coreless wiring board according to the first exemplary embodiment;

Figure 7 is a structural view showing a member at another point in the method of manufacturing a coreless wiring board according to the first exemplary embodiment;

8 is a structural view showing a member at another point in a method of manufacturing a coreless wiring board according to the first exemplary embodiment;

Figure 9 is a structural view showing a member at another point in the method of manufacturing a coreless wiring board according to the first exemplary embodiment;

Figure 10 is a structural view showing a member at another point in the method of manufacturing a coreless wiring board according to the first exemplary embodiment;

11 is a structural view showing a member at another point in a method of manufacturing a coreless wiring board according to the first exemplary embodiment;

Figure 12 is a structural view showing a member at another point in the method of manufacturing a coreless wiring board according to the first exemplary embodiment;

Figure 13 is a structural view showing a member at another point in the method of manufacturing a coreless wiring board according to the first exemplary embodiment;

Figure 14 is a structural view showing a member at another point in the method of manufacturing a coreless wiring board according to the first exemplary embodiment;

Figure 15 is a structural view showing a member at another point in a method of manufacturing a coreless wiring board according to the first exemplary embodiment;

Figure 16 is a plan view showing an intermediate product of a coreless wiring board of a variant of the first exemplary embodiment;

Figure 17 is a plan view showing an intermediate product of a coreless wiring board according to a second exemplary embodiment;

Figure 18 is a structural view showing a member at a point in a method of manufacturing a coreless wiring board in accordance with a second exemplary embodiment;

Figure 19 is a structural view showing a member at another point in the method of manufacturing a coreless wiring board according to the second exemplary embodiment;

Figure 20 is a plan view showing an intermediate product of a coreless wiring board of a comparative example;

Figure 21 is a plan view showing an intermediate product of a coreless wiring board according to a modification of the second exemplary embodiment;

Figure 22 is a plan view showing an intermediate product of a coreless wiring board according to another modification of the second exemplary embodiment;

Figure 23 is a plan view showing an intermediate product of a coreless wiring board according to still another modification of the second exemplary embodiment;

Fig. 24 is a plan view schematically showing an intermediate product of a coreless wiring board according to another modification of the second exemplary embodiment.

11. . . Intermediate product

27. . . Product department

28. . . Product formation area

29. . . Frame

30. . . Ends

31. . . Corner

51. . . Conductor layer

54. . . Frame side conductor layer

61. . . Slit

120. . . contour line

121. . . Tangent

130. . . Solder bump

Claims (19)

An intermediate multilayer wiring board product comprising: a stack of a plurality of resin insulating layers, the stack comprising: a product forming region comprising a plurality of product portions disposed along a main surface of the stack, each of the plurality of product portions becoming the plurality of layers a product of the wiring board; and a frame portion surrounding the product forming region; a first conductor layer formed on at least one of the plurality of resin insulating layers in each of the plurality of product portions; and a second conductor layer Forming at least one of the plurality of resin insulating layers in the frame portion; wherein the frame portion has a plurality of cuts that completely pass through the frame portion in a thickness direction thereof, the plurality of cut portions being substantially Equally spaced configuration. The intermediate multilayer wiring board product of claim 1, wherein at least one of the plurality of cut portions is a slit, and the extended tangent is set along a contour line of each of the plurality of product portions. (extension of a cutting line) extending, and having a width substantially equal to the spacing between contour lines of adjacent article portions. An intermediate multilayer wiring board article according to claim 1 or 2, wherein the frame portion has a plurality of edge portions surrounding the product forming region, and each of the plurality of corner portions connecting the adjacent end portions ( Corner portion), and At least one of the plurality of cut portions is disposed in at least one of the plurality of corner portions formed by removing a corresponding corner portion. The intermediate multilayer wiring board article of claim 1 or 2, wherein the plurality of cut portions are formed after forming the first conductor layer and the second conductor layer. An intermediate multilayer wiring board article according to claim 1 or 2, further comprising a solder bump for connecting a member provided on the first conductor layer formed on the outermost resin insulating layer of the stack. The intermediate multilayer wiring board product of claim 1 or 2, wherein the multilayer wiring board comprises: the plurality of resin insulating layers and the plurality of first conductor layers alternately stacked, wherein each of the plurality of resin insulating layers They are made of the same type of resin insulating layer, and wherein the plurality of first conductor layers are connected through via holes that are diametrically enlarged in one direction. An intermediate multilayer wiring board product comprising: a stack of a plurality of resin insulating layers, the stack comprising: a product forming region comprising a plurality of product portions disposed along a main surface of the stack, each of the plurality of product portions becoming the a product of the multilayer wiring board; and a frame portion surrounding the product forming region; a first conductor layer formed on at least one of the plurality of resin insulating layers in each of the plurality of product portions; and a second conductor a layer, except for a plurality of non-formed regions disposed in the frame portion Further, the second conductor layer is formed on at least one of the plurality of resin insulating layers in the frame portion such that a first area ratio of the first conductor layer to the article forming region is substantially equal to the second conductor layer pair a second area ratio of the frame portion, wherein at least one of the plurality of non-formed regions has a slit shape extending along an extended tangent set by a contour line of each of the plurality of product portions, and wherein At least one of the plurality of non-formed regions having a slit shape extends to an outer end of the frame portion. The intermediate multilayer wiring board article of claim 7, wherein each of the plurality of second conductor layers is formed on each of the plurality of resin insulating layers except for the plurality of non-formed regions, The first area ratio and the second area ratio are made equal to each other in each of the plurality of resin insulating layers. An intermediate multilayer wiring board product according to claim 7 or 8, wherein the frame portion has a plurality of end portions surrounding the product forming region, and a plurality of corner portions each connecting adjacent end portions, and the same At least one of the plurality of non-formed regions is disposed in at least one of the plurality of corner portions to occupy the entire area of the corresponding corner portion. The intermediate multilayer wiring board article of claim 7 or 8, wherein the second conductor layer has a meshed pattern to have a second area ratio equal to the first area ratio. An intermediate multilayer wiring board product according to claim 7 or 8, wherein the multilayer wiring board comprises: the plurality of resin stacked alternately An insulating layer and a plurality of first conductor layers, wherein each of the plurality of resin insulating layers is made of the same type of resin insulating layer, and wherein the plurality of first conductor layers are transparently expanded in one direction Holes to connect. A method of manufacturing a multilayer wiring board, comprising: a preparation process comprising an intermediate product for preparing a multilayer wiring board, the intermediate product comprising: a stack of a plurality of resin insulating layers, the stack comprising: an article forming region including a main surface along the stack a plurality of product parts, each of the plurality of product parts will be a product of the multilayer wiring board; and a frame portion surrounding the product forming area; and a first conductor layer formed in each of the plurality of product parts And at least one of the plurality of resin insulating layers; and a second conductor layer formed on at least one of the plurality of resin insulating layers in the frame portion; and a cutting portion forming process including forming a plurality of cut portions The frame portion of the intermediate product is passed through the frame portion in the thickness direction thereof. The method of claim 12, wherein the plurality of cut portions are disposed substantially at equal intervals. The method of claim 12, wherein the preparation process comprises: a stacking process comprising stacking the plurality of resin insulating layers on one surface of the bottom component, wherein the bottom component comprises a layer formed on the bottom a metal foil on the surface; a bottom component removal process comprising removing the bottom component after the stacking process to expose the metal foil; the first conductor layer forming process comprising patterning the bottom component removal process a metal foil to form the first conductor layer in the plurality of product portions on the outermost resin insulating layer of the stack; and a solder bump forming process included in the first conductor after the first conductor layer forming process Solder bumps are formed on the layer, the solder bumps are used to connect a member; and wherein the cut portion forming process is performed after the first conductor layer forming process. The method of claim 14, wherein the cut forming process is performed prior to the solder bump forming process. The method of claim 12, wherein the multilayer wiring board comprises: the plurality of resin insulating layers and the plurality of first conductor layers alternately stacked, wherein each of the plurality of resin insulating layers is of the same type The resin insulating layer is formed, and wherein the plurality of first conductor layers are connected by via holes that are enlarged in diameter in one direction. A method of manufacturing a multilayer wiring board, comprising: a preparation process comprising: an intermediate product for preparing a multilayer wiring board, the intermediate product comprising: a stack of a plurality of resin insulating layers, the stack comprising: a product forming region, a plurality of product portions disposed along a major surface of the stack, each of the plurality of product portions being a product of the multilayer wiring board; and a frame portion surrounding the product forming region; a first conductor layer formed on the And at least one of the plurality of resin insulating layers in each of the plurality of product portions; and the second conductor layer, the second conductor layer being formed on the plurality of non-formed regions disposed in the frame portion At least one of the plurality of resin insulating layers in the frame portion such that a first area ratio of the first conductor layer to the article forming region is substantially equal to a second area ratio of the second conductor layer to the frame portion; The separation process includes removing the frame from the article forming region and cutting the article forming region along a tangential line to separate the plurality of article portions from each other. The method of claim 17, wherein the preparation process comprises: a stacking process comprising stacking the plurality of resin insulating layers on one surface of the bottom component, wherein the bottom component comprises a metal formed on the surface a foil; a bottom component removal process comprising removing the bottom component after the stacking process to expose the metal foil; the first conductor layer forming process comprising patterning the metal foil after the bottom component removal process Forming the first conductor layer in the plurality of product portions on the outermost resin insulating layer of the stack; and solder bump forming process included in the first conductor layer forming process Thereafter, solder bumps are formed on the first conductor layer, and the solder bumps are used to connect a member. The method of claim 17 or 18, wherein the multilayer wiring board comprises: the plurality of resin insulating layers and the plurality of first conductor layers alternately stacked, wherein each of the plurality of resin insulating layers is of the same type The resin insulating layer is formed, and wherein the plurality of first conductor layers are connected by via holes that are enlarged in diameter in one direction.