KR100815322B1 - Printed circuit board and fabricating method of the same - Google Patents

Abstract

A printed circuit board and a method for manufacturing the same are provided to prevent an electric error by preventing a bonding material from flowing inside a via-hole when housing is attached to protect a semiconductor chip by forming a PIC(Photo Imageable Coverlay) to cover a half of a side contact hole. A printed circuit board includes a first insulation layer(102), a first circuit pattern(104), a second insulation layer(106), a second circuit pattern, and a PIC(Photo Imageable Coverlay). The first circuit pattern is formed on both sides of the first insulation layer. The second insulation layer is stacked on both sides of the first insulation layer. The second circuit pattern is formed on a top and a bottom of the second insulation layer. The PIC is stacked on the remained second circuit pattern except a wire bonding pad of the second circuit pattern formed on a top of the second insulation layer of the circuit region. The PIC is formed for a half of a side contact hole to be opened.

Description

Printed Circuit Board and Fabricating Method of the same

1 is a cross-sectional view showing a printed circuit board according to the prior art.

2 is a cross-sectional view of a printed circuit board according to an exemplary embodiment of the present invention.

3A to 3H are cross-sectional views illustrating a method for manufacturing a printed circuit board according to an exemplary embodiment of the present invention illustrated in FIG. 2.

<Explanation of symbols for the main parts of the drawings>

2, 6, 102, 106: insulation layer 4, 10, 104, 110: circuit pattern

8, 108: via hole 12, 112: solder resist

16, 116: gold-plated layer 114: PIC

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board and a method for manufacturing the same, and more particularly, to a printed circuit board and a method for manufacturing the same, wherein the PIC is formed to cover 1/2 of the side contact hole to prevent electrical defects of the side contact hole due to the bonding material. It is about.

In recent years, semiconductor devices called integrated circuits are mainly used in electronic devices. Such a semiconductor chip is mounted on a substrate to be physically supported and electrically connected to other elements of the substrate circuit.

In particular, the size of a semiconductor chip is smaller, the lead of the chip is also smaller, and the spacing of the leads is also reduced as the lighter and shorter of the electronic product of the electronic product is reduced.

As a result, the conventional printed circuit board (Printed Circuit Board) has a problem that such a semiconductor chip can not be mounted directly on the substrate.

It is an application package that emerged to solve this problem. Such an application package is currently applied to a product, and research on various packages is being actively conducted.

1 is a view showing a conventional printed circuit board.

Referring to FIG. 1, a conventional printed circuit board includes a first circuit pattern 10 formed on both surfaces of a first insulating layer 2, and a second insulating layer 6 stacked on both sides of a first insulating layer 2. , The second circuit pattern 10 formed on the upper and lower portions of the second insulating layer 6 and the second circuit pattern except the wire bonding pads of the second circuit pattern 10 on the second insulating layer 6 ( In order to protect 10), the solder resist 12 and the gold plating layer 16 formed on the wire bonding pad are included on the second circuit pattern 10 except for the wire bonding pad.

In the conventional printed circuit board, a semiconductor chip such as an image sensor or an integrated circuit (IC) is attached to the solder resist 12 on the second circuit pattern 10 formed between the wire bonding pad and the wire bonding pad. The wire of the chip is attached to the wire bonding pad, and a housing for protecting the semiconductor chip is attached to the solder resist formed around the via hole 8 which is a side contact hole by the bonding material.

However, the conventional printed circuit board has a problem in that when the housing is attached, the bonding material flows into the side contact hole, that is, the via hole 8, and electrical defects are generated by the bonding material.

Accordingly, an object of the present invention is to provide a printed circuit board and a method of manufacturing the same that can prevent electrical defects of side contact holes caused by bonding materials.

In order to achieve the above object, a printed circuit board according to an embodiment of the present invention includes a circuit region to which a semiconductor chip is attached and a dummy region formed on both sides of the circuit region, and a side contact between the circuit region and the dummy region. A printed circuit board having holes, comprising: first circuit patterns formed on both surfaces of a first insulating layer; A second insulating layer laminated on both surfaces of the first insulating layer; Second circuit patterns formed on and under the second insulating layer; And a PIC (Photo Imageable Coverlay) stacked on a second circuit pattern except for a wire bonding pad among second circuit patterns formed on the second insulating layer in the circuit region, wherein the PIC includes one of the side contact holes. It is characterized in that the / 2 is formed to be open.

According to an embodiment of the present invention, a method of manufacturing a printed circuit board includes: (a) forming a first circuit pattern on both surfaces of a first insulating layer and then stacking a second insulating layer on both sides of the first insulating layer; (b) forming side contact holes in the first insulating layer and the second insulating layer to separate the circuit region and the dummy region; (c) forming second circuit patterns on the upper and lower portions of the second insulating layer and electrically connecting inner walls of the side contact holes; (d) stacking a PIC (Photo Imageable Coverlay) on the second circuit pattern formed on the second insulating layer; (e) removing the PIC so that half of the side contact holes are open; And (f) removing the dummy region.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating a printed circuit board according to an exemplary embodiment of the present invention.

Referring to FIG. 2, a printed circuit board according to an exemplary embodiment of the present invention may include a first circuit pattern 104 formed on both surfaces of the first insulating layer 102 and a second stacked on both sides of the first insulating layer 102. The wire bonding pads of the second circuit patterns 110a and 110b formed on the insulating layer 106, the second insulating layer 106, and the second circuit pattern 110a on the second insulating layer 106 are disposed. In order to protect the remaining second circuit patterns 110a except for the second circuit pattern 110a on the second insulating layer 106, a photosensitive film, that is, a PIC (Photo Imageable Coverlay) stacked on the remaining circuit patterns except for the wire bonding pads. (114).

In this case, the PIC 114 is formed such that a side contact hole, that is, the via hole 108 is opened by about 1/2. In addition, the printed circuit board according to an exemplary embodiment of the present invention further includes a gold plating layer 116 formed on the inner surface of the via hole 108, that is, the wire bonding pad and the side contact hole, that is, the second circuit pattern 110a.

In the printed circuit board according to the exemplary embodiment of the present invention, the second circuit pattern 110b formed below the second insulating layer 106 is formed on the second circuit pattern 110b formed below the second insulating layer 106. Solder resist 112 is formed to protect.

In this case, the PIC 114 may be formed instead of the solder resist 112.

As described above, since the PIC 114 is formed to cover the side contact hole by about 1/2, the printed circuit board according to the embodiment of the present invention may be formed on the second circuit pattern 110a formed between the wire bonding pad and the wire bonding pad. When a semiconductor chip such as an image sensor or integrated circuit (IC) is attached on the PIC 114, a wire of the semiconductor chip is attached to a wire bonding pad, and a housing for protecting the semiconductor chip is attached on the PIC 114. Can be prevented from flowing into the side contact hole.

Accordingly, the printed circuit board according to the embodiment of the present invention can prevent the electrical defects caused by the bonding material in the side contact hole, that is, the via hole 108.

3A to 3H are cross-sectional views illustrating a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention illustrated in FIG. 2.

First, a copper clad laminate (hereinafter referred to as "CCL") having copper foil interposed on both surfaces of the first insulating layer 102 is prepared, and then the first insulating layer (as shown in FIG. 3A) through an image forming process. First circuit patterns 104, which are inner circuit patterns, are formed on both surfaces of 102.

Here, the first insulating layer 102 is any one of Ajinomoto Build-up Film (ABF), prepreg, polyimide, FR-4.

At this time, the first circuit pattern 104 is formed by the following method.

First, after applying a dry film on the copper foil interposed on both sides of the first insulating layer 102, the dry film of the remaining portion except for the first circuit pattern is removed through an exposure and development process.

Then, the part from which the dry film was removed is etched with etching liquid, and the dry film is removed and the copper foil of the exposed part is removed.

After removing the copper foil, the dry film remaining on the first circuit pattern is removed to form the first circuit pattern.

In addition, the first circuit pattern 104 may be formed by the following method.

First, after applying a dry film on the copper foil interposed on both surfaces of the first insulating layer 102, the dry film of the portion where the first circuit pattern is to be formed through an exposure and development process.

Thereafter, an electrolytic copper plating layer is formed on the copper foil from which the dry film is removed through an electrolytic copper plating process.

After forming an electrolytic copper plating layer, the dry film which remains on copper foil is removed, and the copper foil of the part from which the dry film was removed with the etching liquid is removed, and a 1st circuit pattern is formed.

The first circuit pattern forming method has been described above, but the first circuit pattern may be formed by the same method as the second circuit pattern formed later.

After the first circuit pattern 104 is formed, the second insulating layer 106 is placed on the first insulating layer 102 on which the first circuit pattern 104 is formed, and then heated and pressed by a press to form the first insulating layer 102. The second insulating layer 106 is laminated on both surfaces of the substrate.

In this case, the single-sided copper laminated board having copper foil interposed on one surface of the second insulating layer 106 may be laminated on both surfaces of the first insulating layer 102.

Here, the second insulating layer 106 is any one of Ajinomoto Build-up Film (ABF), prepreg, polyimide, FR-4.

After stacking the second insulating layer 106, the first insulating layer as shown in FIG. 3B using a Computer Numerical Control (CNC) drill to electrically conduct the upper and lower portions of the second insulating layer 106. A via hole 108 penetrating through the 102 and the second insulating layer 106 is formed.

At this time, the printed circuit board between the via hole 108 and the via hole 108 is used as the circuit region 210 to which a semiconductor chip or component is attached on the second circuit pattern to be formed on the second insulating layer 106. The left and right printed circuit boards of the region 210 are used as the dummy region 200 which is removed when the component is attached. Detailed description thereof will be described later.

After the via hole 108 is formed, a deburring process is performed to remove burrs of the copper foil generated by the drilling process when the via hole 108 is formed. Remove foreign substances.

Thereafter, a seed layer is formed on the upper and lower portions of the second insulating layer 106 and the inner wall of the via hole 108 through an electroless copper plating process.

After the seed layer is formed, the dry film is coated on the seed layer, and then the dry film of the portion where the second circuit patterns 110a and 110b, which are the outer circuit patterns, are formed through the exposure and development processes.

Thereafter, the electrolytic copper plating layer is formed on the seed layer by an electrolytic copper plating process, and then the dry film remaining on the seed layer is removed.

After removing the dry film on the seed layer, the dry film is removed to remove the exposed seed layer with an etchant to form second circuit patterns 110a and 110b.

At this time, when the cross-sectional copper clad laminate in which copper foil is laminated on the second insulating layer 106 is laminated on both surfaces of the first insulating layer 102, the second circuit patterns 110a and 110b may form the first circuit pattern 104. Is formed by.

After the second circuit patterns 110a and 110b are formed, the solder resist 112 is coated on the second circuit pattern 110b formed under the second insulating layer 106. Here, the solder resist 112 means a "coating which covers the circuit pattern of the printed circuit board and prevents unwanted connection by soldering when the component is mounted", and the protection material and the circuit which protect the circuit pattern of the printed circuit board. It serves to provide insulation.

Subsequently, the artwork film having the solder resist pattern formed thereon is brought into close contact with the solder resist 112 and then exposed and developed to form a second circuit pattern 110b formed under the second insulating layer 106 as shown in FIG. 3D. An opening is formed so that a part of) is exposed.

At this time, the PIC is deposited instead of the solder resist 112 on the second circuit pattern 110b formed under the second insulating layer 106 to expose the second insulating layer 106 as shown in FIG. 3D through an exposure and development process. An opening may be formed to expose a portion of the second circuit pattern 110b formed under the bottom of the substrate.

After stacking the solder resist 112 on the second circuit pattern 110b formed below the second insulating layer 106, the second circuit formed on the second insulating layer 106 as shown in FIG. 3E. The PIC 114 is stacked on the pattern 110a.

At this time, the PIC 114 is formed to a thickness of about 40㎛ to 50㎛.

Thereafter, as shown in FIG. 3F, the PIC 114 is removed on the second circuit pattern used as the wire bonding pad among the second circuit patterns 110a formed on the second insulating layer 106 through the exposure and development processes. do.

At this time, the PIC 114 is removed to open about one half of the via hole 108 used as a side contact hole.

Here, the reason why the PIC 114 is formed so that about one half of the via hole 108 is opened is that when the electrolytic gold plating is performed on the wire bonding pad, the electrolytic gold plating liquid is smoothly flown, and the hole cracks when side contact hole processing is performed. This is to prevent cracks from occurring.

The solder resist 112 and the PIC 114 described above may be formed on the upper and lower portions of the second insulating layer 106 at the same time.

Thereafter, as illustrated in FIG. 3G, the gold plating layer 116 is formed on the wire bonding pad of the second circuit patterns 110a formed on the second insulating layer 106 through the electroplating process. In this case, the gold plating layer 116 is formed not only on the wire bonding pad but also on the circuit pattern formed in the via hole 108 and the inner wall of the via hole 108.

After the gold plating layer 116 is formed, the dummy region 200 is removed using a cutter as shown in FIG. 3H.

Subsequently, a semiconductor chip such as an image sensor or an integrated circuit (IC) is attached to the PIC 114 formed between the wire bonding pad and the wire bonding pad in the second circuit pattern 110a by using an adhesive.

The wire of the semiconductor chip is attached to the wire bonding pad.

After attaching the semiconductor chip, a bonding material is coated on the PIC 114 formed to cover 1/2 of the side contact hole, that is, the via hole 108, to protect the semiconductor chip, and then attach the housing.

In the method of manufacturing a printed circuit board according to the embodiment of the present invention described above, a multilayer structure having a first circuit pattern 104 as an inner circuit pattern and a second circuit pattern 110a and 110b as an outer circuit pattern is formed. In addition to forming a single layer structure in which only one circuit pattern 104 is formed, a plurality of insulating layers and circuit patterns may be further formed on the second circuit patterns 110a and 110b according to the use of the printed circuit board.

As described above, in the method of manufacturing the printed circuit board according to the embodiment of the present invention, the PIC 114 is formed to cover the half of the side contact hole, that is, the via hole 108, so that the bonding material is attached when the housing is attached to protect the semiconductor chip. By preventing flow into the via hole 108, electrical defects caused by the bonding material may be prevented.

In addition, in the method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention, the PIC 114 is formed to cover one half of the side contact hole, that is, the via hole 108. It is possible to smooth the flow of the electrolytic gold plating solution.

In addition, in the method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention, the printed circuit board may be manufactured by an existing process by using PIC.

As described above, the present invention can prevent the electrical defects caused by the bonding material by forming the PIC to cover half of the side contact hole to prevent the bonding material from flowing into the via hole when the housing is attached to protect the semiconductor chip. have.

In addition, the present invention can facilitate the flow of the electrolytic gold plating solution in the via hole during the electrolytic gold plating process by forming a PIC to cover 1/2 of the side contact hole.

In addition, the present invention can manufacture a printed circuit board by the existing process by using the PIC.

Claims (6)

A printed circuit board comprising a circuit region to which a semiconductor chip is attached and a dummy region formed at both sides of the circuit region, wherein side contact holes are formed between the circuit region and the dummy region. First circuit patterns formed on both surfaces of the first insulating layer; A second insulating layer laminated on both surfaces of the first insulating layer; Second circuit patterns formed on and under the second insulating layer; And A PIC (Photo Imageable Coverlay) stacked on a second circuit pattern except for a wire bonding pad among second circuit patterns formed on the second insulating layer in the circuit region; The PIC is formed so that half of the side contact hole is open. The method of claim 1, The second circuit pattern formed under the second insulating layer of the circuit area is protected by a solder resist. The method of claim 1, And the second circuit pattern formed under the second insulating layer in the circuit area is protected by the PIC. (a) forming a first circuit pattern on both sides of the first insulating layer and then laminating a second insulating layer on both sides of the first insulating layer; (b) forming side contact holes in the first insulating layer and the second insulating layer to separate the circuit region and the dummy region; (c) forming second circuit patterns on the upper and lower portions of the second insulating layer and electrically connecting inner walls of the side contact holes; (d) stacking a PIC (Photo Imageable Coverlay) on the second circuit pattern formed on the second insulating layer; (e) removing the PIC so that half of the side contact holes are open; And (f) removing the dummy region. The method of claim 4, wherein After the step (c), applying a solder resist on the second circuit pattern formed below the second insulating layer; And removing the solder resist applied on the second circuit pattern of the dummy region. The method of claim 4, wherein Step (d) may include depositing PIC under the second insulating layer; And And removing the PIC on the second circuit pattern of the dummy region.

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