TWI473230B - Package substrate for optically detecting opening shift of solder mask within tolerance range - Google Patents

Description

Optically detecting the package substrate with the gap of the solder mask opening within the allowable range

The present invention relates to a carrier for an electronic component, and more particularly to a package substrate that optically detects that the opening of the solder mask is within an allowable range, and can be used in a semiconductor package structure.

The package substrate is generally used as a carrier for carrying electronic components in a semiconductor package structure, for example, for carrying a wafer, a micro-chip package structure or a passive component, etc., and the type thereof may be a substrate panel or a substrate strip. The surface of the substrate is usually covered with a layer of solder mask to protect the line solder mask layer. However, in the manufacturing process of the substrate, the solder mask layer must be patterned to make a solder mask opening that can expose the wiring layer pads. However, in actual substrate manufacturing, the solder mask opening has an offset value, which is in the original design. Displacement of the pads to be aligned, once the tolerance of the gap of the solder mask opening is exceeded, causes electrical connection failure or/and abnormality of the pads. This problem will be more serious with the micro-pitch of the pads and the miniaturization of the opening of the solder mask. This is because the allowable range of the gap opening of the solder mask will be relatively small, but currently there is no one that can be easily and quickly. The detection method is used to determine whether the actual offset value of the shroud opening is within the tolerance of the offset.

In order to solve the above problems, the main object of the present invention is to provide a package substrate which can optically detect the deviation of the opening of the solder mask within an allowable range, and can easily judge whether the offset value of the gap of the solder mask is allowed by visual inspection or optical instrument. Within the scope.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a package substrate capable of optically detecting that the opening of the solder mask is within an allowable range, comprising a substrate body, a circuit layer, and a solder mask layer, wherein the circuit layer is formed on a surface of the substrate body, The circuit layer includes at least one pad. The solder mask layer is formed on the surface of the substrate body and the circuit layer, and the solder mask layer has at least one solder mask opening, which exposes the pad. Wherein, the circuit layer further comprises a detection pad, and the solder mask layer comprises a solder mask island corresponding in shape and aligned with the detection pad, and the intermediate point distance between the detection pad and the pad is one The first pitch, the intermediate point distance between the solder mask island and the solder mask opening is a second pitch, the first pitch is equal to the second pitch, and the coverage area of the solder mask island is Slightly larger than the test pad to completely cover the test pad within the tolerance of the weld cap opening.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing package substrate, the wiring layer may further include a plating conductive line connected to the detecting pad.

In the foregoing package substrate, a plating layer may be further formed on the pad, and the plating layer is not formed on the detecting pad, and the offset of the soldering cap opening relative to the pad is at the Within the offset tolerance range.

In the above package substrate, the solder mask island may be formed in one of the ring grooves of the solder mask layer.

In the foregoing package substrate, the solder mask layer may further have a connecting portion connected to the solder mask island through the annular groove and covering a portion of the plating conductive wire passing through the annular groove.

In the above package substrate, the solder mask island and the detection pad may both be square, and the solder mask island has a length equal to the corresponding length of the detection pad plus twice the tolerance of the offset.

In the above package substrate, the solder mask island and the detection pad may each have a circular shape, and the solder mask island has a diameter equal to a corresponding diameter of the detection pad plus twice the tolerance range of the offset.

In the foregoing package substrate, the substrate main system may include at least one unit area and a frame area, and the pad and the solder mask opening may be located in the unit area, and the detecting pad and the solder mask island may be located. The border area.

In the foregoing package substrate, the detection pad and the solder mask island may be located at a corner of the frame region.

In the foregoing package substrate, the solder mask opening may be smaller than the pad so that the pad is a solder mask defining pad (SMD pad).

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

According to a first preferred embodiment of the present invention, a package substrate capable of optically detecting that the opening of the solder mask is within an allowable range is illustrated in a partial cross-sectional view of FIG. 1, a surface view of FIG. 2, and a third diagram. A partially enlarged schematic view of a welded island. The package substrate 100 mainly includes a substrate body 110, a circuit layer 120, and a solder mask layer 130.

The substrate body 110 is a main structure of the package substrate 100 and may include at least one core layer such as BT resin, FR-3 resin or FR-4 resin. When the package substrate 100 is a two-layer or more multi-layer board structure, at least one of the circuit layer, the ground layer or the power layer and the appropriate plated through hole or/and the conduction blind hole may be interposed in the substrate body 110; In the layer structure, the inside of the substrate body 110 may be provided with plated through holes that are vertically connected; when it is a single layer plate structure, the inside of the substrate body 110 is not provided with a metal layer and plated through holes. Typically, the substrate body 110 is a wafer carrier during the fabrication of the semiconductor package construction.

The circuit layer 120 is formed on one surface 111 of the substrate body 110, and the circuit layer 120 includes at least one pad 121. When the surface 111 is an outer surface of the semiconductor package structure, the pad 121 can be a ball pad or a contact pad; when the surface 111 is an inner surface of the semiconductor package structure, the pad 121 It can be a finger or a bump pad. The circuit layer 120 can be formed by pattern etching using a pressed copper foil, or the wiring layer 120 can be formed by a patterned dry film plating.

The solder mask layer 130 is formed on the surface 111 of the substrate body 110 and the circuit layer 120. The solder mask layer 130 is an electrically insulating surface protection layer and can be patterned by exposure and development techniques. The solder mask layer 130 has at least one solder mask opening 131 that exposes the pads 121. In this embodiment, the solder mask opening 131 can be smaller than the pad 121, so that the pad 121 is a solder mask defining pad (SMD pad), so in the pad type, the soldering cap opening 131 The degree of offset will directly affect the electrical connection position and joint area of the pad 121.

The circuit layer 120 further includes at least one detecting pad 122. The distance between the detecting pad 122 and the pad 121 is fixed and indicates that both are formed at the same time, and the solder mask layer 130 includes a shape corresponding position and position. The soldering islands 132 of the detecting pads 122 are aligned, and the distance between the soldering islands 132 and the soldering mask openings 131 is fixed and the two are formed at the same time. Further, the detecting pads 122 are paired with the soldering islands 132. Matching is more appropriate. Specifically, the intermediate point between the detecting pad 122 and the pad 121 is a first pitch D1, and the intermediate point between the welding pad island 132 and the welding cap opening 131 is a first The two pitches D2 are equal to the second pitch D2, and the coverage area of the solder mask island 132 is slightly larger than the detection pad 122 to allow the offset range A of the solder mask opening 131. The detection pad 122 is completely covered inside. Depending on the product design, the tolerance range A of the solder mask opening 131 may be between 0.1 and 50 micrometers (um), preferably not more than one-half of the pitch of the pads; for example, when the pitch of the pads is At 100 microns, the offset allowable range A of the shroud opening 131 is set to a value less than 50 microns, such as 40 microns.

As shown in FIG. 2, the substrate body 110 can include at least one unit area 112 and a frame area 113, and the pad 121 and the solder mask opening 131 can be located in the unit area 112. The detecting pad 122 is The shroud island 132 can be located within the bezel area 113. The substrate body 110 can be a substrate panel, and each of the unit regions 112 can be configured as a substrate strip. Wherein, all or a part of the unit area 112 is a portion of the package substrate that remains in the element after forming an electronic component such as a semiconductor package structure, and the frame region 113 is cut after the component is formed. The portion of the border area 113 will not remain within the component. Therefore, the position and shape of the detecting pad 122 and the welding shroud island 132 can be more diverse, and the design of the component is not limited. More specifically, the detection pad 122 and the solder mask island 132 may be located at one corner of the frame region 113, and the number of configurations may be a multiple array, thereby achieving detection corresponding to the size of the solder mask layer 130 and the circuit layer 120. However, if only the detection pad 122 of a certain corner is partially exposed, it can be determined that the size of the two is not matched due to the difference in thermal expansion coefficient or the unevenness of the substrate warpage.

As shown in FIG. 3, in the embodiment, the soldering island 132 and the detecting pad 122 are both square, and the soldering island 132 has a length L1 equal to the corresponding length L2 of the detecting pad 122. Up to twice the offset allows the sum of the range A (as shown in Figure 1), ie L1 = L2 + 2A.

Therefore, when the actual offset value B of the shroud opening 131 is within the offset allowable range A, that is, B < A shown in FIG. 4A, the shroud island 132 will completely cover the detecting pad 122. Pad 122 has no exposed metal surface. As shown in FIGS. 4A and 4B, when the actual offset value B of the shroud opening 131 exceeds the offset allowable range A, the shroud island 132 having the same offset value will no longer completely cover the detecting pad 122. The detecting pad 122 has an exposed metal surface. In the embodiment, the exposed metal surface of the detecting pad 122 has a shape of a "1" shape (as shown in FIG. 4B). Therefore, it can be easily judged by visual inspection or optical instrument whether the actual offset value of the welding cap opening 131 is within the tolerance of the offset.

In addition, as shown in FIG. 1 , the package substrate 100 may further include a plating layer 140 formed on the pad 121 . Generally, the plating layer 140 is a nickel gold layer. Moreover, the plating layer 140 is not formed on the detecting pad 122, and the offset of the soldering cap opening 131 with respect to the pad 121 is within the offset allowable range A. More specifically, as shown in FIG. 3, the circuit layer 120 further includes a plating conductive line 123 connected to the detecting pad 122. As shown in FIG. 4A, when the offset of the shroud opening 131 relative to the pad 121 exceeds the offset allowable range A, the exposed pad surface of the detecting pad 122 beyond the shroud island 132 will also be plated. An excess plating portion 141 is formed in synchronization with the material of the plating layer 140 to avoid oxidation of the exposed metal surface and is easily sensed by a visual or optical instrument.

According to a second preferred embodiment of the present invention, another package substrate capable of optically detecting the opening of the solder mask opening within an allowable range is illustrated in a partial cross-sectional view of FIG. 5, a surface view of FIG. 6, and a seventh diagram. A partial enlarged view of a welded island. The package substrate 200 has the same name and function as the package substrate 100 of the first embodiment, and the same detailed description is omitted. The package substrate 200 mainly includes a substrate body 110 and a circuit layer. 120, and a solder mask layer 130.

As shown in the first embodiment, the circuit layer 120 is formed on one surface 111 of the substrate body 110. The circuit layer 120 includes at least one pad 121. The solder mask layer 130 is formed on the surface 111 of the substrate body 110 and the circuit layer 120. The solder mask layer 130 has at least one solder mask opening 131 for exposing the pad 121. The circuit layer 120 further includes a detection pad 122, and the solder mask layer 130 includes a solder mask island 132 corresponding to the shape and aligned with the detection pad 122. The detection pad 122 is between the detection pad 122 and the pad 121. The intermediate point distance is a first pitch D1, and the intermediate point distance between the welding shroud island 132 and the shroud opening 131 is a second pitch D2, and the first pitch D1 is equal to the second The pitch D2, and the coverage area of the shroud island 132 is slightly larger than the detection pad 122 to completely cover the detection pad 122 within the offset tolerance range A of the shroud opening 131.

As shown in FIG. 6, the package substrate 200 can be a substrate strip type, the substrate body 110 includes at least one unit region 112 and a frame region 113, and the pad 121 is located with the solder mask opening 131. In the unit area 112, the detecting pad 122 and the soldering cover island 133 are located in the frame area 113. Each of the unit regions 112 is a portion where the package substrate is retained in the element after forming an electronic component such as a semiconductor package structure.

As shown in FIG. 7, more specifically, the shroud island 132 can be formed in one of the annular grooves 234 of the shim layer 130. The solder mask layer 130 may further have a connecting portion 233 connected to the solder mask island 132 through the annular groove 234 and covering a portion of the plating conductive line 123 passing through the annular groove 234 to avoid the plating conduction. The improper line 123 is exposed.

Referring to Figures 5 and 7, at the same time, the shape of the solder mask island 132 and the detecting pad 122 should be consistent with the shape of the pad 121 to simulate the actual deviation of the solder mask opening and its corresponding exposed pad. Degree of shift. For example, when the pad 121 is circular, the shape of the solder mask island 132 and the detecting pad 122 may both be circular, and the soldering island 132 has a diameter R1 which is equal to the detecting pad 122. The corresponding diameter R2 is doubled to the sum of the offset allowable ranges A, that is, R1=R2+2A.

Therefore, when the actual offset value of the shroud opening 131 is within the offset tolerance range, the shroud island 132 will completely cover the test pad 122, and the test pad 122 has no exposed metal surface. Fig. 9 is a partially enlarged photograph of the actual product of the present embodiment at the welding hood island. It can be seen that the welding hood island completely covers the detection pad and the connection portion of the welding hood layer completely covers the pattern of the electroplating conduction line.

As shown in FIG. 8, when the actual offset value B of the shroud opening 131 exceeds the offset allowable range A, the shroud island 132 having the same offset value will no longer completely cover the detecting pad 122. The detecting pad 122 has an exposed metal surface. In the embodiment, the exposed metal surface of the detecting pad 122 has a circular arc shape. Therefore, it can be easily judged by visual inspection or optical instrument whether the actual offset value of the welding cap opening is within the tolerance of the offset. In addition, when a plating layer 140 is formed on the surface of the pad 121, the detecting pad 122 extends beyond the exposed metal surface of the soldering island 132 to have an unnecessary plating portion 141 which is formed of the same material as the plating layer 140 and formed simultaneously.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

100‧‧‧Package substrate

110‧‧‧Substrate body

111‧‧‧ surface

112‧‧‧Unit area

113‧‧‧Border area

120‧‧‧Line layer

121‧‧‧ pads

122‧‧‧Test pad

123‧‧‧Electroplating conduction line

130‧‧‧welding layer

131‧‧‧welding opening

132‧‧‧welding island

140‧‧‧Electroplating

141‧‧‧Excess plating department

200‧‧‧Package substrate

233‧‧‧Connecting Department

234‧‧‧ Ring groove

A‧‧‧Offset tolerance

B‧‧‧ actual offset

D1‧‧‧ first pitch

D2‧‧‧second pitch

Length of L1‧‧‧welding island

Length of L2‧‧‧ test pad

R1‧‧‧diameter of welding island

R2‧‧‧ length of test pad

1 is a partial cross-sectional view of a package substrate in which an optically detectable solder mask opening is offset within an allowable range in accordance with a first embodiment of the present invention.

Figure 2 is a schematic view showing the surface of the package substrate in accordance with the first embodiment of the present invention.

FIG. 3 is a partially enlarged schematic view showing the surface of the package substrate at a solder mask island according to the first embodiment of the present invention.

4A and 4B are diagrams showing a partial cross-sectional view of the package substrate and a partial surface enlargement at the island of the solder mask when the offset value of the opening of the solder mask exceeds the allowable range of the offset according to the first embodiment of the present invention. schematic diagram.

Figure 5 is a partial cross-sectional view of a package substrate in which the optical opening of the solder mask is offset within an allowable range in accordance with a second embodiment of the present invention.

Figure 6 is a schematic view showing the surface of the package substrate in accordance with a second embodiment of the present invention.

FIG. 7 is a partially enlarged schematic view showing the surface of the package substrate at a solder mask island according to a second embodiment of the present invention.

FIG. 8 is a partial cross-sectional view showing the package substrate included in the solder mask island when the offset value of a solder mask opening exceeds an offset tolerance range according to the second embodiment of the present invention.

Figure 9 is a pictorial view of the surface of the package substrate at the island of the solder mask in accordance with a second embodiment of the present invention.

100. . . Package substrate

110. . . Substrate body

111. . . surface

120. . . Circuit layer

121. . . Pad

122. . . Test pad

130. . . Welding mask

131. . . Weld cap opening

132. . . Weld island

140. . . Plating

141. . . Excess plating

B. . . Actual offset

D1. . . First pitch

D2. . . Second pitch

Claims (10)

A package substrate capable of optically detecting a gap of a solder mask opening within an allowable range, comprising: a substrate body having a surface; a circuit layer formed on the surface of the substrate body, the circuit layer comprising at least one a pad; and a solder mask layer formed on the surface of the substrate body and the circuit layer, the solder mask layer having at least one solder mask opening to expose the pad; wherein the circuit layer is further Included as a test pad, and the solder mask layer includes a solder mask island corresponding to the shape and aligned with the test pad, and the intermediate point between the test pad and the pad is a first pitch, the soldering The intermediate point between the hood island and the opening of the welding hood is a second pitch, the first pitch is equal to the second pitch, and the coverage area of the welding hood island is slightly larger than the detecting pad, The test pad is completely covered within the tolerance of the gap of the shroud opening. According to the scope of claim 1, the package substrate can be optically detected to be within an allowable range of the solder mask opening, wherein the circuit layer further comprises an electroplating conductive line connected to the detecting pad. The package substrate capable of optically detecting that the opening of the solder mask is offset within an allowable range according to the second aspect of the patent application, further comprising a plating layer formed on the pad, and the plating layer is not formed on the detecting pad. The offset of the shroud opening relative to the pad is within the tolerance of the offset. According to the scope of claim 2, the package substrate can be optically detected to be within an allowable range of the solder mask opening, wherein the solder mask island is formed in one of the ring grooves of the solder mask layer. According to claim 4, the package substrate can be optically detected to be within an allowable range of the solder mask opening, wherein the solder mask layer further has a connecting portion connected to the solder mask island and covered by the ring groove. The plated conductive wire passes through a portion of the ring groove. According to the first aspect of the patent application, the package substrate can be optically detected to be within an allowable range of the solder mask opening, wherein the solder mask island and the detection pad are both square, and the solder mask island has a length equal to the detection pad. The corresponding length is doubled to the sum of the allowable ranges of the offset. According to claim 1, the optically detectable solder mask opening is offset within an allowable range, wherein the solder mask island and the detection pad are both circular, and the solder mask island has a diameter equal to the detection. The corresponding diameter of the pad plus twice the sum of the allowable ranges of the offset. The package substrate according to the first aspect of the patent application, wherein the solder mask opening is offset within an allowable range, wherein the substrate main system comprises at least one unit area and a frame area, and the pad is located with the solder mask opening In the unit area, the detecting pad and the welding hood island are located in the frame area. According to the sixth aspect of the patent application, the package substrate can be optically detected to be within an allowable range of the solder mask opening, wherein the detecting pad and the solder mask island are located at a corner of the frame region. According to the scope of claim 1, the package substrate can be optically detected to be within an allowable range of the solder mask opening, wherein the solder mask opening is smaller than the pad so that the pad is a solder mask defining pad (SMD pad).