JP5489860B2 - Multilayer semiconductor module - Google Patents

Multilayer semiconductor module Download PDF

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JP5489860B2
JP5489860B2 JP2010115860A JP2010115860A JP5489860B2 JP 5489860 B2 JP5489860 B2 JP 5489860B2 JP 2010115860 A JP2010115860 A JP 2010115860A JP 2010115860 A JP2010115860 A JP 2010115860A JP 5489860 B2 JP5489860 B2 JP 5489860B2
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connection terminal
opening
substrate
shape
connection
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JP2011003890A5 (en
JP2011003890A (en
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毅 川端
油井  隆
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

本発明は、複数の半導体装置を積層して構成するときの最下層に配置する積層用半導体モジュールと、これを用いた積層型半導体モジュールに関する。   The present invention relates to a semiconductor module for stacking disposed in a lowermost layer when a plurality of semiconductor devices are stacked and configured, and a stacked semiconductor module using the same.

携帯電話装置やデジタルカメラ等の各種電子機器の小型化、高機能化の要請に伴い、電子部品、特に複数個の半導体装置及びチップを積層して一体化してなる積層型半導体モジュール(Package on Package)が開発されている。   In response to demands for miniaturization and higher functionality of various electronic devices such as mobile phone devices and digital cameras, electronic components, especially stacked semiconductor modules that are integrated by stacking multiple semiconductor devices and chips (Package on Package) ) Has been developed.

この積層型半導体モジュールの実装においては、一層の高密度化による上下パッケージの接続の歩留まりや高機能化に伴う検査感度の向上が問題となってきており、それらに対して品質そのものの向上による検査の歩留まりの改善が求められている。   In the mounting of this stacked semiconductor module, the improvement in inspection sensitivity due to the higher yield and higher functionality of the connection of upper and lower packages due to higher density has become a problem. There is a need for improved yields.

従来の積層型半導体モジュールとしては特許文献2などが知られている。図8(a)は従来の積層型半導体モジュールを示し、第1のパッケージPK1の上に第2のパッケージPK2が積層して実装されている。   Patent document 2 etc. are known as a conventional laminated semiconductor module. FIG. 8A shows a conventional stacked semiconductor module, in which a second package PK2 is stacked and mounted on a first package PK1.

第1のパッケージPK1の下面には外部接続用端子2が配置され、第1のパッケージPK1の上面には上下接続端子1が配置されている。正常な製品では、上下接続端子1は第1のパッケージPK1の上面に形成されている上層モジュール接続用のパッド15aの上に接合されている。また、上下接続端子1の接続面の形状と外部接続用端子2の形状が、いずれも円形の類似形状である。また、上層モジュール接続用のパッド15aは、図8(b)に示すように円形である。   The external connection terminals 2 are disposed on the lower surface of the first package PK1, and the upper and lower connection terminals 1 are disposed on the upper surface of the first package PK1. In a normal product, the upper and lower connection terminals 1 are bonded onto the upper layer module connection pads 15a formed on the upper surface of the first package PK1. Further, the shape of the connection surface of the upper and lower connection terminals 1 and the shape of the external connection terminal 2 are both similar circular shapes. Further, the upper layer module connection pad 15a is circular as shown in FIG.

特許文献2には、図9に示すように半導体装置の基板11に設けたランド4自体を熱膨張方向に長くなるような長方形、楕円、長円などで形成して、プリント基板と半導体装置の接続信頼性を高めたものが記載されている。   In Patent Document 2, as shown in FIG. 9, the land 4 itself provided on the substrate 11 of the semiconductor device is formed in a rectangle, an ellipse, an ellipse or the like that is elongated in the direction of thermal expansion. What improved connection reliability is described.

特開2004−363126号公報JP 2004-363126 A 特開2000−208557号公報JP 2000-208557 A

通常、上下の半導体装置間の接続判定には電気検査が用いられる。つまり、上下間の接続状態および電気保証を行うために上下接続された積層完成品状態で再検査を実施するのが一般的である。   Usually, an electrical inspection is used to determine the connection between the upper and lower semiconductor devices. In other words, in general, re-inspection is performed in the state of the connection between the upper and lower sides and the state of the laminated finished product connected in the upper and lower directions in order to ensure electricity.

その検査においては、積層型半導体モジュールを検査装置のソケットに挿入し、上部からの荷重をかけることによりに第1のパッケージPK1の外部接続用端子2と前記ソケットの側のプローブとを接触させ、積層型半導体モジュールの内部配線を通じて第1のパッケージPK1と第2のパッケージPK2の接続部の導通の判定を行っている。   In the inspection, the stacked semiconductor module is inserted into the socket of the inspection apparatus, and the external connection terminal 2 of the first package PK1 is brought into contact with the probe on the socket side by applying a load from above. The connection between the first package PK1 and the second package PK2 is determined to be conductive through the internal wiring of the stacked semiconductor module.

しかし、このような電気検査では第1のパッケージPK1と第2のパッケージPK2との間の接合状態が、確実な接合ではなくて、単に接触しているかどうかが微妙な場合に、上記検査時の荷重により第1のパッケージPK1と第2のパッケージPK2の接続部の導通の接触が一時的に取られる状態が発生して、「電気的にOK」と判定されて検査をパスしてしまう場合がある。   However, in such an electrical inspection, when the bonding state between the first package PK1 and the second package PK2 is not a reliable bonding and it is delicate whether or not it is simply in contact, There is a case in which a state in which the connection between the connection portions of the first package PK1 and the second package PK2 is temporarily taken due to the load occurs and the inspection is passed because it is determined as “electrically OK”. is there.

そのため、上下の接続端子においては単に接触しているだけでなく、上下がきちんと物理的に接合して接続が維持されているかどうかの判定には、非接触の透過検査としてX線検査や超音波探傷法(SAT Scanning Acoustic Tomograph )が用いられている。   Therefore, not only the upper and lower connection terminals are in contact but also whether or not the upper and lower connection terminals are properly physically joined and the connection is maintained is determined by a non-contact transmission inspection such as X-ray inspection or ultrasound. The flaw detection method (SAT Scanning Acoustic Tomograph) is used.

しかしながら、このような透過検査は、目視判定では非常に時間がかかり、自動判定でも閾値の設定が困難であったりして、接合有無の不良判定が非常に困難である。
具体的には、図8(a)(b)に挙げた例では、パッド15aの形状が円形であり、外部接続用端子2もボール形状の円形状であるため、非接触の透過検査において積層型半導体モジュールを上部から透過させても共に円形状の同一になっている。しかも上下接合状態での接続面の円形状に対し、未接合状態や非接触状態でも上部の端子のボールの平面形状そのものが見られ、共に同形状になっている。その上、最下部の端子、上部の端子等同形状の接続端子がサイズに関係なく混在しているため、未接合の状態であっても、接合した状態と大きさや形状が一見して同じで、さらに他の接続端子とも形状が同一であるため、接合箇所や他の接続端子の区別が困難である。
However, such a transmission inspection takes a very long time for visual determination, and it is difficult to set a threshold value even with automatic determination, and it is very difficult to determine whether or not there is a joint.
Specifically, in the example shown in FIGS. 8A and 8B, the pad 15a has a circular shape, and the external connection terminal 2 has a ball-shaped circular shape. Even if the mold type semiconductor module is transmitted from the upper part, both are circular and identical. Moreover, in contrast to the circular shape of the connection surface in the vertically joined state, the planar shape of the ball of the upper terminal itself can be seen in the unjoined state and the non-contact state, and both are the same shape. In addition, since the connection terminals of the same shape such as the lowermost terminal and the upper terminal are mixed regardless of the size, the size and shape of the joined state are the same at first glance, even in the unjoined state, Furthermore, since the other connecting terminals have the same shape, it is difficult to distinguish the joint location and the other connecting terminals.

特許文献2には、図9に示すようにランド4の形状を長方形にして半導体装置のプリント基板に対する接続強度の向上を目的としたものが開示されている。しかし、積層型半導体モジュールのように積層状態において上下に端子が存在する検査時の課題に対するものでないことは明白である。   Japanese Patent Application Laid-Open No. H10-228561 discloses a land having a rectangular shape as shown in FIG. 9 for the purpose of improving the connection strength of a semiconductor device to a printed circuit board. However, it is clear that this is not a problem at the time of inspection in which terminals are present in the upper and lower sides in a stacked state as in a stacked semiconductor module.

具体的には、上下の接続端子に単に特許文献2に見られる長方形のランドを適用しただけでは、上下の接続端子に対するサイズの差異や各接続部位における形状の差異が明確でないために、X線等の透過検査においては、最下部の端子、上下間の端子などの同形状の接続端子が混在する可能性がある。   Specifically, simply applying the rectangular lands found in Patent Document 2 to the upper and lower connection terminals is not clear in the size difference between the upper and lower connection terminals and the shape difference in each connection part. In the transmission inspection such as the above, there is a possibility that connection terminals having the same shape such as the lowest terminal and the upper and lower terminals are mixed.

本発明は、非破壊検査での接合部の良否判定を容易に、また確実に行うことができ、それにより品質および信頼性を向上させることができる積層用半導体モジュール及び積層型半導体モジュールを提供することを目的とする。   The present invention provides a stacked semiconductor module and a stacked semiconductor module that can easily and reliably determine the quality of a joint in a nondestructive inspection, thereby improving quality and reliability. For the purpose.

発明の積層型半導体モジュールは、一方の面に第1の半導体チップが実装され、前記第1の半導体チップの保持領域外に第2パッドがあり、他方の面の第1パッド上に半田からなる第1の接続端子を有する第1の基板と、一方の面に第2の半導体チップが実装された第2の基板と、前記第1の基板と前記第2の基板を積層して、前記第1の基板と前記第2の基板の間を接続する半田からなる第2の接続端子とを含む積層型半導体モジュールであって、前記第2パッドは、開口部を有する絶縁膜で被覆され、前記開口部の平面形状は、前記第1の接続端子の平面形状とは異なり、前記第2の接続端子は、前記開口部を満たして前記第2パッドに接合され、前記第1の基板と前記第2の基板との積層方向に透過検査した場合に前記開口部のピッチと前記第1の接続端子のピッチとは等しく、前記開口部の平面形状は、前記開口部の並びと前記第1の接続端子の並びとは平行するが位置が異なり、前記第1の接続端子から前記開口部の一部がはみ出しており、前記開口部の平面形状は全部が多角形であり、前記第1の接続端子の平面形状は全部が円形状であり、前記開口部の前記多角形の外形は、前記第1の接続端子の径より大きいことを特徴とする。 The stacked semiconductor module of the present invention has a first semiconductor chip mounted on one surface, a second pad outside the holding region of the first semiconductor chip, and a solder on the first pad on the other surface. A first substrate having a first connection terminal, a second substrate having a second semiconductor chip mounted on one surface, the first substrate and the second substrate, and A stacked semiconductor module including a first connection terminal and a second connection terminal made of solder for connecting between the first substrate and the second substrate, wherein the second pad is covered with an insulating film having an opening, The planar shape of the opening is different from the planar shape of the first connection terminal, and the second connection terminal fills the opening and is joined to the second pad, and the first substrate and the When the transmission inspection is performed in the stacking direction with the second substrate, And the pitch of the first connection terminals is equal, and the planar shape of the openings is parallel to the arrangement of the openings and the arrangement of the first connection terminals, but the positions thereof are different. A part of the opening protrudes from the surface, and the planar shape of the opening is entirely polygonal; the planar shape of the first connection terminal is entirely circular; and the polygon of the opening The outer shape is larger than the diameter of the first connection terminal .

この構成によれば、積層型半導体モジュールは、下層モジュールと上層モジュールとを接続する第2の接続端子の平面形状ならびに第1の基板の他方の面に形成された第1の接続端子の平面形状を、第2の接続端子による前記他端と第1の基板の側の前記パッドとの接続面の形状とが異ならせ、第1の接続端子と前記開口部との積層方向に透過検査した状態において前記開口部の外形が第1の接続端子からはみ出している、または前記開口部の外形が第2の接続端子ならびに第1の接続端子よりも大きいため、下層モジュールと上層モジュールとの未接合状態と接合状態で形状が明らかに異なる。なおかつ上方向からの透過検査において、前記開口部を満たして前記パッドに接合された第2の接続端子の平面形状が他端子に隠れないため、上部からの透過検査によって、その形状差異を容易に判別できる。よって、上層および下層モジュールの接合部の検査を確実にすることができ、品質、信頼性の高い半導体装置及びモジュールとして供給できる。   According to this configuration, the stacked semiconductor module includes the planar shape of the second connection terminal that connects the lower layer module and the upper layer module and the planar shape of the first connection terminal formed on the other surface of the first substrate. The shape of the connection surface between the other end of the second connection terminal and the pad on the first substrate side is different, and the transmission inspection is performed in the stacking direction of the first connection terminal and the opening. The outer shape of the opening protrudes from the first connection terminal, or the outer shape of the opening is larger than the second connection terminal and the first connection terminal, so that the lower layer module and the upper module are not joined. The shape is obviously different depending on the bonding state. In addition, in the transmission inspection from above, the planar shape of the second connection terminal that fills the opening and is bonded to the pad is not hidden by other terminals, so that the shape difference can be easily detected by transmission inspection from above. Can be determined. Therefore, the inspection of the joint between the upper layer and lower layer modules can be ensured, and the semiconductor device and module can be supplied with high quality and reliability.

本発明の実施の形態における(a)積層型半導体モジュールの断面図、(b)接続面Aの断面図、(c)接続面Bの断面図、(d)接続面Cの断面図(A) Cross-sectional view of stacked semiconductor module, (b) Cross-sectional view of connection surface A, (c) Cross-sectional view of connection surface B, (d) Cross-sectional view of connection surface C in the embodiment of the present invention 同実施の形態における積層型半導体モジュールの製造方法の説明図Explanatory drawing of the manufacturing method of the laminated semiconductor module in the embodiment 同実施の形態における積層用半導体装置の下層モジュールの断面図Sectional drawing of the lower layer module of the semiconductor device for lamination | stacking in the same embodiment 同実施の形態における第1の基板11の投影状態の平面図The top view of the projection state of the 1st substrate 11 in the embodiment 同実施の形態における(a)積層型半導体モジュールの一部未接合の場合の断面図と(b)上部方向からX線透過装置により透過観察した場合の画像(A) A cross-sectional view of the case where the stacked semiconductor module is partially unjoined in the embodiment, and (b) an image when observed through transmission with an X-ray transmission device from above. 同実施の形態における開口部の形状を示す拡大平面図The enlarged plan view which shows the shape of the opening part in the embodiment 課題の説明図Illustration of the problem 従来例に記載された積層型半導体モジュールの断面図と下層モジュールの接合面の平面図Sectional view of the stacked semiconductor module described in the conventional example and plan view of the joint surface of the lower layer module 別の従来例に記載されたランドの形状を示す平面図The top view which shows the shape of the land described in another prior art example

以下、本発明の実施の形態を図1〜図7に基づいて説明する。
図1(a)は本発明の積層型半導体モジュールを示す。なお、端子、電極及び配線等の個数および形状については省略又は図示しやすい個数および形状等としている。以下の全ての図において同様の省略などを行っている。
Hereinafter, embodiments of the present invention will be described with reference to FIGS.
FIG. 1A shows a stacked semiconductor module of the present invention. Note that the numbers and shapes of terminals, electrodes, wirings, and the like are omitted or easy to show. Similar omissions are made in all the following figures.

第1のパッケージPK21の上に第2のパッケージPK22が積層して実装されている。第1のパッケージPK21の上面には第1の半導体チップ12が実装され、第2のパッケージPK22の第2の基板25の上面には第2の半導体チップ22が実装されている。   A second package PK22 is stacked and mounted on the first package PK21. The first semiconductor chip 12 is mounted on the upper surface of the first package PK21, and the second semiconductor chip 22 is mounted on the upper surface of the second substrate 25 of the second package PK22.

第2のパッケージPK22は、具体的には、汎用的な積層用メモリー装置等であって、メモリー等の第2の半導体チップ22を基板に搭載、互いの電極同士をワイヤーボンドやフリップチップ工法を用いて電気接続し、場合によっては、半導体チップを被覆するように樹脂で封止や塗布されている。   Specifically, the second package PK22 is a general-purpose stacking memory device or the like, in which a second semiconductor chip 22 such as a memory is mounted on a substrate, and the electrodes are connected to each other by wire bonding or a flip chip method. It is used for electrical connection, and in some cases, it is sealed or coated with resin so as to cover the semiconductor chip.

図2は第1のパッケージPK21と第2のパッケージPK22の積層工程を示している。第2のパッケージPK22には、第1のパッケージPK21との接合用に第2の接続端子30が形成されている。接続端子30を構成する接合金属としては、SnPb、SnAgCu、SnCu、SnBiなどの半田材料を用いた半田ボールが一般的である。   FIG. 2 shows a stacking process of the first package PK21 and the second package PK22. A second connection terminal 30 is formed in the second package PK22 for joining with the first package PK21. As the joining metal constituting the connection terminal 30, a solder ball using a solder material such as SnPb, SnAgCu, SnCu, SnBi is generally used.

下層モジュールである積層用半導体モジュールの第1のパッケージPK21は、図3のように構成されている。
第1のパッケージPK21は、第1の基板11と、第1の基板11のチップ保持面に実装された第1の半導体チップ12とにより構成されている。
The first package PK21 of the stacked semiconductor module, which is a lower layer module, is configured as shown in FIG.
The first package PK 21 includes a first substrate 11 and a first semiconductor chip 12 mounted on the chip holding surface of the first substrate 11.

第1の半導体チップ12は、平面方形状のチップ基板の中央部に半導体素子が形成された集積回路形成領域(図示せず)が設けられ、その外側に複数の第1のチップ端子23が配置されている。第1のチップ端子23は、集積回路の配線の形成に使用される金属と同一の金属により一般的に形成されており、アルミニウム、銅、またはアルミニウムと銅との積層材料等で形成される。チップ基板の表面は、第1のチップ端子23が形成されている領域を除き、ポリイミド等の絶縁膜(図示せず)で覆われている。第1のチップ端子23は集積回路形成領域内に配置されていてもよい。第1のチップ端子23には、突起電極24がワイヤバンプ方式またはめっき(plating)方式等の公知の方法により形成されている。   The first semiconductor chip 12 is provided with an integrated circuit formation region (not shown) in which a semiconductor element is formed at the center of a planar rectangular chip substrate, and a plurality of first chip terminals 23 are arranged on the outside thereof. Has been. The first chip terminal 23 is generally formed of the same metal as that used for forming the wiring of the integrated circuit, and is formed of aluminum, copper, or a laminated material of aluminum and copper. The surface of the chip substrate is covered with an insulating film (not shown) such as polyimide except for the region where the first chip terminals 23 are formed. The first chip terminal 23 may be disposed in the integrated circuit formation region. A protruding electrode 24 is formed on the first chip terminal 23 by a known method such as a wire bump method or a plating method.

第1のチップ端子23に設けられている突起電極24は、半田、金、銅、およびニッケル等のいずれかからなる単体又は2つ以上からなる積層体であればよく、形状は球状又は柱状のバンプであればよい。   The protruding electrode 24 provided on the first chip terminal 23 may be a simple substance or a laminate made of two or more of solder, gold, copper, nickel, etc., and the shape is spherical or columnar. It may be a bump.

第1の基板11は、アラミド樹脂、ガラスエポキシ樹脂、ポリイミド樹脂またはセラミック等により形成された多層配線構造を有している。第1の基板11のチップ保持面には、第1の半導体チップ12に設けられた突起電極24と対応する位置に第1のチップ接続端子13が複数設けられている。   The first substrate 11 has a multilayer wiring structure formed of aramid resin, glass epoxy resin, polyimide resin, ceramic, or the like. A plurality of first chip connection terminals 13 are provided on the chip holding surface of the first substrate 11 at positions corresponding to the protruding electrodes 24 provided on the first semiconductor chip 12.

第1の半導体チップ12は第1の基板11にフリップチップ実装されており、第1の半導体チップ12の突起電極24が、導電性接着材14により第1のチップ接続端子13に電気的に接続されている。さらに、第1の半導体チップ12と第1の基板11の接続補強のため、アンダーフィル樹脂16がその間を埋めている。アンダーフィル樹脂16の代わりに非導電性樹脂フィルムの硬化収縮により接続する方法等を用いて第1の半導体チップ12と第1の基板11との接続を行ってもよい。   The first semiconductor chip 12 is flip-chip mounted on the first substrate 11, and the protruding electrode 24 of the first semiconductor chip 12 is electrically connected to the first chip connection terminal 13 by the conductive adhesive 14. Has been. Furthermore, an underfill resin 16 fills the space for reinforcing the connection between the first semiconductor chip 12 and the first substrate 11. The first semiconductor chip 12 and the first substrate 11 may be connected using a method of connecting by curing shrinkage of a non-conductive resin film instead of the underfill resin 16.

第1の基板11のチップ保持面とは反対側の面(裏面)には、外部接続用の第1の接続端子2が等間隔の格子状に複数配置されている。第1の接続端子2はプリント基板である外部基板(図示せず)と電気的に接続できる。第1の接続端子2の材料として通常はSnPb、SnAgCu、SnCu、SnBiといった半田材料、または金、銅又はニッケル等からなるボール形状のものを搭載し、融点以上にリフロー加熱することで第1の基板11に溶融接合できる。また、第1の接続端子2としては表面層に金属蒸着等を行って導電性を付与した樹脂ボールを用いることもできる。   On the surface (back surface) opposite to the chip holding surface of the first substrate 11, a plurality of first connection terminals 2 for external connection are arranged in a lattice pattern at equal intervals. The first connection terminal 2 can be electrically connected to an external board (not shown) which is a printed board. As a material for the first connection terminal 2, a solder material such as SnPb, SnAgCu, SnCu, SnBi or a ball-shaped material made of gold, copper, nickel, or the like is usually mounted, and the first reflow heating is performed to a temperature higher than the melting point. It can be melt bonded to the substrate 11. Further, as the first connection terminal 2, a resin ball provided with conductivity by performing metal vapor deposition or the like on the surface layer can also be used.

第1の基板11のチップ保持面における第1の半導体チップ12の保持領域の外側部分には、積層型半導体モジュールの上層モジュールとしての第2のパッケージPK22と接続するための上層モジュール接続用のパッド15が複数設けられている。さらにパッド15の上をソルダーレジスト又はポリイミド等のような絶縁膜20が一部を被覆して、かつ上層モジュール接続用の開口部3によってパッド15の一部を露出させている。開口部3から露出している部分はニッケル、金めっき等のめっき(plating)による表面処理を施し、下層のパッドの酸化を防止している。第1の基板11のチップ保持面とは反対面(裏面)も、第1の接続端子2が形成された部分等を除いて、ソルダーレジストまたはポリイミド等の絶縁膜20が形成されている。   A pad for connecting an upper layer module for connecting to a second package PK22 as an upper layer module of the stacked semiconductor module is provided on the outer side of the holding region of the first semiconductor chip 12 on the chip holding surface of the first substrate 11. A plurality of 15 are provided. Further, an insulating film 20 such as solder resist or polyimide covers a part of the pad 15 and a part of the pad 15 is exposed by the opening 3 for connecting the upper layer module. The portion exposed from the opening 3 is subjected to surface treatment by plating such as nickel or gold plating to prevent oxidation of the underlying pad. An insulating film 20 such as solder resist or polyimide is also formed on the surface (back surface) opposite to the chip holding surface of the first substrate 11 except for the portion where the first connection terminals 2 are formed.

図4は第1のパッケージPK21の第1の基板11の詳細を示す。
図4には図3の平面図に加え、第1の接続端子2の投影図を合わせて示している。
ここで開口部3は開口の形状が四角形状であるのに対し、第1の接続端子2が半田ボールであるためその形状は円形状をしていることで、両者が異なる平面形状をしている。しかも開口部3の外形は、外部接続用端子2よりも大きい。
FIG. 4 shows details of the first substrate 11 of the first package PK21.
4 shows a projection view of the first connection terminal 2 in addition to the plan view of FIG.
Here, the opening 3 has a square shape, whereas the first connection terminal 2 is a solder ball, so the shape of the opening 3 is circular. Yes. Moreover, the outer shape of the opening 3 is larger than that of the external connection terminal 2.

この実施の形態では、第1のパッケージPK21の開口部3と第1の接続端子2の形状の違いと大きさに特徴があって、これによって、第1のパッケージPK21と第2のパッケージPK22の接続状態を、次に説明のように非接触の透過検査によって簡易に検出できる。   In this embodiment, there is a feature in the difference and size of the opening 3 of the first package PK21 and the first connection terminal 2, and thereby, the first package PK21 and the second package PK22 are different. The connection state can be easily detected by non-contact transmission inspection as described below.

このように構成された第1のパッケージPK21に対して、第2のパッケージPK22を図2に示すように搭載させたままにして、接続端子30の材料の融点以上のリフロー加熱によって溶融し凝固することによって、第1のパッケージPK21の側のパッド15に接続端子30の下端が半田接合され、接続端子30を介して第1のパッケージPK21が第2のパッケージPK22に電気接続される。   The second package PK22 is mounted on the first package PK21 configured as described above as shown in FIG. 2, and is melted and solidified by reflow heating at or above the melting point of the material of the connection terminal 30. Thus, the lower end of the connection terminal 30 is solder-bonded to the pad 15 on the first package PK21 side, and the first package PK21 is electrically connected to the second package PK22 via the connection terminal 30.

溶融された接続端子30は、開口部3の形状に沿った形で濡れ広がって凝固することで、底面が開口部3の開口形状とほぼ同一の形状となっている。図1(b)はこのようにして形成された積層型半導体モジュールにおける第2のパッケージPK22と一つの接続端子30との接続面Aの断面図、図1(c)は第1のパッケージPK21と一つの接続端子30との接続面Bの断面図、図1(d)は第1のパッケージPK21と一つの第1の接続端子2との接続面Cの断面図を示している。   The melted connection terminal 30 wets, spreads and solidifies along the shape of the opening 3, so that the bottom surface has substantially the same shape as the opening shape of the opening 3. FIG. 1B is a cross-sectional view of the connection surface A between the second package PK22 and one connection terminal 30 in the stacked semiconductor module formed as described above, and FIG. 1C is a view illustrating the first package PK21. FIG. 1D is a cross-sectional view of the connection surface C between the first package PK21 and the first connection terminal 2, and FIG.

このように接続端子30の凝固した成分で満たされた正常な接合状態の場合の開口部3の四角形は、積層型半導体モジュールを上部方向からX線透過装置等により透過観察した場合には、接続端子30の底面が開口部3の全体に広がっているため、しかも、開口部3の四角形状の外形は第1の接続端子2よりも大きく形成されているため、X線等での上部からの透過観察において、下層モジュールの第1の接続端子2に接続端子30が重なる位置にあっても、接続端子30の接続面の画像が隠れることなく、図4のように接続端子30の底面すなわち開口部3の四角形状が、その下方に位置している第1の接続端子2の影からはみ出して観察できる。   The quadrangle of the opening 3 in the normal bonded state filled with the solidified component of the connection terminal 30 is connected when the stacked semiconductor module is observed through transmission from above using an X-ray transmission device or the like. Since the bottom surface of the terminal 30 spreads over the entire opening 3 and the rectangular outer shape of the opening 3 is larger than the first connection terminal 2, the X-ray or the like from the top In the transmission observation, even if the connection terminal 30 overlaps the first connection terminal 2 of the lower layer module, the bottom surface of the connection terminal 30, that is, the opening, as shown in FIG. The quadrangular shape of the portion 3 can be observed by protruding from the shadow of the first connection terminal 2 located below the portion.

これに対して、仮に濡れ不良が発生した未接合の場合や、図5(a)に示す接続端子30の左側のPのように接合不良が生じていると、接続端子30の底面が開口部3の全体に広がらないため、元の接続端子30の形状に近い円形状の底面を形成している。この接合不良の積層型半導体モジュールを上部方向からX線透過装置等により透過観察した場合には、開口部3やパッド自体は厚み自体も10μm〜20μmと薄いために透過画像として鮮明には写らずに、それよりも相対的に厚い、例えば100μm以上の厚さを持つ接続端子30の未接合の端子画像だけが円形状として極めて鮮明に映し出される。図5(b)のように接合不良個所Pの検出例を示す。   On the other hand, if there is a bonding failure in the case of non-bonding in which wetting failure has occurred, or if the bonding failure has occurred as indicated by P on the left side of the connection terminal 30 shown in FIG. 3 does not spread over the entire area 3, and thus a circular bottom surface close to the shape of the original connection terminal 30 is formed. When the poorly bonded stacked semiconductor module is observed through an X-ray transmission device or the like from the upper direction, the opening 3 and the pad itself are as thin as 10 μm to 20 μm. In addition, only the unjoined terminal image of the connection terminal 30 having a relatively thicker thickness, for example, 100 μm or more, is displayed very clearly as a circular shape. FIG. 5B shows an example of detection of a joint failure portion P. As shown in FIG.

図5(a)と図5(b)を比較して分かるように、正常な接合時には四角形状、未接合時には元の接続端子の形状としての円形状をそれぞれ確認できるため、第1のパッケージPK21が第2のパッケージPK22の接続状態を簡易に検出できる。よって、図3に示した構造の第1のパッケージPK21を下層モジュールとして使用して積層型半導体モジュールを組み立てることによって、簡単な検査工程だけで高信頼性の積層型半導体モジュールを実現できる。   As can be seen by comparing FIG. 5A and FIG. 5B, the square shape as the shape of the original connection terminal can be confirmed when normally joined, and when not joined, the first package PK21. However, the connection state of the second package PK22 can be easily detected. Therefore, by assembling the stacked semiconductor module using the first package PK21 having the structure shown in FIG. 3 as a lower layer module, a highly reliable stacked semiconductor module can be realized only by a simple inspection process.

なお、上記の実施の形態では、開口部3の形状が四角形の場合を例に挙げて説明したが、四角形よりも角部が多い多角形であってもよい。具体例を図6(a)〜(e)に示す。
図6(a)は開口部3の形状が十字形の場合、図6(b)は開口部3の形状が正方形でコーナにアールを付けた場合、図6(c)は開口部3の形状が五角形の場合、図6(d)は開口部3の形状が正方形でコーナ部分に内側に向かって突出したアールを付けた場合、図6(e)は開口部3の形状は、一部が変形した変形楕円形の場合である。この何れの場合でも開口部3の多角形の外形は、第1の接続端子2の径よりも大きくする。このように、十字形、角部にアールを設けたもの、五角形、辺の一部に円弧を含むような多角形、全て曲線であるが角がある多角形等であってもよい。
In the above embodiment, the case where the shape of the opening 3 is a quadrangle has been described as an example, but a polygon having more corners than the quadrangle may be used. Specific examples are shown in FIGS.
6A shows a case where the shape of the opening 3 is a cross shape, FIG. 6B shows a case where the shape of the opening 3 is a square and a corner is attached, and FIG. 6C shows a shape of the opening 3. 6 (d) shows a case where the shape of the opening 3 is a square and a rounded corner is attached to the corner portion, and FIG. 6 (e) shows that the shape of the opening 3 is partially This is the case of a deformed elliptical shape. In either case, the polygonal outer shape of the opening 3 is made larger than the diameter of the first connection terminal 2. Thus, it may be a cross, a corner provided with rounded corners, a pentagon, a polygon that includes an arc at a part of the side, a polygon that is all curved but has corners, and the like.

なお、開口部3のコーナ部分にアールを付けることで、開口部3のコーナ部分にアールを付け無い場合に比べてレジスト残渣や異物残渣を少なくすることができ、有効である。
なお、開口部3の大きさは、第1の接続端子2の径全体を包む大きさであればよく、その形状全体を隠すような大きさにすればよい。例えば、実際には外部端子径のばらつきレベルとして0.01mm以下程度、開口サイズのばらつきも0.01mm程度あるため、2乗平均の0.015mm以上に、端子径よりも大きくするのが望ましい。それにより、ほぼ全部の外部接続用端子径に隠れることなく、開口部での接続面が確認できる。
It should be noted that by applying a radius to the corner portion of the opening 3, resist residue and foreign matter residue can be reduced as compared with a case where the corner portion of the opening 3 is not radiused, which is effective.
In addition, the size of the opening 3 may be a size that covers the entire diameter of the first connection terminal 2 and may be a size that hides the entire shape. For example, in practice, the variation level of the external terminal diameter is about 0.01 mm or less, and the variation in the opening size is also about 0.01 mm. Therefore, it is desirable to make the square average 0.015 mm or more larger than the terminal diameter. Accordingly, the connection surface at the opening can be confirmed without being hidden by almost all the external connection terminal diameters.

具体的には、φ0.3mm程度のボール径に対しては□0.315mmより大きい四角形のような多角形形状を設定すればよい。また、開口部3と第1の接続端子2を投影面上に見た場合に、開口部3の多角形形状の直線部や角部が見えていると、円形状との差異が明確でわかりやすい。   Specifically, for a ball diameter of about φ0.3 mm, a polygonal shape such as a square larger than □ 0.315 mm may be set. In addition, when the opening 3 and the first connection terminal 2 are viewed on the projection plane, if the polygonal straight and corner portions of the opening 3 are visible, the difference from the circular shape is clear and easy to understand. .

また、下層モジュールにおいて、上層モジュールの開口部3のピッチと第1の接続端子2のピッチとを等しくすることもできる。ピッチが等しいと、図7に示すように上層および下層モジュールの外部接続用端子は同じ円形状がほぼ同様のサイズで等間隔に並ぶために、上述したような上部からのX線やSAT等の検査で判別が困難であるが、この実施の形態では図4に示すように上層モジュールPK22が接続される下モジュールの開口部30は多角形で、下層モジュールの第1の接続端子2の円形状とは異なる形状で、その外形は、下層モジュールの第1の接続端子2の径よりも大きいために容易に透過観察において判別できる。   In the lower module, the pitch of the openings 3 of the upper module and the pitch of the first connection terminals 2 can be made equal. If the pitches are equal, the external connection terminals of the upper and lower modules are arranged at equal intervals in the same size as shown in FIG. 7, so that X-rays, SAT, etc. Although it is difficult to determine by inspection, in this embodiment, as shown in FIG. 4, the opening 30 of the lower module to which the upper module PK22 is connected is polygonal, and the circular shape of the first connection terminal 2 of the lower module Since the outer shape is larger than the diameter of the first connection terminal 2 of the lower layer module, it can be easily discriminated in transmission observation.

さらに、上述のような下層モジュールに対して、汎用的なボール形状の接続端子30を有した上層モジュールを接合、積層した場合には、積層型半導体モジュールの状態で上層モジュールの接続端子30の底面が多角形の形状を呈し、未接合の部位は円形状のまま残る。このように形状が異なる上に、上層モジュールの接続端子30の径よりも大きいものである。よって、X線等による上部からの透過検査において明らかに接合有無が判別できる。   Further, when an upper layer module having a general-purpose ball-shaped connection terminal 30 is bonded to and stacked on the lower layer module as described above, the bottom surface of the connection terminal 30 of the upper layer module in the state of the stacked semiconductor module. Exhibits a polygonal shape, and the unjoined portion remains circular. Thus, the shape is different and the diameter is larger than the diameter of the connection terminal 30 of the upper layer module. Therefore, the presence or absence of bonding can be clearly determined in the transmission inspection from the upper part by X-ray or the like.

接続端子30の径よりも大きくない場合には上部から透過させて観察した際には、底面の多角形形状が接続端子30自体に隠れ、透過画像としてその端子径の円形状が見られ、未接合の場合と判別できない場合がある。また、上記の接続端子の底面形状の変化は接続前後、つまり積層前後のみで上下のそれぞれの半導体モジュールの製造工程においては、特殊な加工は一切なく、パッドの形状を上述のような多角形にするのみであるため、既存工程、汎用的なモジュールを用いることも容易である。また、開口部と外部接続用端子を投影面上に見た場合に、開口部の多角形形状の直線部や角部が見えていると、円形状との差異が明確で分かり易い。つまりここでは開口部3の形状は多角形で、接続端子30の底面も多角形である。そのサイズについては、上層モジュールの接続端子30の径より大きい。もしくは下層モジュールの第1の接続端子2の径よりも大きい。加えて双方より大きくてもよい。   If the diameter is not larger than the diameter of the connection terminal 30, when viewed through the top, the polygonal shape of the bottom surface is hidden by the connection terminal 30 itself, and a circular shape of the terminal diameter is seen as a transmission image. It may not be possible to distinguish from the case of joining. In addition, the change in the bottom shape of the connection terminal is before and after connection, that is, only before and after lamination, in the manufacturing process of the upper and lower semiconductor modules, there is no special processing, and the pad shape is changed to the polygon as described above. Therefore, it is easy to use existing processes and general-purpose modules. In addition, when the opening and the external connection terminal are viewed on the projection plane, if the polygonal straight and corner portions of the opening are visible, the difference from the circular shape is clear and easy to understand. That is, here, the shape of the opening 3 is a polygon, and the bottom surface of the connection terminal 30 is also a polygon. The size is larger than the diameter of the connection terminal 30 of the upper layer module. Or it is larger than the diameter of the 1st connection terminal 2 of a lower layer module. In addition, it may be larger than both.

上記の各実施の形態では、開口部3の平面形状が第1の接続端子2の平面形状とは異なり、開口部3の外形が第1の接続端子2よりも大きいとしたが、開口部3の平面形状が第1の接続端子2の平面形状とは異なり、第1の接続端子2と開口部3との積層方向に透過検査した状態で開口部3の外形が第1の接続端子2からはみ出していても同様の効果を期待できる。   In each of the above embodiments, the planar shape of the opening 3 is different from the planar shape of the first connection terminal 2, and the outer shape of the opening 3 is larger than that of the first connection terminal 2. Unlike the planar shape of the first connection terminal 2, the outer shape of the opening 3 is different from that of the first connection terminal 2 in a state where a transmission inspection is performed in the stacking direction of the first connection terminal 2 and the opening 3. The same effect can be expected even if it protrudes.

上記の各実施の形態では、開口部3の平面形状が接続端子30の平面形状ならびに第1の基板11の他方の面に形成された第1の接続端子2の平面形状とは異なり、一端が第2の基板25に接続された接続端子30の他端が溶融して凝固して開口部3を満たしてパッド15に接合され、開口部3の外形が接続端子30ならびに第1の接続端子2よりも大きいとしたが、開口部3の平面形状が接続端子30の平面形状ならびに第1の基板11の他方の面に形成された第1の接続端子2の平面形状とは異なり、一端が第2の基板25に接続された接続端子30の他端が溶融して凝固して開口部3を満たしてパッド15に接合され、第1の接続端子2と開口部3との積層方向に透過検査した状態で開口部3の外形が接続端子30ならびに第1の接続端子2からはみ出していても同様の効果を期待できる。   In each of the above-described embodiments, the planar shape of the opening 3 is different from the planar shape of the connection terminal 30 and the planar shape of the first connection terminal 2 formed on the other surface of the first substrate 11. The other end of the connection terminal 30 connected to the second substrate 25 is melted and solidified to fill the opening 3 and bonded to the pad 15, and the outer shape of the opening 3 is the connection terminal 30 and the first connection terminal 2. However, the planar shape of the opening 3 is different from the planar shape of the connection terminal 30 and the planar shape of the first connection terminal 2 formed on the other surface of the first substrate 11. The other end of the connection terminal 30 connected to the second substrate 25 is melted and solidified to fill the opening 3 and bonded to the pad 15, and transmission inspection is performed in the stacking direction of the first connection terminal 2 and the opening 3. In this state, the outer shape of the opening 3 is the connection terminal 30 and the first connection. Even if not protrude from the child 2 can expect a similar effect.

なお、上記の各実施の形態において、検査対象全てのモジュール間接続端子について、外部接続端子と上層モジュール接続用パッド開口部との積層方向に透過検査した状態で上層モジュール接続用パッド開口部の外形がモジュール間接続端子ならびに外部接続端子からはみ出しているとよい。この場合、簡易な透過検査により検査対象全ての不良の判別ができるので、オープンやショートの電気検査を全く不要にすることもできる。   In each of the embodiments described above, the outer shape of the upper layer module connection pad opening in a state in which all of the inter-module connection terminals to be inspected are subjected to a transmission inspection in the stacking direction of the external connection terminal and the upper layer module connection pad opening. Should protrude from the inter-module connection terminal and the external connection terminal. In this case, since all defects to be inspected can be determined by a simple transmission inspection, it is possible to eliminate the need for open or short electrical inspection.

また、上層モジュール接続用パッドの開口部が、円形状と異形状部分の組み合わせの場合には、透過状態におけるはみだし部分に、外部接続端子との異形状部分を含んでいる。そのことにより、設計制約上、局所的な異形状部分を設ける場合にも、限定された領域でありながら透過検査による判別できる。例えば、外部接続端子の円形状に対して、上記のはみだし部分には直線形状を形成するとよい。   Further, when the opening of the upper layer module connection pad is a combination of a circular shape and an irregular shape portion, the protruding portion in the transparent state includes an irregular shape portion with respect to the external connection terminal. As a result, even when a locally irregularly shaped portion is provided due to design constraints, it can be discriminated by transmission inspection even though it is a limited region. For example, with respect to the circular shape of the external connection terminal, a linear shape may be formed at the protruding portion.

さらに、上層モジュール接続パッド開口部の高さは、モジュール間接続端子高さの半分以下にするとよい。更に具体的には、モジュール間接続端子高さは300μm〜400μmであり、パッド表面に対するパッド開口部の高さは5μm〜20μmである。このようにパッド開口部高さを十分低くすることで、以下の効果が得られる。   Further, the height of the upper module connection pad opening may be less than half the height of the inter-module connection terminal. More specifically, the inter-module connection terminal height is 300 μm to 400 μm, and the height of the pad opening with respect to the pad surface is 5 μm to 20 μm. Thus, the following effects are acquired by making pad opening part height low enough.

本積層型モジュールの特徴的な接続不良として、上層モジュール接続用パッド表面に端子が接触して、電気的導通を一時的にだけ維持している場合がある。この現象は、端子の半田が加熱され溶融した後、パッドにぬれ広がらずに、そのまま固まった状態になり、それがパッド表面に接触するかしないかの位置でほぼ元の端子形状を維持することで生じる。パッド開口部の高さが接続端子に近い高さの場合には、パッドにぬれ広がっていない状態でも、形状がパッド開口部の側面にならって接続端子が溶融するため、上面からの透過形状ではパッド開口部の形状を呈してしまい、この不良現象を透過検査では区分できない。これに対して本発明では、パッド開口部の高さが、接続端子の高さの半分以下と低いため、上記接触のみの異常時とぬれ広がって接続された正常時が、底面の形状の差異によって簡易な透過検査において確認できる。   As a characteristic connection failure of this laminated module, there is a case where the terminal contacts the upper module connection pad surface and the electrical continuity is maintained only temporarily. This phenomenon is that after the solder of the terminal is heated and melted, it does not spread on the pad, but remains in a solid state and maintains its original terminal shape at the position where it touches the pad surface or not. It occurs in. When the height of the pad opening is close to the connection terminal, the connection terminal melts following the side of the pad opening even when the pad is not wet and spread. The shape of the pad opening is exhibited, and this defect phenomenon cannot be distinguished by transmission inspection. On the other hand, in the present invention, since the height of the pad opening is as low as half or less of the height of the connection terminal, there is a difference in the shape of the bottom surface when the contact only is abnormal and when the contact is spread and connected normally. Can be confirmed by simple transmission inspection.

本発明は、小型デバイス、携帯電話装置やデジタルスチールカメラ、ビデオカメラ等の各種の小型の電子機器の信頼性の向上に寄与する。   The present invention contributes to improving the reliability of various small electronic devices such as small devices, mobile phone devices, digital still cameras, and video cameras.

PK21 第1のパッケージ
PK22 第2のパッケージ
2 外部接続端子
3 開口部(上層モジュール接続用パッド開口部)
11 第1の基板
12 第1の半導体チップ
13 第1のチップ接続端子
14 導電性接着材
15 上層モジュール接続用パッド
16 アンダーフィル樹脂
20 絶縁膜
22 第2の半導体チップ
23 第1のチップ端子
24 突起電極
25 第2の基板
30 モジュール間接続端子
PK21 First package PK22 Second package 2 External connection terminal 3 Opening (upper module module pad opening)
11 First substrate 12 First semiconductor chip 13 First chip connection terminal 14 Conductive adhesive 15 Upper layer module connection pad 16 Underfill resin 20 Insulating film 22 Second semiconductor chip 23 First chip terminal 24 Protrusion Electrode 25 Second substrate 30 Module connection terminal

Claims (2)

一方の面に第1の半導体チップが実装され、前記第1の半導体チップの保持領域外に第2パッドがあり、他方の面の第1パッド上に半田からなる第1の接続端子を有する第1の基板と、
一方の面に第2の半導体チップが実装された第2の基板と、
前記第1の基板と前記第2の基板を積層して、前記第1の基板と前記第2の基板の間を接続する半田からなる第2の接続端子とを含む積層型半導体モジュールであって、
前記第2パッドは、開口部を有する絶縁膜で被覆され、
前記開口部の平面形状は、前記第1の接続端子の平面形状とは異なり、
前記第2の接続端子は、前記開口部を満たして前記第2パッドに接合され、
前記第1の基板と前記第2の基板との積層方向に透過検査した場合に前記開口部のピッチと前記第1の接続端子のピッチとは等しく、前記開口部の平面形状は、前記開口部の並びと前記第1の接続端子の並びとは平行するが位置が異なり、前記第1の接続端子から前記開口部の一部がはみ出しており、
前記開口部の平面形状は全部が多角形であり、前記第1の接続端子の平面形状は全部が円形状であり、
前記開口部の前記多角形の外形は、前記第1の接続端子の径より大きい
積層型半導体モジュール。
A first semiconductor chip is mounted on one surface, a second pad is provided outside the holding region of the first semiconductor chip, and a first connection terminal made of solder is provided on the first pad on the other surface. 1 substrate,
A second substrate a second semiconductor chip is mounted on one surface,
And laminating the first substrate and the second substrate, there in the stacked semiconductor module and a second connection terminal composed between the first substrate and the second substrate from the solder to connect And
The second pad is covered with an insulating film having an opening,
The planar shape of the opening, unlike the prior SL planar shape of the first connection terminal,
The second connection terminal fills the opening and is joined to the second pad,
When transmission inspection is performed in the stacking direction of the first substrate and the second substrate, the pitch of the openings is equal to the pitch of the first connection terminals, and the planar shape of the openings is the opening. The arrangement of the first connection terminals is parallel to the arrangement of the first connection terminals but the position is different, and a part of the opening protrudes from the first connection terminals,
The planar shape of the opening is all polygonal, and the planar shape of the first connection terminal is all circular.
The stacked semiconductor module , wherein the polygonal outer shape of the opening is larger than the diameter of the first connection terminal .
前記開口部の並びは、前記第1の接続端子の並びに対して、前記第1の基板の外周側に位置するThe arrangement of the openings is located on the outer peripheral side of the first substrate with respect to the arrangement of the first connection terminals.
請求項1記載の積層型半導体モジュール。The stacked semiconductor module according to claim 1.
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