TW201042751A - Semiconductor module for stacking and stacked semiconductor module - Google Patents

Semiconductor module for stacking and stacked semiconductor module Download PDF

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Publication number
TW201042751A
TW201042751A TW099115884A TW99115884A TW201042751A TW 201042751 A TW201042751 A TW 201042751A TW 099115884 A TW099115884 A TW 099115884A TW 99115884 A TW99115884 A TW 99115884A TW 201042751 A TW201042751 A TW 201042751A
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Taiwan
Prior art keywords
connection terminal
opening
shape
substrate
planar shape
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TW099115884A
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Chinese (zh)
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TWI518869B (en
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Takeshi Kawabata
Takashi Yui
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Panasonic Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

In a semiconductor module, a pad (15) is provided on the face of a first substrate (11) of a lower layer module connecting with an upper layer module; one part thereof is covered by an insulating film (20) to form an opening portion (3) exposing the pad (15); a first connecting terminal (2) is formed below the first substrate (11) of the lower layer module; the planary shape of the opening portion (3) is different from the planary shape of the first connecting terminal (2); the shape of the opening portion (3) is bigger than the first connecting terminal (2); even upon a penetration inspection from above, the shape of the lower end of a second connecting terminal (30) which enlarges at the opening portion (3) will not merge into the other end. In the way of non-destructive inspection, the detection of the bonding portion is proceeded easily and assuredly.

Description

201042751 六、發明說明: 【發明所屬之技術領域】 本發明係關於當積層複數個半導體裝置而構成時配置在 最下層的積層用半導體模組、及使用它的積層型半導體模 組。 【先前技術】 伴隨行動電話裝置及數位相機等各種電子機器的小型 Q 化、高功能化之要求,而正在開發電子構件,尤其是積層 複數個半導體裝置及晶片而一體化之積層型半導體模組 (Package on Package ) ° 在該積層型半導體模組之安裝中,隨著進一步高密度化 所造成上下封裝的連接良率及高功能化,有提高檢查感度 的問題,針對這些問題而謀求改善提高品質之檢查良率。 作爲過去的積層型半導體模組,已知有特開2004-363 126 號公報等。第8(a)圖顯示過去的積層型半導體模組,將 G 第2封裝PK2積層、安裝在第1封裝PK1上。 在第1封裝PK1的下面配置外部連接用端子2,在第1 封裝PK1的上面配置上下連接用端子1。在正常的製品中, 將上下連接端子1接合至形成在第1封裝PK1上面的上層 模組連接用墊15a上。又,上下連接端子1的連接面形狀 與外部連接用端子2的形狀皆爲類似圓形的形狀。又,如 第8圖(b)所示,上層模組連接用墊15a爲圓形。 在特開2000-2085 5 7號公報中記載,如第9圖所示,將已 201042751 設置在半導體裝置的基板Π之焊盤(land) 4本身形成爲 會在熱膨脹方向上變長的長方形、橢圓、長圓等,提高印 刷基板與半導體裝置的連接可靠性者。 通常,使用電性檢査來進行上下的半導體裝置間的連接 判定。即,一般是在上下間的連接狀態下、及在爲了進行 電性保證而在經上下連接之積層完成品狀態下實施再檢 查。 在該檢查中,將積層型半導體模組插入檢查裝置的插座 (socket),藉由施加來自上部的荷重來使第1封裝PK1 的外部連接用端子2與前述插座側的探針(probe )接觸, 通過積層型半導體模組的內部配線來進行第1封裝PK1與 第2封裝PK2之連接部的導通判定。 但是,在這種電性檢查中,第1封裝PK1與第2封裝PK2 之間的接合狀態,在非確實的接合,是否單純地接觸的微 妙情況下,會發生因上述檢查時的荷重而暫時導致第1封 裝PK1與第2封裝PK2之連接部的導通接觸的狀態,而有 被判定爲「電性上0K」通過檢查的情況。 因此,對於在上下的連接端子中,是否不僅是單純地接 觸而是上下牢固地物理性接合以維持連接的判定,可使用 X光檢査及超音波探傷法(SAT,Scanning Acoustic Tomograph)作爲非接觸透過檢查。 然而,這種透過檢查,係以目視判定非常耗時,即使利 用自動判定亦會因難以設定臨界値(threshold value )而使 201042751 得對於有無接合之不良判定非常困難。 具體而百,在第8圖(a) 、(b)所舉的例,由於整15a 的形狀爲圓形,外部連接用端子2亦爲球形狀的圓形狀, 所以在非接觸透過檢查中從上部透過積層型半導體模組會 一起成爲同一圓形狀。而且相對於上下接合狀態下的連接 面的圓形狀,在未接合狀態及非接觸狀態下皆可看到上部 端子的球平面形狀,一起成爲同形狀。此外,由於最下部 的端子、上部的端子等同形狀的連接端子係不分尺寸地混 〇 在一起,所以即使是在未接合的狀態下,乍看之下仍與已 接合狀態的大小及形狀相同,甚至亦與其他的連接端子爲 同一形狀,因此難以區別接合的地方及其他連接端子。 在特開2000-208557號公報中,揭露了以如第9圖所示將 焊盤4的形狀作成長方形’來提高半導體裝置之對印刷基 板的連接強度爲目的者。但是’其明顯不是針對如積層型 半導體模組般,當檢査在積層狀態下存在於上下的端子時 〇 所遭遇的問題者。 具體而言,只將專利文獻2中所見之長方形焊盤單純地 應用於上下的連接端子’因爲對於上下的連接端子之尺寸 差異及在各連接部位之形狀差異並不明確’而有在x光等 透過檢查中,最下部的端子、上下間的端子等同形狀的連 接端子會混在一起的可能性。 本發明之目的爲提供一種積層用半導體模組及積層型半 導體模組,其能容易且確實地進行以非破壞檢查來判定接 201042751 合部的好壞,藉此能使品質及可靠性提高。 【發明內容】 Ο[Technical Field] The present invention relates to a semiconductor module for lamination disposed at a lowermost level when a plurality of semiconductor devices are stacked, and a laminated semiconductor module using the same. [Prior Art] With the requirements of small-scale Q and high-performance of various electronic devices such as mobile phone devices and digital cameras, electronic components are being developed, in particular, laminated semiconductor modules in which a plurality of semiconductor devices and wafers are stacked. (Package on Package) ° In the mounting of the laminated semiconductor module, the connection yield and the high functionality of the upper and lower packages are further increased due to further increase in density, and the problem of improving the inspection sensitivity is improved, and improvement and improvement are required for these problems. Quality check yield. As a conventional laminated semiconductor module, JP-A-2004-363 126 and the like are known. Fig. 8(a) shows a conventional laminated semiconductor module in which a G second package PK2 is laminated and mounted on the first package PK1. The external connection terminal 2 is disposed on the lower surface of the first package PK1, and the upper and lower connection terminals 1 are disposed on the upper surface of the first package PK1. In a normal product, the upper and lower connection terminals 1 are joined to the upper module connection pad 15a formed on the upper surface of the first package PK1. Further, the shape of the connection surface of the upper and lower connection terminals 1 and the shape of the external connection terminals 2 are all circularly shaped. Further, as shown in Fig. 8(b), the upper module connection pad 15a has a circular shape. As described in FIG. 9, the land 4 which has been placed on the substrate of the semiconductor device in 201042751 is formed into a rectangular shape which is elongated in the thermal expansion direction, Ellipse, oblong, etc., improve the reliability of the connection between the printed circuit board and the semiconductor device. Usually, electrical connection is used to determine the connection between the upper and lower semiconductor devices. In other words, in general, in the state of connection between the upper and lower sides, and in the state of the laminated product which is connected up and down in order to perform electrical reliability, the re-inspection is carried out. In this inspection, the laminated semiconductor module is inserted into a socket of the inspection device, and the external connection terminal 2 of the first package PK1 is brought into contact with the probe on the socket side by applying a load from the upper portion. The conduction determination of the connection portion between the first package PK1 and the second package PK2 is performed by the internal wiring of the laminated semiconductor module. However, in such an electrical inspection, in a delicate state in which the joint state between the first package PK1 and the second package PK2 is not reliably joined, the load at the time of the inspection is temporarily generated. In a state in which the connection between the first package PK1 and the connection portion of the second package PK2 is in contact with each other, it is determined that the "electrical upper 0K" has passed the inspection. Therefore, whether or not the connection terminals in the upper and lower sides are not only simply contacted but firmly and physically joined to maintain the connection, X-ray inspection and ultrasonic spectroscopy (SAT) can be used as the non-contact. Pass the inspection. However, such a pass inspection is very time consuming by visual judgment. Even if the automatic judgment is used, it is difficult to determine the threshold value of 201042751, and it is very difficult to determine the presence or absence of the joint defect. Specifically, in the example of (a) and (b) of FIG. 8, since the shape of the entire 15a is circular, and the terminal 2 for external connection is also a spherical shape, it is in the non-contact transmission inspection. The upper transparent laminated semiconductor modules together have the same circular shape. Further, with respect to the circular shape of the joint surface in the upper and lower joined state, the spherical shape of the upper terminal can be seen in both the unjoined state and the non-contact state, and together they have the same shape. In addition, since the lowermost terminal and the upper terminal are equally shaped, the connection terminals are mixed together regardless of the size, so even in the unjoined state, the size and shape of the joined state are the same at first glance. Even with other connection terminals, it is difficult to distinguish the joints and other connection terminals. Japanese Patent Publication No. 2000-208557 discloses that the shape of the pad 4 is formed into a rectangular shape as shown in Fig. 9 to improve the connection strength of the semiconductor device to the printed substrate. However, it is obviously not intended for a problem such as a laminated semiconductor module when it is checked for a terminal which exists in the upper and lower layers in a laminated state. Specifically, only the rectangular pad seen in Patent Document 2 is simply applied to the upper and lower connection terminals 'because the difference in size between the upper and lower connection terminals and the difference in shape between the connection portions is not clear' In the inspection, the lowermost terminal and the terminal of the same shape of the upper and lower terminals may be mixed together. It is an object of the present invention to provide a semiconductor module for a laminate and a laminated semiconductor module which can easily and reliably determine the quality of the joint portion of the 201042751 by non-destructive inspection, thereby improving quality and reliability. SUMMARY OF THE INVENTION Ο

本發明之積層用半導體模組,其特徵爲,在已將第1半 導體晶片安裝在一面、已將第1連接端子形成於另一面的 第1基板之前述一面上,將可與上層模組電性連接的墊設 置在前述第1半導體晶片的保持區域外’在以被覆一部分 前述墊的方式形成在第1基板之前述一面的絕緣膜上,形 成以使前述墊露出的方式開口的開口部’前述開口部的平 面形狀與第1連接端子的平面形狀不同’在第1連接端子 及前述開口部的積層方向上進行透過檢查的狀態下前述開 口部的外形會從第1連接端子溢出。 又,本發明之積層型半導體模組,係在已將第1半導體 晶片安裝於一面之第1基板的前述一面上’積層已安裝第 2半導體晶片的第2基板’利用第2連接端子來連接第1 基板與第2基板之間以進行安裝,其特徵爲’將可與第2 基板電性連接的墊設置在第1基板之前述一面的第1半導 體晶片的保持區域外,在以被覆一部分前述墊的方式形成 在第1基板之前述一面的絕緣膜上’形成以使前述塾露出 的方式開口的開口部’前述開口部的平面形狀與第2連接 端子的平面形狀、及已形成在第1基板之另一面的弟1連 接端子的平面形狀不同’一端已連接至第2基板之第2連 接端子的另一端熔融、凝固,塡滿前述開口部而被接合至 前述墊,在第1連接端子及前述開口部的積層方向上進行 201042751 透過檢查的狀態下前述開口部的外形會從第2連接端子及 第1連接端子溢出。 依照該構成,積層型半導體模組,係使連接下層模組與 上層模組之第2連接端子的平面形狀、及已形成在第1基 板之另一面之第1連接端子的平面形狀,與第2連接端子 的前述另一端與第1基板側之前述墊的連接面形狀不同’ 在第1連接端子及前述開口部的積層方向上進行透過檢査 0 的狀態下前述開口部的外形會從第1連接端子溢出、或前 述開口部的外形比第2連接端子及第1連接端子還大’所 以在下層模組與上層模組的未接合狀態及接合狀態下形狀 明顯不同。況且,在從上方的透過檢查中’塡滿前述開口 部而與前述墊接合之第2連接端子的平面形狀不會被其他 端子隱蔽,所以能藉由從上部的透過檢查而容易地判別其 形狀差異。因此,能確實地檢查上層及下層模組的接合部, 能供給品質、可靠性高的半導體裝置及模組。 〇 【實施方式】 以下,基於第1圖〜第7圖說明本發明的實施形態》 第1圖(a)顯示本發明之積層型半導體模組。又,關於 端子、電極及配線等之個數及形狀,係省略或以容易圖示 的個數及形狀等來表示。在以下的全部圖式中做同樣的省 略等。 將第2封裝PK2 2積層、安裝在第1封裝PK21上。將第 1半導體晶片12安裝在第1封裝PK21上,將第2半導體 .201042751 晶片22安裝在第2封裝PK22之第2基板25的上面。 具體而言,第2封裝PK22爲泛用的積層用記憶體裝置, 將記億體等之第2半導體晶片22搭載在基板,使用線接合 (wire bond)及覆晶(flip chip)方法來將電極彼此間相互 地電性連接,視情況,可利用樹脂予以封裝及塗布以便被 覆半導體晶片。 第2圖顯示第1封裝PK21及第2封裝PK22的積層製程。 ^ 將與第1封裝PK21接合用之第2連接端子30形成在第2 封裝 PK22。一般是使用 SnPb、SnAgCu、SnCu、SnBi 等焊 錫材料之焊球,作爲構成連接端子30的接合金屬30。 將下層模組之積層用半導體模組之第1封裝PK21構成爲 如第3圖。 第1封裝PK21係利用第1基板Η、及已安裝在第1基 板11的晶片保持面之第1半導體晶片12來構成。 第1半導體晶片12係將已形成半導體元件的積體電路形 〇 成區域(未圖示)設置在平面方形狀的晶片基板中央部’ 將複數個第1晶片端子23配置在其外側。第1晶片端子23 一般是利用與用於形成積體電路配線的金屬相同的金屬來 形成,利用錦、銅、或銀及銅的積層材料等來形成。晶片 基板的表面,除了已形成第1晶片端子23的區域以外’係 利用聚醯亞胺等絕緣膜(未圖示)予以覆蓋。第1晶片端 子23亦可配置在積體電路形成區域內。以線接合方式或鍍 覆(plating )方式等周知方法來將突起電極24形成於第1 201042751 晶片端子23。 設置在第1晶片端子23的突起電極24可爲由焊錫、金、 銅' 及鎳等之任一者所構成的單體或由2者以上所構成之 積層體’形狀可爲球狀或柱狀的凸塊。 第1基板具有以芳族醯胺(Ar amid )樹脂、玻璃環氧樹 脂、聚醯亞胺樹脂或陶瓷等所形成的多層配線構造。在第 1基板11的晶片保持面,將複數個第1晶片連接端子13 0 設置在與已設置有第1半導體晶片12之突起電極24對應 的位置。 將第1半導體晶片12覆晶安裝在第1基板11,第1半導 體晶片12之突起電極24,係利用導電性接著材14來電性 連接至第1晶片連接端子13。進一步地,爲了補強第1半 導體晶片12與第1基板11的連接,在其間埋設底部塡料 樹脂(underfil resin) 16。亦可取代底部塡料樹脂16而使 用利用非導電性樹脂膜的硬化收縮來連接的方法等,進行 〇 第1半導體晶片12與第1基板11的連接。 在第1基板11之晶片保持面的相反側的面(背面),將 複數個外部連接用之第1連接端子2配置成等間隔的彳各+ 狀。第1連接端子2能與印刷基板之外部基板(未圖示) 電性連接。作爲第1連接端子2的材料,通常是搭載由 SnPb、SnAgCu、SnCu、SnBi之焊錫材料,或是金、銅、或 錬等所構成之球形狀者’能藉由在熔點以上進行迴流加熱 而熔融接合至第1基板11。又,亦能使用在表面層進行金 -10- 201042751 屬蒸著等以賦予導電性的樹脂球來作爲第1連接端子2。 在第1基板11晶片保持面中之第1半導體晶片12保持 區域的外側部分設置複數個上層模組連接用墊15,其用以 與作爲積層型半導體模組的上層模組之第2封裝PK22連 接。進一步地,在墊1 5上’利用如防焊阻劑(s ο 1 d e r r e s i s t ) 或聚醯亞胺等之絕緣膜20來被覆一部分,且利用上層模組 連接用的開口部3來使墊15的一部分露出。從開口部3露 ^ 出的部分會施加鍍鎳、金等鍍覆(Plating )的表面處理, Ο 防止下層的墊氧化。第1基板11之晶片保持面的相反面(背 面)除了已形成第1連接端子2之部分等以外,形成有防 焊阻劑或聚醯亞胺等之絕緣膜20。 第4圖顯示第1封裝PK21的第1基板1 1的細部。 第4圖中除了顯示第3圖的平面圖以外,亦合倂第1連 接端子2的投影圖。 在此,相對於開口部3的開口形狀爲四角形狀,由於第 〇 1連接端子2爲焊球,所以其形狀作成圓形狀,因此兩者 作成不同的平面形狀。而且’開口部3的外形比外部連接 用端子2還大。 在此實施形態’有第1封裝PK21的開口部3與第1連接 端子2的形狀差異大的特徵。藉此,能藉由如下說明的非 接觸透過檢查而簡易地檢測第1封裝PK21及第2封裝PK22 的連接狀態。 對如此所構成的第1封裝PK21’在以第2圖所示方式搭 -11- 201042751 載第2封裝PK22的狀態下,藉由利用連接端子30 熔點以上的迴流加熱來熔融、凝固,將連接端子30 焊錫接合至第1封裝PK21側的墊15,透過連接端^ 將第1封裝PK21電性連接至第2封裝PK22。 已熔融之連接端子30會因以沿著開口部3形狀的 濕擴展、凝固而使底面成爲與開口部3的開口形狀 同的形狀。第1圖(b)爲顯示在依此所形成之積層 _ 體模組之第2封裝PK22與一個連接端子30的連接 〇 剖面圖,第1圖(C)爲顯示第1封裝PK21與一個 子30的連接面B的剖面圖,第1圖(d)爲顯示第 PK21與一個第1連接端子2的連接面C的剖面圖。 如此以連接端子30之已凝固成分予以塡滿的正 的情況之開口部3的四角形,在利用X光透過裝置 方向透過觀察積層型半導體模組的情況下,由於連 30的底面會擴展至整體開口部3,而且,由於將開 Q 的四角形狀的外形形成爲比第1連接端子2還大, 以X光等從上部進行透過觀察中,即使連接端子30 疊於下層模組的第1連接端子2的位置,也不會隱 端子30的連接面的畫像,如第4圖所示連接端子 面即開口部3的四角形狀會從位於其下方的第1連 2的影子溢出而能觀察到。 對此,假如一旦發生潤濕不良之未接合的情況, 5圖(a)所示之連接端子30左側的P般發生接合^ 的材料 的下端 F 30而 形狀潤 幾乎相 型半導 面A的 連接端 1封裝 常狀態 從上部 接端子 口部3 因此在 處在重 蔽連接 30的底 .接端子 及如第 =良,則 -12- 201042751 由於連接端子30的底面不會被擴展至整體開口部3,所以 形成近似原來的連接端子30形狀的圓形狀之底面。在利用 X光透過裝置等從上部方向透過觀察該接合不良之積層型 半導體模組的情況下,開口部3及墊本身,由於本身厚度 薄到10# m〜20 y m而無法拍出鮮明的透過畫像,只有比其 相對厚的,例如具有100/zm以上厚度之連接端子30之未 接合的端子畫像會被以圓形狀而極鮮明地反映出來。顯示 Q 出如第5圖(b)所示之接合不良的地方P的檢測例。 如由比較第5圖(a )與第5圖(b )所得知,由於能夠 分別確認:正常接合時成爲四角形、未接合時成爲原來的 連接端子形狀之圓形,所以能簡易地檢測第1封裝PK2 1 與第2封裝PK22的連接狀態。因此,能以第3圖所示構造 之第1封裝PK2 1作爲下層模組來使用而組裝積層型半導體 模組,藉以僅利用簡單的檢查製程來實現高可靠性的積層 型半導體模組。 3 又,在上述實施形態中,雖然是舉開口部3的形狀爲四 角形的情況爲例來說明,但是亦可爲角部比四角形還多的 多角形。將具體例顯示於第6圖(a)〜(e)。 第6圖(a )係開口部3的形狀爲十字形的情況,第6圖 (b)係開口部3的形狀爲正方形且在角落(corner )附加 R角的情況,第6圖(c )係開口部3的形狀爲五角形的情 況,第6圖(d)係開口部3的形狀爲正方形且在角落部分 附加向內側突出之R角的情況,第6圖(e )係開口部3的 -13- 201042751 形狀爲一部分變形的變形橢圓形的情況。不論是何種情 況’都是把開口部3的多角形外形做得比第1連接端子2 的徑還大。如此,亦可爲十字形、在角部設置r角者、五 角形、在邊的一部分包含圓弧般的多角形、全部爲曲線但 有角的多角形等。 又,相較於未在開口部3的角落部分附加R角的情況, 藉由在開口部3的角落部分附加R角,能有效地減少阻劑 q 殘渣及異物殘渣。 又’開口部3的大小,只要是可包括第1連接端子2的 整體徑的大小即可,只要是作成可隱蔽其整體形狀的大小 即可。例如,實際上是以0.0 1 mm以下程度作爲外部端子徑 的變異水準,由於開口尺寸的變異亦爲0.01 mm程度,所以 較佳爲作成比端子徑大平方平均的0.015 mm以上。藉此, 不會隱藏在幾乎全部的外部連接用端子徑,而能確認在開 口部的連接面。 Ο 具體而言,相對於Φ0.3隨程度的球徑,只要設定爲比口 0.3 15刪還大的四角形的多角形形狀即可。又,在投影面上 看到開口部3及第1連接端子2的情況下,一旦可看到開 口部3的多角形形狀的直線部及角部,便可容易地明確分 辨出與圓形狀的差異。 又,在下層模組中,亦能將上層模組的開口部3的間距 (pitch )與第1連接'端子2的間距定爲相等。一旦間距相 等,則如第7圖所示上層及下層模組的外部連接用端子’ -14- 201042751 係相同的圓形狀以幾乎同樣的尺寸來等間隔排列,因此難 以利用如上述之來自上部的X光及SAT等檢查來進行判 別,但在本實施形態中,如第4圖所示上層模組PK22所連 接的下層模組的開口部30爲多角形,爲與下層模組之第1 連接端子2的圓形狀不同的形狀,其外形由於比下層模組 之第1連接端子2的徑還大,所以能夠容易在透過觀察中 判別。 0 進一步地,在對如上述的下層模組接合、積層具有泛用 球形狀的連接端子30之上層模組的情況下,在積層型半導 體模組的狀態下上層模組之連接端子30底面呈現多角形 的形狀,未接合的部位仍以圓形狀殘留著。除了如此形狀 差異外,亦爲比上層模組的連接端子3 0的徑還大者。因 此,能在利用X光等從上部進行透過檢查中清楚地判別有 無接合。 當在未比連接端子30的徑還大的情況下,從上部透過而 Ο 進行觀察時,底面的多角形形狀會隱藏在連接端子30本 身,作爲透過畫像可看到其端子徑的圓形狀,而有不能與 未接合的情況判別的情況。又,上述連接端子的底面形狀 變化係僅在連接前後,即積層前後,上下之各自的半導體 模組的製造製程中,完全沒有特殊的加工,僅將墊的形狀 作成如上述的多角形,所以即使使用既存製程、泛用的模 組也是容易的。又,在投影面上看到開口部及外部連接用 端子的情況下,一旦可看到開口部的多角形形狀的直線部 -15- 201042751 及角部,便容易地明確分辨出與圓形狀的差異。即在此’ 開口部3的形狀爲多角形,連接端子30的底面也是多角 形。就其尺寸而言,比上層模組的連接端子30的徑還大。 或者是比下層模組之第1連接端子2的徑還大。此外亦可 比雙方都大。 在上述各實施形態中,開口部3的平面形狀與第1連接 端子2的平面形狀不同,將開口部3的外形作成比第1連 Q 接端子2還大,但開口部3的平面形狀與第1連接端子2 的平面形狀不同,在第1連接端子2與開口部3的積層方 向上進行透過檢查的狀態下即使開口部3的外形從第1連 接端子2溢出亦能期待同樣的效果。 在上述的各實施形態中,開口部3的平面形狀係與連接 端子30的平面形狀、及已形成在第1基板11的另一面的 第1連接端子2的平面形狀不同,一端已連接至第2基板 25之連接端子30的另一端熔融、凝固,塡滿開口部3而接 D 合於墊15,將開口部3的外形作成比連接端子3 0及第1 連接端子2還大,但是開口部3的平面形狀係與連接端子 30的平面形狀、及已形成在第1基板11之另一面的第1 連接端子2的平面形狀不同,一端已連接至第2基板25之 連接端子3 0的另一端熔融、凝固,塡滿開口部3而接合於 墊15,在第1連接端子2及開口部3的積層方向上進行透 過檢査的狀態下即使開口部3的外形從連接端子30及第1 連接端子2溢出亦能期待同樣的效果。 -16- 201042751 又,在上述各 間連接端子,在 的積層方向上進 口部的外形可從 情況,因爲能利 不良,所以亦能 又,在上層模 0 形狀部分的情況 連接端子不同形 不同形狀部分的 進行判別。例如 線形狀形成在上 進一步地,上 間連接端子高度 子筒度爲3 0 0 /z Ο " m~20 " m。藉 得以下的效果。 作爲本積層型 層模組連接用墊 此現象之發生是 墊上潤濕擴展, 接觸於墊表面的 部的高度接近連 實施形態中,針對檢查對象之全部的模組 外部連接端子及上層模組連接用墊開口部 行透過檢查的狀態下上層模組連接用墊開 模組間連接端子及外部連接端子溢出。此 用簡易的透過檢查來判別檢查對象的全部 將開路及短路的電性檢查全部取消。 組連接用墊的開口部爲組合圓形狀與不同 下,在透過狀態中之溢出部分包含與外部 狀部分。依此,在設計限制上,設置局部 情況下,能在已限定的區域利用透過檢查 ,相對於外部連接端子的圓形狀,可將直 述溢出的部分。 層模組連接墊開口部的高度,可設爲模組 的一半以下。更具體而言,模組間連接端 m〜400/zm,墊開口部對墊表面的高度爲5 由如此地將墊開口部高度充分降低,可獲 模組之特徵性接觸不良,有端子接觸於上 表面,而僅暫時地維持電性導通的情況。 因爲在端子的焊錫被加熱、熔融後,未在 而是成爲直接凝固的狀態,其在接觸或未 位置維持幾乎原來的端子形狀。在墊開口 接端子高度的情況下,由於即使是未在墊 -17- 201042751 上潤濕擴展的狀態,形狀亦會循著墊開口部的側面而連接 端子熔融,所以從上面的透過形狀會呈現出墊開口部的形 狀’而不能利用透過檢査來區分該不良現象。對此,在本 發明中,由於墊開口部高度低到連接端子高度的一半以 下’所以能藉由底面形狀的差異而在簡易的透過檢查中確 認:只有上述接觸之異常時、及已潤濕擴展而被連接之正 常時。 0 本發明,有助於提高小型裝置、行動電話裝置及數位相 機、攝影機等各種小型電子機器的可靠性。 【圖式簡單說明】 第1圖係在本發明之實施形態中(a)積層型半導體模 組的剖面圖,(b)連接面A的剖面圖,(c)連接面B的 剖面圖,(d )連接面C的剖面圖。 第2圖係在同實施形態中積層型半導體模組之製造方 法的說明圖。 〇 第3圖係在同實施形態中積層用半導體裝置之下層模 組的剖面圖。 第4圖係在同實施形態中第1基板1 1之投影狀態的平 面圖。 第5圖係在同實施形態中(a )積層型半導體模組之一 部分未接合情況的剖面圖,(b)從上部方向藉由X光透過 裝置進行透過觀察的情況之畫像。 第6圖係顯示在同實施形態中開口部形狀的放大平面 -18- 201042751 圖 第7圖係問題的說明圖。 第8圖係記載於過去例之積層型半導體模組的剖面圖 及下層模組的接合面之平面圖。 第9圖係顯示記載於其他過去例之焊盤形狀的平面圖。 【主要元件符號說明】 ΟThe semiconductor module for a laminate according to the present invention is characterized in that the first semiconductor wafer is mounted on one surface of the first substrate on which the first connection terminal is formed on the other surface, and the upper module can be electrically connected. The pad to be connected is provided outside the holding region of the first semiconductor wafer, and is formed on the insulating film formed on the one surface of the first substrate so as to cover a part of the pad, and an opening portion that opens to expose the pad is formed. In the state in which the planar shape of the opening is different from the planar shape of the first connection terminal, the outer shape of the opening overflows from the first connection terminal in a state where the transmission inspection is performed in the stacking direction of the first connection terminal and the opening. Further, in the laminated semiconductor module of the present invention, the second substrate 'the second semiconductor wafer on which the second semiconductor wafer is mounted is stacked on the one surface of the first substrate on which the first semiconductor wafer is mounted is connected by the second connection terminal. The first substrate and the second substrate are mounted together, and the pad electrically connected to the second substrate is provided outside the holding region of the first semiconductor wafer on the one surface of the first substrate, and is covered with a portion. The pad is formed on the insulating film on the one surface of the first substrate, and an opening portion that opens to expose the ridge is formed. The planar shape of the opening and the planar shape of the second connection terminal are formed. The other side of the first substrate has a different planar shape. The other end of the second connection terminal that is connected to the second substrate is melted and solidified, and the opening is filled and joined to the pad, and the first connection is made. When the terminal and the opening are stacked in the direction of the 201042751 transmission, the outer shape of the opening overflows from the second connection terminal and the first connection terminal. According to this configuration, the laminated semiconductor module has a planar shape in which the second connection terminal of the lower module and the upper module is connected, and a planar shape of the first connection terminal formed on the other surface of the first substrate, and In the state in which the other end of the connection terminal is different from the shape of the connection surface of the pad on the first substrate side, the outer shape of the opening is from the first state in the state where the transmission inspection 0 is performed in the lamination direction of the first connection terminal and the opening. When the connection terminal overflows or the outer shape of the opening portion is larger than the second connection terminal and the first connection terminal, the shape is significantly different between the lower module and the upper module in the unjoined state and the joined state. In addition, in the transmission inspection from the top, the planar shape of the second connection terminal that is joined to the pad by the opening is not concealed by the other terminal, so that the shape can be easily discriminated by the inspection from the upper portion. difference. Therefore, the joint portion between the upper layer and the lower layer module can be reliably inspected, and a semiconductor device and a module having high quality and reliability can be supplied. [Embodiment] Hereinafter, an embodiment of the present invention will be described based on Fig. 1 to Fig. 7. Fig. 1(a) shows a laminated semiconductor module of the present invention. Further, the number and shape of the terminals, the electrodes, the wirings, and the like are omitted or indicated by the number and shape of the drawings. Do the same in all of the following figures. The second package PK2 2 is laminated and mounted on the first package PK21. The first semiconductor wafer 12 is mounted on the first package PK21, and the second semiconductor 201042751 wafer 22 is mounted on the upper surface of the second substrate 25 of the second package PK22. Specifically, the second package PK22 is a general-purpose memory device for lamination, and the second semiconductor wafer 22 such as a billion-body is mounted on a substrate, and a wire bond and a flip chip method are used. The electrodes are electrically connected to each other, and may be packaged and coated with a resin to coat the semiconductor wafer, as the case may be. Fig. 2 shows a lamination process of the first package PK21 and the second package PK22. ^ The second connection terminal 30 for bonding to the first package PK21 is formed in the second package PK22. A solder ball of a solder material such as SnPb, SnAgCu, SnCu, or SnBi is generally used as the bonding metal 30 constituting the connection terminal 30. The first package PK21 of the semiconductor module for stacking the lower layer module is constructed as shown in Fig. 3. The first package PK21 is configured by using the first substrate Η and the first semiconductor wafer 12 mounted on the wafer holding surface of the first substrate 11. In the first semiconductor wafer 12, an integrated circuit formation region (not shown) in which a semiconductor element is formed is provided in a central portion of a wafer substrate having a planar shape. A plurality of first wafer terminals 23 are disposed outside. The first wafer terminal 23 is generally formed of the same metal as that used to form the integrated circuit wiring, and is formed of a laminate material of brocade, copper, or silver or copper. The surface of the wafer substrate is covered with an insulating film (not shown) such as polyimide, except for the region where the first wafer terminal 23 is formed. The first chip terminal 23 may also be disposed in the integrated circuit formation region. The bump electrode 24 is formed on the first 201042751 wafer terminal 23 by a known method such as a wire bonding method or a plating method. The protruding electrode 24 provided on the first wafer terminal 23 may be a single body composed of solder, gold, copper, or nickel, or a laminated body composed of two or more. The shape may be a spherical shape or a column. Bumps. The first substrate has a multilayer wiring structure formed of an aromatic amide, a glass epoxy resin, a polyimide resin, or a ceramic. On the wafer holding surface of the first substrate 11, a plurality of first wafer connection terminals 13 0 are provided at positions corresponding to the bump electrodes 24 on which the first semiconductor wafer 12 is provided. The first semiconductor wafer 12 is flip-chip mounted on the first substrate 11, and the bump electrode 24 of the first semiconductor wafer 12 is electrically connected to the first wafer connection terminal 13 by the conductive material 14. Further, in order to reinforce the connection between the first semiconductor wafer 12 and the first substrate 11, a bottom underfill resin 16 is buried therebetween. The first semiconductor wafer 12 and the first substrate 11 may be connected to each other by a method of joining the base resin 16 and curing by shrinkage of the non-conductive resin film. On the surface (back surface) on the opposite side of the wafer holding surface of the first substrate 11, a plurality of first connection terminals 2 for external connection are arranged at equal intervals. The first connection terminal 2 can be electrically connected to an external substrate (not shown) of the printed circuit board. The material of the first connection terminal 2 is usually a solder material made of SnPb, SnAgCu, SnCu, or SnBi, or a ball shape made of gold, copper, or tantalum, which can be reflowed by melting point or higher. The first substrate 11 is melt-bonded. Further, it is also possible to use, as the first connection terminal 2, a resin ball which is made of gold in the surface layer, such as steaming or the like, to impart conductivity. A plurality of upper module connection pads 15 are provided on the outer portion of the first semiconductor wafer 12 holding region in the wafer holding surface of the first substrate 11 for use in the second package PK22 of the upper module as the laminated semiconductor module. connection. Further, a part of the pad 15 is covered with an insulating film 20 such as a solder resist or a polyimide, and the pad 15 is connected by the opening 3 for the upper module connection. Part of it is exposed. The surface exposed from the opening 3 is subjected to a surface treatment such as plating of nickel or gold to prevent oxidation of the underlying pad. On the opposite surface (back surface) of the wafer holding surface of the first substrate 11, an insulating film 20 such as a solder resist or a polyimide is formed in addition to the portion where the first connection terminal 2 is formed. Fig. 4 shows a detail of the first substrate 11 of the first package PK21. In the fourth drawing, in addition to the plan view of Fig. 3, a projection view of the first connection terminal 2 is also incorporated. Here, since the opening shape of the opening portion 3 has a square shape, since the first connecting terminal 2 is a solder ball, the shape thereof is rounded, so that the two have different planar shapes. Further, the outer shape of the opening portion 3 is larger than the external connection terminal 2. In this embodiment, the difference between the shape of the opening 3 of the first package PK21 and the first connection terminal 2 is large. Thereby, the connection state of the first package PK21 and the second package PK22 can be easily detected by the non-contact transmission inspection described below. In the state in which the first package PK21' is placed in the second package PK22 in the manner shown in FIG. 2, the first package PK21' is melted and solidified by reflow heating at a temperature equal to or higher than the melting point of the connection terminal 30. The terminal 30 is solder-bonded to the pad 15 on the first package PK21 side, and the first package PK21 is electrically connected to the second package PK22 through the connection terminal. The molten connecting terminal 30 has a shape in which the bottom surface has the same shape as the opening of the opening portion 3 due to wet expansion and solidification along the shape of the opening portion 3. Fig. 1(b) is a cross-sectional view showing the connection between the second package PK22 and the one connection terminal 30 of the laminated body module formed in this manner, and Fig. 1(C) is a view showing the first package PK21 and one sub-package. A cross-sectional view of the connection face B of 30, and Fig. 1(d) is a cross-sectional view showing a connection surface C of the first PK 21 and one first connection terminal 2. When the quadrangular shape of the opening portion 3 in the positive state in which the solidified component of the connection terminal 30 is full is observed, when the laminated semiconductor module is viewed through the X-ray transmission device, the bottom surface of the connection 30 is expanded to the whole. In the opening portion 3, the outer shape of the quadrangular shape in which the Q is opened is formed larger than that of the first connection terminal 2, and the first connection of the connection terminal 30 is superimposed on the lower layer module when the transmission is observed from the upper portion by X-ray or the like. The position of the terminal 2 does not obscure the image of the connection surface of the terminal 30. As shown in Fig. 4, the four-corner shape of the opening portion 3, which is the connection terminal surface, overflows from the shadow of the first connection 2 located below it, and can be observed. . On the other hand, if the wettability is not joined, the P on the left side of the connection terminal 30 shown in Fig. 5(a) is similar to the lower end F30 of the material of the bonding, and the shape is almost the same as the semi-conductive surface A. The connection end 1 is packaged in a normal state from the upper terminal port 3 and thus at the bottom of the heavy connection 30 and as in the case of the first connection, -12-201042751 since the bottom surface of the connection terminal 30 is not extended to the overall opening Since the portion 3 is formed, a bottom surface of a circular shape that approximates the shape of the original connecting terminal 30 is formed. When the laminated semiconductor module in which the bonding failure is observed from the upper direction by the X-ray transmitting device or the like is used, the opening portion 3 and the pad itself cannot be sharply transmitted because the thickness thereof is as thin as 10 # m to 20 μm. The image is only relatively thick, and for example, the unjoined terminal image of the connection terminal 30 having a thickness of 100/zm or more is reflected in a round shape. The detection example of the place P where the joint failure is shown as shown in Fig. 5(b) is shown. As can be seen from the comparison of Fig. 5 (a) and Fig. 5 (b), it can be confirmed that the first connection is formed into a square shape when the normal connection is made, and the original connection terminal shape is circular when the connection is not performed. Therefore, the first detection can be easily performed. The connection state of the package PK2 1 and the second package PK22. Therefore, the first package PK2 1 having the structure shown in Fig. 3 can be used as a lower layer module to assemble a laminated semiconductor module, whereby a highly reliable laminated semiconductor module can be realized by a simple inspection process. Further, in the above-described embodiment, the case where the shape of the opening portion 3 is a quadrangular shape is described as an example, but a polygonal shape having more corner portions than the square shape may be used. Specific examples are shown in Fig. 6 (a) to (e). Fig. 6(a) shows a case where the shape of the opening 3 is a cross, and Fig. 6(b) shows a case where the shape of the opening 3 is square and an R angle is added to a corner, and Fig. 6(c) The shape of the opening portion 3 is a pentagonal shape, and the shape of the opening portion 3 in Fig. 6(d) is a square shape, and an R angle protruding inward is added to the corner portion. Fig. 6(e) shows the opening portion 3 -13- 201042751 The case of a deformed ellipse whose shape is partially deformed. In any case, the polygonal shape of the opening portion 3 is made larger than the diameter of the first connection terminal 2. In this case, it may be a cross shape, an angle of r at the corner, a pentagon, a polygon having an arc at a part of the side, a polygon having a curved shape but an angle, and the like. Further, in the case where the R angle is not added to the corner portion of the opening portion 3, by adding the R angle to the corner portion of the opening portion 3, the resist q residue and the foreign matter residue can be effectively reduced. Further, the size of the opening portion 3 may be a size that can include the overall diameter of the first connection terminal 2, and may be a size that can be concealed as a whole shape. For example, in practice, the variation level of the external terminal diameter is about 0.01 mm or less, and since the variation in the opening size is also about 0.01 mm, it is preferable to form a square of 0.015 mm or more larger than the terminal diameter. Thereby, the terminal diameter for the external connection is not concealed, and the connection surface of the opening portion can be confirmed. Specifically, the spherical diameter with respect to Φ0.3 may be set to a polygonal shape having a square shape larger than the mouth 0.315. Moreover, when the opening 3 and the first connection terminal 2 are seen on the projection surface, the polygonal portion and the corner portion of the polygonal shape of the opening 3 can be seen, and the circular shape can be easily and clearly distinguished. difference. Further, in the lower module, the pitch of the opening 3 of the upper module and the pitch of the first connection 'terminal 2 can be made equal. When the pitches are equal, as shown in Fig. 7, the external connection terminals '-14- 201042751 of the upper and lower modules are arranged at equal intervals in almost the same size, so that it is difficult to use the upper portion as described above. In the present embodiment, the opening portion 30 of the lower module connected to the upper module PK22 shown in FIG. 4 has a polygonal shape and is the first connection with the lower module. Since the shape of the terminal 2 having a different circular shape is larger than the diameter of the first connection terminal 2 of the lower module, it can be easily discriminated in the transmission observation. Further, in the case where the lower module is joined as described above and the upper module of the connection terminal 30 having the general spherical shape is laminated, the bottom surface of the connection terminal 30 of the upper module is presented in the state of the laminated semiconductor module. In the shape of a polygon, the unjoined portion remains in a circular shape. In addition to such a shape difference, it is also larger than the diameter of the connection terminal 30 of the upper module. Therefore, it is possible to clearly discriminate whether or not the joint is made by performing inspection of the permeation from the upper portion by X-ray or the like. When it is not larger than the diameter of the connection terminal 30, when viewed from the upper portion and viewed from the upper portion, the polygonal shape of the bottom surface is hidden in the connection terminal 30 itself, and the circular shape of the terminal diameter can be seen as a transmission image. There is a case where it is impossible to distinguish from the case where it is not joined. Further, the shape change of the bottom surface of the connection terminal is not particularly processed in the manufacturing process of the semiconductor modules before and after the connection, that is, before and after the lamination, and only the shape of the pad is formed as the above-described polygonal shape. Even using existing processes and common modules is easy. In addition, when the opening portion and the external connection terminal are seen on the projection surface, the polygonal portion -15-201042751 and the corner portion of the polygonal portion of the opening can be clearly seen and clearly distinguished from the circular shape. difference. Namely, the shape of the opening portion 3 is polygonal, and the bottom surface of the connection terminal 30 is also polygonal. In terms of its size, it is larger than the diameter of the connection terminal 30 of the upper module. Or it is larger than the diameter of the first connection terminal 2 of the lower module. It can also be larger than both parties. In each of the above embodiments, the planar shape of the opening 3 is different from the planar shape of the first connection terminal 2, and the outer shape of the opening 3 is made larger than that of the first connection Q terminal 2, but the planar shape of the opening 3 is When the first connection terminal 2 has a different planar shape, the same effect can be expected even if the outer shape of the opening 3 overflows from the first connection terminal 2 in a state where the first connection terminal 2 and the opening 3 are in the inspection direction. In each of the above embodiments, the planar shape of the opening 3 is different from the planar shape of the connection terminal 30 and the planar shape of the first connection terminal 2 formed on the other surface of the first substrate 11, and one end is connected to the first The other end of the connection terminal 30 of the substrate 25 is melted and solidified, and the opening portion 3 is filled and D is bonded to the pad 15. The outer shape of the opening portion 3 is made larger than the connection terminal 30 and the first connection terminal 2, but the opening is opened. The planar shape of the portion 3 is different from the planar shape of the connection terminal 30 and the planar shape of the first connection terminal 2 formed on the other surface of the first substrate 11, and one end is connected to the connection terminal 30 of the second substrate 25. The other end is melted and solidified, and the opening portion 3 is filled and joined to the mat 15 , and the outer shape of the opening portion 3 is obtained from the connection terminal 30 and the first state in a state where the transmission inspection is performed in the stacking direction of the first connection terminal 2 and the opening 3 . The same effect can be expected if the connection terminal 2 overflows. -16- 201042751 In addition, in the connection direction of each of the above-mentioned connection terminals, the outer shape of the inlet portion can be used in the stacking direction, and since it can be disadvantageous, the connection terminals can be differently shaped and shaped in the case of the upper mold 0 shape portion. Part of the discrimination. For example, the shape of the line is formed above. Further, the height of the upper connection terminal is 3 0 0 /z Ο " m~20 " m. The following effects can be obtained. As a laminated layer module connection pad, this phenomenon occurs when the pad is wetted and spread, and the height of the portion contacting the pad surface is close to that of the embodiment, and the module external connection terminal and the upper module connection for all the inspection objects are connected. In the state in which the opening of the pad is passed through the inspection, the connection module between the upper module connection pad and the external connection terminal overflow. This uses a simple inspection to determine the total number of inspection objects. All electrical inspections for open and short circuits are canceled. The opening portion of the group connection pad has a combined circular shape and is different, and the overflow portion in the transmission state includes the outer portion. Accordingly, in the case of design limitation, the transmission inspection can be utilized in the limited area, and the overflowed portion can be directly described with respect to the circular shape of the external connection terminal. The height of the opening of the layer module connection pad can be set to be less than half of the module. More specifically, the connection between the modules is 400 to 400 m, and the height of the pad opening to the surface of the pad is 5, so that the height of the opening of the pad is sufficiently lowered, and the characteristic contact of the module is poor, and the terminal is in contact. On the upper surface, only the electrical conduction is temporarily maintained. Since the solder of the terminal is heated and melted, it is in a state of being directly solidified, and it maintains almost the original terminal shape at the contact or non-position. In the case where the pad is open to the height of the terminal, since the shape is followed by the side of the opening of the pad and the connection terminal is melted even if it is not wetted and extended on the pad -17-201042751, the transmission shape from the top is presented. The shape of the opening of the pad is 'out of view' and the penetration inspection cannot be used to distinguish the problem. On the other hand, in the present invention, since the height of the pad opening portion is as low as half or less of the height of the connection terminal, it can be confirmed by a simple transmission inspection by the difference in the shape of the bottom surface: only the abnormality of the above contact, and the wetting When extended and connected to normal. The present invention contributes to improving the reliability of various small electronic devices such as small devices, mobile phone devices, digital cameras, and video cameras. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a laminated semiconductor module in (a) a laminated semiconductor module, (b) a cross-sectional view of the connecting surface A, and (c) a cross-sectional view of the connecting surface B, ( d) A sectional view of the joint surface C. Fig. 2 is an explanatory view showing a method of manufacturing a laminated semiconductor module in the same embodiment. Fig. 3 is a cross-sectional view showing a layer module of a semiconductor device for lamination in the same embodiment. Fig. 4 is a plan view showing a projection state of the first substrate 11 in the same embodiment. Fig. 5 is a cross-sectional view showing the case where (a) one of the laminated semiconductor modules is not joined, and (b) an image of the case where the upper side is observed by the X-ray transmitting device. Fig. 6 is an enlarged plan showing the shape of the opening in the same embodiment -18 - 201042751 Fig. 7 is an explanatory view of the problem. Fig. 8 is a plan view showing a cross-sectional view of a laminated semiconductor module of the past example and a joint surface of the lower module. Fig. 9 is a plan view showing the shape of a pad described in another conventional example. [Main component symbol description] Ο

1 上下連接用端子 2 第1連接端子、外部連接用端子 3 開口部 4 焊盤 11 第1基板、基板 12 第1半導體晶片 13 第1晶片連接端子 14 導電性接著材 15 墊 16 底部塡料樹脂 20 絕緣膜 22 第2半導體晶片 23 第1晶片端子 24 突起電極 25 第2基板 30 第2連接端子 A、Β、C 連接面 -19- 201042751 p PKl、 PK2、 接合不良的地方 PK21 第1封裝 PK22 第2封裝1 Upper and lower connection terminal 2 First connection terminal, external connection terminal 3 Opening part 4 Pad 11 First substrate, substrate 12 First semiconductor wafer 13 First wafer connection terminal 14 Conductive material 15 Pad 16 Bottom resin 20 Insulating film 22 Second semiconductor wafer 23 First wafer terminal 24 Projection electrode 25 Second substrate 30 Second connection terminal A, Β, C Connection surface -19- 201042751 p PKl, PK2, poor bonding PK21 1st package PK22 Second package

-20--20-

Claims (1)

201042751 七、申請專利範圍: 1. 一種積層用半導體模組,係在已將第1半導體晶片安裝 在一面,已將第1連接端子形成於另一面的第1基板之 前述一面上,將可與上層模組電性連接的墊設置在前述 第1半導體晶片的保持區域外, 在以被覆一部分前述墊的方式形成在第1基板之前述 一面的絕緣膜上,形成以使前述墊露出的方式開口的開 〇 口部’ 前述開口部的平面形狀與第1連接端子的平面形狀不 同,在第1連接端子及前述開口部的積層方向上進行透 過檢查的狀態下前述開口部的外形會從第1連接端子溢 出。 2. 如申請專利範圍第1項之積層用半導體模組,其中前述 開口部的間距(pitch )與第1連接端子的間距是相等的。 3. 如申請專利範圍第1項之積層用半導體模組,其中前述 〇 開口部的外形比第1連接端子還大。 4. 如申請專利範圍第1項之積層用半導體模組,其中前述 開口部的外形比第1連接端子還大,且前述開口部的間 距與第1連接端子的間距是相等的。 5. 如申請專利範圍第1項之積層用半導體模組,其中前述 開口部的平面形狀爲多角形狀或變形橢圓形,第1連接 端子的平面形狀爲圓形狀’前述開口部的外形比第1連 接端子的徑還大。 -21- 201042751 6 _如申請專利範圍第1項之積層用半導體模組,其中前述 開口部的平面形狀爲多角形狀或變形橢圓形,第1連接 端子的平面形狀爲圓形狀’前述開口部的外形比第1連 接端子的徑還大,且前述開口部的間距與第1連接端子 的間距是相等的。 7 .如申請專利範圍第1項之積層用半導體模組,其中前述 開口部的平面形狀爲多角形狀或變形橢圓形,第1連接 Q 端子的平面形狀爲圓形狀,前述開口部的外形比第1連 接端子的徑還大,且前述開口部的外形係相對於第1連 接端子的徑大1 5 A m以上。 8. —種積層型半導體模組,係在已將第1半導體晶片安裝 於一面之第1基板的前述一面上,積層已安裝第2半導 體晶片的第2基板,利用第2連接端子來連接第1基板 與第2基板之間以進行安裝, 將可與第2基板電性連接的墊設置在第1基板之前述 〇 —面的第1半導體晶片的保持區域外, 在以被覆一部分前述墊的方式形成在第1基板之前述 —面的絕緣膜上,形成以使前述墊露出的方式開口的開 口部, 前述開口部的平面形狀與第2連接端子的平面形狀、 及已形成在第1基板之另一面的第1連接端子的平面形 狀不同, 一端已連接至第2基板之第2連接端子的另一端熔 -22- 201042751 融、凝固,塡滿前述開口部而被接合至前述墊’在第1 連接端子及前述開口部的積層方向上進行透過檢查的狀 態下前述開口部的外形會從第2連接端子及第1連接端 子溢出。 9.如申請專利範圍第8項之積層型半導體模組’其中前述 開口部的高度爲前述第2連接端子的高度之一半以下。 1 〇,如申請專利範圍第8項之積層型半導體模組’其中前述 q 開口部的外形係比第2連接端子的徑大1 5 # m以上。 11.如申請專利範圍第8項之積層型半導體模組’其中前述 開口部的平面形狀與第2連接端子的平面形狀、及已形 成在第1基板之另一面的第1連接端子的平面形狀不同’ 一端已連接至第2基板之第2連接端子的另一端熔融、 凝固,塡滿前述開口部而被接合至前述墊’ 前述開口部的外形比第2連接端子及第1連接端子還 大。 Ο 1 2 .如申請專利範圍第8項之積層型半導體模組’其中前述 開口部的平面形狀與第2連接端子的平面形狀、及已形 成在第1基板之另一面的第1連接端子的平面形狀不同’ 一端已連接至第2基板之第2連接端子的另〜端熔 融、凝固,塡滿前述開口部而被接合至前述墊’ 前述開口部的外形比第2連接端子及第1連接端子還 大,且前述開口部的高度爲前述第2連接端子的高度之 —半以下。 -23- 201042751 13.如申請專利範圍第8項之積層型半導體模組’其中將前 述開口部的平面形狀形成爲多角形狀或變形橢圓形’ 一端已連接至第2基板之第2連接端子的另一端熔融、 凝固,塡滿前述開口部而被接合至則述塾’ 第2連接端子的平面形狀、及已形成在第1基板之另一 面的第1連接端子的平面形狀爲圓形狀,前述開口部的 外形比第2連接端子及第1連接端子的徑還大。 _ 14.如申請專利範圍第8項之積層型半導體模組’其中將前 〇 述開口部的平面形狀形成爲多角形狀或變形橢圓形’ 一端已連接至第2基板之第2連接端子的另一端熔融' 凝固,塡滿前述開口部而被接合至前述墊’ 第2連接端子的平面形狀、及已形成在第1基板之另一 面的第1連接端子的平面形狀爲圓形狀’ HU述開口部的 外形比第2連接端子及第1連接端子的徑還大’且 前述開口部的高度爲前述第2連接端子的高度之一半 〇 以下。 -24-201042751 VII. Patent application scope: 1. A semiconductor module for lamination is provided on the one surface of the first substrate on which the first semiconductor wafer has been mounted on one surface, and the first connection terminal is formed on the other surface. The pad electrically connected to the upper module is provided outside the holding region of the first semiconductor wafer, and is formed on the insulating film formed on the one surface of the first substrate so as to cover a part of the pad, so as to open the pad. In the opening portion of the opening portion, the planar shape of the opening is different from the planar shape of the first connecting terminal, and the outer shape of the opening is in the first state in the state in which the first connecting terminal and the opening are laminated. The connection terminal overflows. 2. The semiconductor module for a laminate according to the first aspect of the invention, wherein a pitch of the opening portion and a pitch of the first connection terminal are equal. 3. The semiconductor module for a laminate according to the first aspect of the invention, wherein the outer shape of the opening portion is larger than the first connection terminal. 4. The semiconductor module for a laminate according to the first aspect of the invention, wherein the outer shape of the opening is larger than the first connection terminal, and the pitch of the opening is equal to the pitch of the first connection terminal. 5. The semiconductor module for a laminate according to the first aspect of the invention, wherein the planar shape of the opening is a polygonal shape or a deformed elliptical shape, and a planar shape of the first connection terminal is a circular shape. The diameter of the connection terminal is also large. The semiconductor module for a laminate according to the first aspect of the invention, wherein the planar shape of the opening is a polygonal shape or a deformed elliptical shape, and the planar shape of the first connection terminal is a circular shape of the opening. The outer shape is larger than the diameter of the first connection terminal, and the pitch of the opening is equal to the pitch of the first connection terminal. The semiconductor module for a laminate according to the first aspect of the invention, wherein the planar shape of the opening is a polygonal shape or a deformed elliptical shape, and a planar shape of the first connection Q terminal is a circular shape, and an outer shape of the opening is larger than The diameter of the connection terminal is also large, and the outer shape of the opening is larger than the diameter of the first connection terminal by 15 A or more. 8. The laminated semiconductor module in which the first semiconductor wafer is mounted on one surface of the first substrate, and the second substrate on which the second semiconductor wafer is mounted is laminated, and the second connection terminal is connected to the second substrate. a substrate is mounted between the substrate and the second substrate, and a pad electrically connectable to the second substrate is disposed outside the holding region of the first semiconductor wafer of the first substrate, and a portion of the pad is covered. In the insulating film formed on the surface of the first substrate, an opening that opens to expose the pad is formed, and a planar shape of the opening and a planar shape of the second connection terminal and a first substrate are formed. On the other surface, the first connection terminal has a different planar shape, and the other end of the second connection terminal connected to the second substrate is melted and solidified, and the opening is joined to the pad. When the first connection terminal and the opening are in the inspection direction in the stacking direction, the outer shape of the opening overflows from the second connection terminal and the first connection terminal. 9. The laminated semiconductor module of claim 8, wherein the height of the opening is one-half or less of the height of the second connection terminal. In the laminated semiconductor module of the eighth aspect of the invention, the outer shape of the q-opening portion is larger than the diameter of the second connecting terminal by 15 5 m or more. 11. The laminated semiconductor module of claim 8, wherein the planar shape of the opening and the planar shape of the second connection terminal and the planar shape of the first connection terminal formed on the other surface of the first substrate. The other end of the second connection terminal that is connected to the second substrate at one end is melted and solidified, and is joined to the pad by the opening. The outer shape of the opening is larger than the second connection terminal and the first connection terminal. . The laminated semiconductor module of the eighth aspect of the invention, wherein the planar shape of the opening and the planar shape of the second connection terminal and the first connection terminal formed on the other surface of the first substrate are The other end of the second connection terminal connected to the second substrate is melted and solidified, and the opening is joined to the pad. The outer shape of the opening is smaller than the second connection terminal and the first connection. The terminal is also large, and the height of the opening is −half or less of the height of the second connection terminal. -23- 201042751 13. The laminated semiconductor module of claim 8, wherein the planar shape of the opening is formed into a polygonal shape or a deformed elliptical shape, and one end is connected to the second connection terminal of the second substrate. The other end is melted and solidified, and is joined to the opening, and the planar shape of the second connection terminal and the planar shape of the first connection terminal formed on the other surface of the first substrate are rounded. The outer shape of the opening is larger than the diameter of the second connection terminal and the first connection terminal. 14. The laminated semiconductor module of claim 8, wherein the planar shape of the opening is formed into a polygonal shape or a deformed elliptical shape, and one end is connected to the second connection terminal of the second substrate. One end is melted and solidified, and the planar shape of the second connection terminal that is joined to the pad by the opening is filled, and the planar shape of the first connection terminal formed on the other surface of the first substrate is a circular shape. The outer shape of the portion is larger than the diameter of the second connection terminal and the first connection terminal, and the height of the opening is one-half or less of the height of the second connection terminal. -twenty four-
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