TW200950010A - Universal substrate for semiconductor packages and the package - Google Patents

Abstract

Disclosed are a universal substrate for semiconductor packages and the package. The universal substrate comprises a substrate base, two sets of original fingers and one set of redistribution fingers on the substrate base, and a solder resist formed on the substrate base. The redistribution fingers are located between the two sets of original fingers. The solder resist has an opening from which the redistribution fingers are exposed. A plurality of exhaust grooves are formed on the solder resist without penetrating the solder resist. The exhaust grooves connect the opening and extend toward the sides of the substrate base but not connecting to other openings from which the original fingers are exposed so as to form air channels to exhaust outward during chip attaching. This solves the problems of bubbles remaining in the opening and chip-attaching adhesive contaminating the original fingers when a large size chip is disposed. In one embodiment, traces connecting the distribution fingers can cross to be overlapped with but not exposed from the exhaust grooves such that the disposition flexibility of the exhaust grooves is increased.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for a semiconductor device, and more particularly to a general-purpose substrate and a semiconductor package structure for a semiconductor package. [Prior Art] In a semiconductor device, for example, a ball grid array semiconductor package structure or a card type semiconductor package structure or the like, the substrate is used to carry the wafer φ and the fingers of the substrate are electrically connected to the pads of the wafer to achieve internal Electrical connection. For a specification, the size of the semiconductor package structure (specifically, the memory card) is not variable. In order to provide different memory capacities, at least one set of redistribution fingers can be added at different locations on the upper surface of the substrate to make the substrate versatile 'can be packaged for small-sized wafers' to reduce substrate manufacturing costs. However, when a large-sized wafer is bonded, the redistribution finger will not be used and covered by the adhesive, and it is easy to remain windy >/package' and the valley is prone to gas explosion (p〇pC〇rn). Referring to FIGS. 1A and 1B , a conventional semiconductor package structure includes a substrate 100 , a wafer ij , a die bond i 2 , a plurality of first bond wires 13 , and a plurality of second bond wires 14 . A gel 15 The substrate 100 mainly has a substrate body 11A and a solder resist layer 13A. The substrate body 110 has a surface m, and is provided with a plurality of first set of fingers 1 2 1 , a plurality of second set of fingers 22 and a plurality of third sets of fingers 123 ′ wherein the second set of fingers 122 and the third set of fingers 123 are generally fingers located on both sides of the surface 111, and are suitable for electrically connecting large-sized wafers. The first set of fingers 1 2 1 is located between the set of fingers 500122 and the third set of fingers 123 as a redistribution connection, and is suitable for electrically connecting small-sized wafers. The solder resist layer ι 3 is formed on the surface 111 and has a plurality of openings 131, 132, 133 to

The first group of fingers 121, the second group of fingers 122 and the third group of fingers 123 are respectively exposed. When the wafer n is a large-sized wafer, the "11" covers the first set of fingers i 2 i and is bonded to the substrate 100 by using the adhesive 12 to be disposed on the substrate 100. The first bonding wires 13 are electrically connected to the second group of fingers 122 of the substrate 100; the second bonding wires 14 are electrically connected to the second to the second substrate 100 The sealing body 15 is formed on the solder resist layer 130 of the substrate 100 to seal the wafer 11, the first bonding wires 13 and the second bonding wires 14. See Figure 1B. As shown, the adhesive 12 adheres to the back side of the solder resist layer 130 of the substrate 100 and the back surface of the wafer 11. The opening 131 of the solder resist layer 130 is closed and is closed. The wafer η is covered (as shown in FIG. 1 ), so that residual gas cannot be discharged outward from the opening (1) during the die bonding process, and bubbles may be present in the adhesive 12 (as shown in FIG. 1 ). This leads to the phenomenon of popcorn (popcorn) in the subsequent process or during use. In order to avoid the problem of bubble residue during the die bonding, A substrate in which the solder resist openings are interconnected is used as a wafer carrier. Another conventional semiconductor package structure has been proposed, which is disclosed in the Republic of China Patent No. 1281733 "Semiconductor Package and Substrate Structure", although it has been avoided. ^The effect of the residue of the package, but the adhesive will spread to the fingers on the sides of the 7 200950010 substrate, which is prone to sticking out of the glue and contaminating the fingers and the substrate line is exposed to cause the problem of being recorded. Another conventional semiconductor package 21, a die bond adhesive 22, and a plurality of structures shown in FIGS. 2A and 2B include a substrate 200, a wafer first bonding wire 23, a plurality of second bonding wires 24, and a Colloid 25. The substrate 200 mainly has a substrate body 21〇, a plurality of first-group fingers 22, a plurality of second group fingers 222, and a plurality of third group fingers.

And a solder mask layer 230. The first set of fingers 22, the second set of fingers 222 and the third set of fingers 223 are all disposed on a surface 211 of the substrate body. The first set of fingers 221 as the redistribution fingers are located between the second set of fingers 222 and the third set of fingers. The solder resist layer 230 is formed on the surface 21 and has a plurality of openings 231, 23 2 and 233 for respectively exposing the first set of fingers 221, the second set of fingers 222 and the third Group finger 223. The solder resist layer 230 further has a plurality of extension openings 235 extending outwardly from the central opening 23丄 and communicating to the peripheral opening 232 or 233. The bonding of the adhesive 22 is performed so that the wafer 21 is placed on the substrate 2. When the wafer 21 is a large-sized wafer, the wafer 21 covers the opening 23 1 and the first set of fingers 22 丨. The first bonding wires 23 are electrically connected to the second group of fingers 222 of the substrate 21 to the substrate 200. The first fresh wires 24 are electrically connected to the wafer 21 to the substrate 2 These second sets of fingers 223. The sealant 25 is formed on the solder resist layer 230 of the substrate 200 to seal the wafer 21, the first bonding wires 23 and the second fresh wires 24. Referring to Figures 2A and 2B, the adhesive 200950010 crystal glue 22 is filled into the opening 231 and the air bubbles remaining in the opening 231 are discharged by the extension openings (3). However, in the process of the die-bonding process, the adhesive glue 22 has fluidity under high temperature and pressure, and the adhesive glue 22 flows along the extended openings... The overflow glue 22 is further contaminated to the first set of fingers 222 and the third set of fingers 223 (as shown in g 2 Β), and even causes the first wire bond wires 23 or the second wire bond wires ^One end benefit 2 sticks to the second set of fingers 222 or the third set of fingers 223. ρ The first group of fingers 221, the second group of fingers 222 and the third group of fingers 223 are electrically connected to form an electric ore layer 28〇. In addition, the 'first set of fingers 221 have the effect of the index position re-matching'. The base 20 0 must further include a plurality of connections of the first-group fingers 221 and the second group of fingers. The line of 222 is 25 inches. Since the extension openings 235 extend through the anti-snagging layer 23, once the lines 250 are interlaced with the extensions σ 235, the lines are exposed, and the plating layer 28 is formed at the same time as the lines 25〇. Exposed section. In addition to the problem of electroplating waste, there is also a phenomenon of exhaust gas clogging, which causes the exhaust function of the extension openings 235 to fail. [Summary of the Invention]

In view of the above, the main object of the present invention is to provide a general-purpose substrate and a semiconductor package structure for a semiconductor package, which can provide a non-blocking and non-overflowing gas passage that is discharged outward during the die-bonding process to avoid bubble residue. The problem can effectively solve the problem of the overflow of glue in the traditional semiconductor package structure I. 200950010 The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. A general-purpose substrate for a semiconductor package according to the present invention comprises a substrate body, a plurality of first set of fingers, a plurality of second sets of fingers, a plurality of third sets of fingers, and a solder mask. The substrate system has a surface. The first set of fingers, the second set of fingers and the third set of finger joints are disposed on the surface of the substrate body. The first set of fingers are located between the second set of fingers and the third set of fingers. The solder resist layer is formed on the surface of the substrate body, the solder resist layer has a first opening, a second opening and a third opening to respectively expose the first set of fingers and the second The group finger refers to the third group. Wherein, the plurality of first exhaust slots are formed on one of the exposed surfaces of the solder resist layer but do not penetrate the solder resist layer, and the first exhaust slots are connected to the first opening and to the surface of the substrate body The side extends but does not communicate to the second opening and the third opening. The object of the present invention and solving the technical problems thereof can be further realized by the following techniques 措施 measures. In the above-mentioned general-purpose substrate, a plurality of wires may be further formed on the surface of the substrate body and connected to the first group of fingers and the second group of fingers, and the solder resist layer covers the same Some lines. In the above-mentioned general-purpose substrate, the first exhaust grooves and the line systems may be misaligned and do not overlap. In the above-mentioned general-purpose substrate, one of the first exhaust grooves may have a bottom surface not higher than the lines. In the above-mentioned general-purpose substrate, one of the first exhaust grooves may have a bottom surface 10 200950010 higher than the lines. In the above-mentioned general-purpose substrate, at least one of the first exhaust slots may be overlapped with at least one of the circuit lines without revealing the lines. In the above-mentioned general-purpose substrate, the extended ends of the first exhaust grooves may include a plurality of closed groove ends stopped in the solder resist layer. In the above-mentioned general-purpose substrate, at least one communication groove may be formed on the exposed surface of the solder resist layer and communicate with the first exhaust grooves to constitute a mesh-shaped channel. In the above-described general-purpose substrate, the extended ends of the adjacent first exhaust grooves may be interconnected in a u shape. In the above general-purpose substrate, the surface of the substrate body may have a first edge, a second edge, and a third edge, the second edge being parallel to the third edge, the first edge system Connecting the second edge and the third edge, wherein the second set of fingers are arranged on the second edge of the surface of the base body. The third set of fingers are arranged on the substrate body The third edge of the surface, the first set of fingers may be arranged in the center of the surface of the substrate body for the redistribution fingers of the second set of fingers. In the above general-purpose substrate, at least one second exhaust groove is connectable to the first opening and extends toward the first edge of the surface of the substrate body. In the above-mentioned general-purpose substrate, at least one third exhaust groove is connectable to the first opening and extends toward the edge of one of the surfaces of the substrate body, the fourth 11 200950010. In the above-mentioned general-purpose substrate, the second opening and the second portion may be adjacent to the periphery of the flute 4, the second edge and the third edge, respectively. In the above-mentioned universal type, the second opening and the ith may be respectively connected to the first edge and the third edge.

In the above-mentioned general-purpose substrate overflow storage tank, it is a connection end. The solder resist layer is formed in the above-described general-purpose substrate in such a manner that the first exhaust grooves are formed in the above-described manner. The first exhaust duct system

It is also revealed that the semiconductor package of the above-mentioned general-purpose substrate-based T-chip is deconstructed' mainly including the aforementioned Japanese-Japanese film, a viscous paste, a plurality of first bonding wires, and a re-bonding wire. The wafer is disposed on the universal substrate and covers the assembly fingers. The wafer has a plurality of first zinc pads and a plurality of pads. The adhesive is adhered to the back side of the wafer and the common solder resist layer, and the adhesive glue is further filled into the first opening and the T exhaust groove. The first bonding wires are electrically connected to the pads of the wafer to the second set of fingers of the universal substrate. The plurality of electrodes are electrically connected to the second pads of the wafer to the third type of fingers of the universal type. The present invention also discloses that the above-mentioned general-purpose substrate three-opening type L-opening type has a plurality of extensions which can be used for the large-scale type of the first type of the second type substrate. The welding of the substrate of the wire-bonding substrate 12 200950010 The second-inch chip of the semiconductor package structure of the two-inch wafer, mainly including the above-mentioned general-purpose base, a wafer, a die-bonding glue, a plurality of welding Line and a plurality of second weld lines. The wafer is disposed on the universal substrate and between the plurality of contacts and the third set of contacts, the wafer having a plurality of pads and a plurality of second pads. The adhesive is adhered to the back surface of the wafer and the solder resist layer of the universal substrate, and the adhesive is not filled in the first opening. The first bonding wires are electrically connected to the first pads of the wafer to the first group of fingers of the universal substrate. The second soldering pads are electrically connected to the second pads of the wafer to the third type of fingers of the universal substrate. It can be seen from the above technical solutions that the substrate for semiconductor package and the semiconductor package structure of the present invention have the following advantages and effects: The use of a general-purpose substrate on the surface of the die bond to form a vent groove that does not penetrate the solder resist layer can be During the die-bonding process, a channel for the gas to be discharged is provided to avoid the problem of residual bubbles. The venting groove on the surface of the solder resist layer can not reveal the line connecting the redistributing fingers (ie, the first group of fingers) to reduce the plating area to reduce the system. In addition, the line can be allowed to increase the distribution of the venting groove. 'And avoid the venting groove being blocked. The road is not overlapped with the exhaust groove and is elastic. By limiting the extended end of the venting groove to limit the area of the viscous gel

The w...π area and the feather F-meter L-slot are not connected to the periphery of the solder-proof layer' to avoid contamination of the large-size wafer due to the adhesion of the glue to the _-like finger (ie the second set of fingers and the third The assembly finger refers to 'effectively solve the problem of the conventional semiconductor package structure 13 200950010 in the process of the adhesive crystal. 4. By using the first set of fingers, the second set of fingers and the third set of fingers, the universal substrate can be applied to different sizes of U, u, and J to save the substrate. cost. 5. The first set of fingers and the second set of fingers are connected by a line system, so that the small-sized wafer can be directly connected to the general-purpose substrate by the first set of fingers.

Electrical interconnection, without the need to wire to the second set of fingers, thereby shortening the length of the fresh line. [Embodiment] According to a first embodiment of the present invention, a general-purpose substrate of a semiconductor package is illustrated in a schematic view of a surface of FIG. 3A, a schematic cross-sectional view of the same, and a perspective view of FIG. 3C. The invention includes a substrate body 31〇, a plurality of first set of fingers 321, a plurality of second sets of fingers 322, a plurality of third sets of fingers w and a solder mask layer 33〇. Referring to Figure 3A, the substrate body 3 has a surface 311' as a bearing surface on which the wafer is placed. The surface 3" can have a - edge, edge 312, a second edge 313, a third edge 314, and a fourth edge %. In this embodiment, the second edge 3 13 and the third edge 314 are parallel to each other, and the first edge 312 and the fourth edge 315 are parallel to each other, and the first edge 312 is connected to the second edge Edge 313 and the third edge 314. The fourth edge 3丨5 is also connected to the second edge 313 and the third edge 314. Referring to the 3A®, the first set of fingers 321, the second set of fingers 322 and the third set of fingers 323 are disposed on the surface of the substrate 14 200950010 body 310. However, it should be understood that the number of tailu groups is not exemplified by the three groups in the figure _ # Ί m Α 11 ‘, the electrical design of the actual substrate is increased by s or adjusted. The first η ^ η - μ ^ ^ and the buckle 3 21 are located between the second set of buckles 322 and the third set of connected embodiments, and the second sets are connected to each other. In the present, the ugly money 322 and the third system generally refer to the first group of fingers 321 , the temple is electrically connected to the 4b second group of fingers 3 22 heavy distribution fingers. One of the two first sets of fingers 排列 is arranged in the center of the surface 3 1 1 'the central & The second set of fingers 322 can be arranged on the second edge 313 of the surface 311 of the substrate body 31. The second set of fingers 323 are arbitrarily > β + arranged on the third edge 314 of the surface 311 of the substrate body 310. The first group of fingers 322 and the third group of fingers 322 may be an e bonding pad, the first group of fingers 321 , the first group of fingers 322 and The materials of the third set of fingers 323 may be copper. In this embodiment, the surface of the first set of fingers 321 , the second plate fingers 322 and the third set of fingers 323 may be plated with a plating layer 380 for adding semiconductor sealing products. In the middle of the electrical connection with the wire bonding force. The material of the electric ore layer 380 can be selected for use in silver, gold, tin, palladium, tin, lead and tin. Referring to FIGS. 3A, 3B, and 3C, the solder resist layer is formed on the surface 311 of the substrate body 310. The solder resist layer 33 has a first opening 331 to reveal the first surface. The contact pin 321 has a second opening 332 and a third opening 333 as shown in FIG. 3A to respectively expose the second set of fingers 322 and 15 200950010. The third opening 332 and the third opening 3 3 3 may be a closed opening or an open notch. In this embodiment, the second opening 3 3 2 and the third opening 3 3 3 The closed perimeter openings are respectively adjacent to the second edge 3 1 3 and the third edge 3 1 4. The solder resist layer 330 can be selected from a cover iayer or a solder mask layer (s〇ider) One of the masks may be formed by film pressing or printing and then developing by exposure to develop a pattern. 凊 Referring to Figures 3A and 3B, a plurality of first exhaust slots are shown. 340 is formed on one exposed surface 334 of the solder resist layer 330 but does not penetrate the solder resist layer 330, and the first exhaust slots 340 are connected to the first open And extending to the side of the surface 311 of the substrate body 310 (ie, the second edge 313 and the third edge 314) but not communicating to the second opening for exposing the second set of fingers 322 332 and the third opening 333 for revealing the second set of fingers 32; 3. Typically, but not limited to, the first exhaust slots 340 can be formed by laser to facilitate control The first exhaust groove 340 is formed so as not to penetrate the solder resist layer 330' to avoid exposing the lines 350. As shown in FIG. 3A, the first exhaust grooves 340 are not connected to the second opening 332. And the third opening 333' to prevent the adhesion of the adhesive to the second set of fingers 322 and the second set of fingers 3 2 3 . In the embodiment, the first exhaust slots 40 The length of the first exhaust groove 340 is connected to the longer side of the first opening 3 3 1 . The extended ends 341 of the first exhaust grooves 3 4 are beyond a large one. The coverage area of the size wafer 3〇, for the gas in the subsequent spotting process, the gas may be discharged from the first exhaust grooves 34 to the outside of the circle <0 200950010 without The plurality of extended ends 341 of the first exhaust grooves 340 may include a plurality of closed groove ends stopped in the solder resist layer 330 to limit the adhesion of the glue. In addition, the general-purpose substrate 300 may further include a plurality of wires 35 〇 formed on the surface 311 of the substrate substrate 310 and connected to the first group of fingers 321 and the second group of fingers 322 . The solder resist layer 33 further covers the lines 350. Therefore, the first group of fingers 321 can serve as the redistribution fingers of the plurality of fingers 322. As shown in FIG. 3B, the lines 305, 3, the first group of fingers 3 2 1 , the second group of fingers 3 2 2, and the second group of fingers 323 may be the same layer. Line layer. Therefore, in addition to the large-size wafer, the second type of fingers 322 can be electrically connected to the universal substrate 300, and the small-sized wafer can be directly realized by the first-group fingers 32 1 . The electrical interconnection of the substrate 3 can further shorten the length of the bonding wire, so the general-purpose substrate 3 can be applied to wafers of different sizes to save the manufacturing cost of the substrate. In addition, since the lines 350 are covered by the solder resist layer 330, the lines 35 are not exposed to the first exhaust grooves 34 and are not formed in the first exhaust grooves 340. The plating layer 38〇 not only reduces the plating area to reduce the cost, but also prevents the first exhaust grooves 34 from being blocked. As shown in FIG. 3A, in the embodiment, the first exhaust grooves 340 and the lines 35 may be misaligned and overlap, so that the formation depth of the first exhaust grooves 340 may be increased. These lines 350 are also not revealed. For example, as shown in Fig. 3B, one of the bottom surfaces 342 of the first exhaust grooves 34 may be no higher than the lines 35, so that the gas produced in the process of the die-bonding process can be discharged more smoothly. More specifically, at least one air channel 360 is connectable to the first opening 331 and extends toward the first edge 312 of the surface 311 of the substrate to increase the viscous venting effect. The second exhaust slot 360 is connected to the first opening 331 at a side of the first opening 331 adjacent to the first edge 312. The other end of the first exhaust slot 360 is connectable to the first 312. At least one second exhaust slot 370 is connectable to the first opening and extends toward the fourth edge 3 of the surface 311 of the substrate body 310. The above-mentioned general-purpose substrate 300 can be used to carry a large size and composed of a semiconductor package structure, such as a memory card, a ball grid array structure (BGA) or a planar array package structure (LGA). After a large size wafer, a schematic diagram of the surface of Figure 4A is illustrated. A semiconductor package structure including the general-purpose substrate 300-size wafer is exemplified in a 4B cross-sectional view. The semiconductor package structure is intended to include the above-described general-purpose type 300, the large-sized wafer 30, a die bond 41, a plurality of first portions 42, and a plurality of second bonding wires 43. The large-sized wafer 3 is mounted on the universal substrate 300, and has a large memory capacity. The large-sized wafer 30 has a plurality of sleeves and a double-tied first pad 31. And a plurality of pads 32, which may be formed on one of the large/eight-size wafers 30, and as the bulk of the large-sized wafers 3/(.), the external electrodes are placed on the general-purpose substrate after the die-bonding The large-sized wafer 30 of the trousers on the 300 is covered by two rows: a shorter edge of 310. The extended wafer is sealed with a substrate bonding wire of the type shown in the first and larger drawings. The second contact 33 is provided with the first set of fingers 321 and the first opening 331. The first pads 31 are adjacent to the second set of fingers 322, and the second pads 32 The extension ends 314 of the first venting grooves 340 extend beyond the large-sized wafer 30. Generally, the material of the adhesive 4 1 is Epoxy resin or other adhesive material that can flow under heating is used. The setting of the large-size wafer 30 is made by bonding the adhesive glue 4 1 The back surface 34 of one of the wafers 30 and the solder resist layer 300 of the general-purpose substrate 300 ^, and the adhesive glue 4 1 is further filled into the first opening 33 1 and the first exhaust grooves 340 The first bonding wires 42 are electrically connected to the first pads 31 of the large-sized wafers 30 to the second groups of fingers 322 of the universal substrate 300. The second bonding wire 43 is electrically connected to the second pads 32 of the large-sized wafer 30 to the third group of fingers 323 of the universal substrate 300. As shown in FIG. 4B, the semiconductor package structure An adhesive φ body 44 may be further formed on the general-purpose substrate 300 to seal the large-sized wafer 30, the first bonding wires 42 and the second bonding wires 43, wherein the bonding adhesive 4 1 is filled in a partial area of the first exhaust groove 340 under the large-sized wafer 30, and the sealant 44 is filled in the remaining area of the first exhaust grooves 340. In the die-bonding process, the large The size wafer 30 is pressed down to the general-purpose substrate 300 to press the viscous gel 4 1 which is not cured and has fluidity, and the gas may be directed to the first exhaust grooves 340 Discharging to prevent air bubbles from remaining in the first opening 313, and filling the first venting grooves 340 by filling the adhesive 19 1 into the first venting groove 340 to increase the adhesion of the universal substrate 3 The extension ends 341 of the first exhaust grooves 340 can block the flow of the adhesive 41 to the second opening 332 and the third opening 333, so that the second set of fingers 322 can be avoided. The third set of fingers 323 are contaminated by the glue of the adhesive 41. The aforementioned general-purpose substrate 300 can be used to carry small-sized wafers and be composed into a semiconductor package structure. The general-purpose substrate 3 is exemplified in the surface of Fig. 5A after the e-small-scale wafer is disposed. A semiconductor package structure including the general-purpose substrate 300 and a small-sized wafer is exemplified in a cross-sectional view taken in Fig. 5B. The semiconductor package structure mainly comprises the above-mentioned general plastic substrate 30 〇, a small-sized wafer 5 〇, a viscous gel 6 J, a plurality of first bonding wires 6 2 and a plurality of second bonding wires 63. The small-sized wafer 5 is disposed on the general-purpose plastic substrate 300 and has a small memory capacity of about half the size of the aforementioned large-sized wafer 30. The small-sized wafer 5 is located between the first set of fingers 3 2 1 and the third set of fingers 3 2 3 'The small-sized wafer 50 has a plurality of first pads 51 and a plurality of The second pad 52 is formed on one of the active surfaces 53 of the small-sized wafer 5 . After the die bonding, the small-sized wafers 50 disposed on the general-purpose substrate 3 不 do not cover the first set of fingers 3 2 丨 and the first openings 331 ′ the first pads 51 Adjacent to the first set of fingers 321 , the second pads 52 are adjacent to the third set of fingers 323 . Referring to FIG. 5B, the adhesive layer 61 is adhered to the back surface 54 of the small-sized wafer 50 and the solder resist layer 20 of the general-purpose substrate 3 200950010 330. The first opening 331 is filled in. The first bonding wires 62 are electrically connected to the first soldering potentials 51 of the small-sized wafers 5 to the first group of fingers 321 of the universal substrate 300. The second bonding wires 63 are electrically connected to the second bonding pads 52 of the small-sized wafer 50 to the third group of fingers 323 of the universal substrate 300. As shown in FIG. 5B, a glue 64 is formed on the universal substrate 300 to seal the small-sized wafer 50, the first bonding wires 62, and the first first wires 63'. 61 is filled in a partial area of the first venting groove 340 under the small-sized wafer 50, and the sealing body 64 is filled in the remaining area of the first venting grooves 340, and the sealing body 64 is further filled in the The first opening 331. As shown in Fig. 5B, preferably, the semiconductor package structure may further comprise a dummy wafer 70 having a size substantially equal to the size of the small-sized wafer. The dummy wafer 70 is disposed on the universal substrate 3A and located between the first set of fingers 321 and the second set of fingers 322 to achieve mold flow balance during the sealing process. According to a second embodiment of the present invention, a general-purpose substrate of another semiconductor package is illustrated in a schematic view of the surface of the substrate in FIG. 6 and a schematic cross-sectional view of FIG. 6B. The basic structure of the general-purpose substrate 4 is the same as that of the first embodiment, and the same components are denoted by the same reference numerals and will not be described again. The main component of the universal substrate 4 is the substrate body 3 1 , the first set of fingers 3 2 1 , the second set of fingers 3 2 2, and the third set of fingers ^ 9 ^

_ 323 and the solder resist layer 33 0. Referring to FIG. 6B, the 4b 篦 纽 杜 — 321 321 321 is located between the second set of fingers 21 200950010 322 and the third set of fingers 323. The first opening 331 of the solder resist layer 33 exposes the first set of fingers 321 . The solder resist layer further has a second opening 332 and a third opening 333 for respectively exposing the second set of fingers 322 and the third set of fingers 323. In this embodiment, the second opening 332 and the third opening 333 are respectively connected to the open peripheral notches of the second edge 313 and the third edge 314. As in the first embodiment, the first exhaust slots 34 are formed on the exposed surface 334 of the solder resist layer 330 but do not penetrate the solder resist layer 330. The first exhaust slots 34 are connected. The first opening 3 3 延伸 extends to the side of the surface 311 of the substrate body 310 (ie, the second edge 313 and the third edge 314 ) but does not communicate with the second opening 332 and the third opening 333 . As shown in FIG. 6A, at least one communication groove 49 can be formed on the exposed surface 334 of the anti-snagging layer 330 and communicates with the first exhaust grooves 340' to form a mesh channel, so that the exhaust can be exhausted. . Φ, as shown in FIG. 6B, the circuit 350 is further formed on the surface 311 of the substrate body 31 and connects the first set of fingers 321 and the second set of fingers. 322, the solder resist layer 330 further covers the lines 350. In this embodiment, one of the bottom surfaces 442 of the first exhaust slots 340 can be higher than the lines 350. Therefore, at least one of the first exhaust slots 340 can be interlaced with at least one of the lines 35 and the lines 35 are not exposed, and the configuration flexibility of the first exhaust slots 340 can be increased. . In this embodiment, at least one of the first exhaust slots 340 may be completely overlapped on a line 35〇200950010. In accordance with a third embodiment of the present invention, another semiconductor packaged universal substrate is illustrated in the schematic view of the substrate surface of Figure 7. The basic structure of the general-purpose substrate 500 is substantially the same as that of the first embodiment, and the same components are denoted by the same reference numerals and will not be described again. The main components of the universal base plate 500 are the substrate body 31, the first set of fingers 321, the second set of fingers 322, the third set of fingers, and the solder resist layer 3 3 0 . The first opening 3 3 i of the solder resist layer 3 3 exposes the first set of fingers 321 , and the second opening 332 of the solder resist layer 33 exposes the second set of fingers 322 . The second opening 333 of the solder resist layer 33 exposes the third set of fingers 323. Similarly, the first exhaust slots 340 are formed on the exposed surface of the solder resist layer 33 but do not penetrate the solder resist layer 310, and the first exhaust slots 34 are connected to the first opening 33. 1 and extending to the side of the surface 3 of the substrate body 3 (ie, the second edge 313 and the third edge 314) but not to the second opening 332 and the third opening 333. In this embodiment, the extended ends 541 of the adjacent first exhaust slots 340 are interconnected in a u-shape to form an overflow return passage. As shown in Fig. 7, the common substrate 5 is further covered by the solder resist layer 33. In this embodiment, a first exhaust slot 34 may partially overlap the lines 350. As shown in FIG. 8 , in a variation of the first embodiment, the solder resist layer 330 further has a plurality of overflow storage tanks 335 , which are connected to the first exhaust slots 340 . Some extension ends 341. The overflow reservoirs 23 200950010 reservoirs 335 may extend through the solder mask layer 33 or the overfill reservoirs 335 may not extend through the solder mask layer 33. The shape of the overflow knee storage tank 335 may be circular or rectangular. In a specific embodiment, the overflow storage tanks 335 can be dummy openings extending through the solder resist layer 330. In the process of the viscous crystal, even if the overflowing glue exceeds the range in which the extending ends 341 can be blocked, the overflowing range can be prevented from continuing to expand by the overflow storage tanks 335. In addition, the present invention is applicable to a general package substrate, wherein the solder resist φ layer has both a central opening and a peripheral opening, and the central opening is completely formed in the wafer covering area, and a plurality of vent grooves formed in the solder resist layer are not used. Through the solder resist layer and connecting the central opening and extending to the side of the surface of the substrate body but not communicating to the peripheral opening, the problem of accumulation of bubbles and adhesive glue overflowing into the peripheral opening in the central opening can be solved. The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make some modifications or modifications to the equivalent embodiment by using the technical content disclosed above. However, without departing from the technical solution of the present invention, the above embodiments are made according to the technical essence of the present invention. Any simple modifications, equivalent changes and modifications are still within the scope of the technical solutions of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A and FIG. 1B are schematic diagrams showing the surface of a substrate and a cross-sectional view of a substrate in a perspective view of a semiconductor package structure. 24 200950010 Figures 2A and 2B: Schematic and cross-sectional views of a substrate surface of another conventional semiconductor package structure. 3A, 3B, and 3C are schematic, cross-sectional, and perspective views of a general-purpose substrate of a semiconductor package in accordance with a first embodiment of the present invention. Fig. 4A is a schematic view showing the surface of a general-purpose substrate of a semiconductor package in accordance with a first embodiment of the present invention after a large-sized wafer is disposed. Fig. 4B is a schematic cross-sectional view showing a semiconductor package structure including a general-purpose substrate and a large-sized wafer in accordance with a first embodiment of the present invention. Fig. 5A is a view showing the surface of a general-purpose substrate of a semiconductor package in accordance with a first embodiment of the present invention after a small-sized wafer and a dummy wafer are disposed. Fig. 5B is a schematic cross-sectional view showing a semiconductor package structure including a substrate for a φ, a small-sized wafer, and a dummy wafer in accordance with a first embodiment of the present invention. 6A and 6B are schematic cross-sectional views and cross-sectional views showing a general-purpose substrate of a semiconductor package in accordance with a second embodiment of the present invention. Figure 7 is a schematic view showing the surface of a general-purpose substrate of another semiconductor package in accordance with a third embodiment of the present invention. Figure 8 is a schematic view showing the surface of a general-purpose substrate of another semiconductor package in accordance with a fourth embodiment of the present invention. 25 200950010 [Main component symbol description]

11 wafer 12 adhesive 12A 13 first bonding wire 14 second bonding wire 15 21 wafer 22 adhesive bonding 22A 23 first bonding wire 24 second bonding wire 25 30 large size wafer 3 1 first bonding pad 32 33 active surface 34 Back 41 Adhesive 42 First wire 43 44 Seal 50 Small size wafer 51 First pad 52 53 Active side 54 Back 61 Adhesive 62 First wire 63 64 Encapsulant 70 Virtual wafer 100 Substrate 110 Substrate Body 111 surface 121 first set of fingers 122 second set of fingers 123 130 solder resist layer 131 opening 132 133 opening 200 substrate 210 substrate body 211 surface 221 first set of fingers 222 second set of fingers 223 230 solder mask 231 Opening 232 233 opening 235 extension opening 250 line 280 plating layer third group finger opening third group finger opening bubble sealing body overflow rubber sealing body second bonding pad second bonding wire second bonding pad second bonding wire 26 200950010 300 Universal substrate 310 substrate body 311 surface 312 first edge 313 second edge 3 14 third edge 315 fourth edge 321 first set of fingers 322 second set of fingers 323 third Contact 330 solder resist layer 331 first opening 332 second opening 333 third opening 334 exposed surface 335 overflow storage tank 340 first exhaust slot 341 extended end 342 bottom surface 350 line 360 second exhaust slot 370 third exhaust Slot 380 Plating layer 400 Universal substrate 442 Bottom surface 490 Connecting groove 500 Universal substrate 541 Extended end reference 27

Claims (1)

200950010 X. Patent Application Range: 1. A general-purpose substrate for a semiconductor package, comprising: a substrate body having a surface; a plurality of first-group fingers disposed on the surface of the substrate body; The plurality of fingers are disposed on the surface of the substrate body, and the plurality of second fingers are disposed on the surface of the substrate body, wherein the first group of fingers are located in the second group of fingers Between the third group of _ fingers; and a tamper-proof layer formed on the surface of the substrate body, the solder resist layer has a first opening, a second opening and a third opening to respectively reveal The first set of fingers, the second set of fingers and the third set of fingers; wherein the plurality of first exhaust slots are formed on one of the solder resist layers exposed surface but not through the solder resist And a first exhaust groove connecting the first opening and extending to a side of the surface of the substrate body but not communicating to the first opening and the third opening. 2. The general-purpose substrate of the semiconductor package of claim 1, further comprising a plurality of lines formed on the surface of the substrate body and connecting the first set of fingers and the second In the group, the solder mask further covers the lines. 3. The general-purpose substrate of the semiconductor package of claim 2, wherein the first exhaust grooves and the circuit lines are misaligned and do not overlap. 4. The general-purpose substrate of the semiconductor package of claim 3, wherein one of the first exhaust grooves has a bottom surface not higher than the lines. 5. The general-purpose base of the semiconductor package of claim 2, wherein the bottom surface of one of the first venting grooves is higher than the lines. 6. The universal package of the semiconductor package of claim 5, wherein at least one of the first exhaust slots overlaps at least one of the lines but does not reveal the lines. 7. The general-purpose substrate of the semiconductor package of claim i, wherein the extension ends of the first venting grooves comprise a plurality of closed groove ends stopped in the anti-tank layer. ❹ 8. The general-purpose substrate of the semiconductor device according to item 1 of the scope of the invention, wherein the v-connecting groove is formed on the exposed surface of the solder resist layer and communicates with the first exhaust grooves to form a mesh aisle. 9. The general-purpose substrate of the semiconductor package of claim 4, wherein the extended ends of the adjacent first exhaust grooves are interconnected in a u-shape. 10. The general-purpose substrate of the semiconductor package of claim 2, wherein the surface of the substrate body has a first edge, a second edge, and a third edge, the second edge Parallel to the third edge system, the first edge is connected to the second edge and the third edge, wherein the second set of fingers are arranged on the second edge of the surface of the substrate body, The third set of fingers are arranged on the second edge of the surface of the substrate body, and the first set of fingers are arranged on the substrate body by the redistribution fingers of the second set of fingers The center of the surface. 11. The universal package of the semiconductor package of claim 10, wherein at least one second venting groove is coupled to the first opening and extends toward the first edge of the surface of the substrate body. 12. The general-purpose base 29 200950010 board of the semiconductor package of claim 11, wherein at least one third exhaust slot is connected to the first opening and to the fourth surface of the substrate body. The edge extends. 13. The general-purpose substrate of the semiconductor package of claim 1, wherein the second opening and the third opening are closed peripheral openings adjacent to the second edge and the third edge, respectively. 14. The general-purpose substrate of the semiconductor package of claim 1, wherein the second opening and the third opening are open perimeter notches respectively communicating to the first edge and the third edge. The general-purpose substrate of the semiconductor package of claim 1, wherein the anti-corrosion layer further comprises a plurality of overflow storage tanks connected to the extension ends of the first exhaust grooves. The general-purpose substrate of the semiconductor package of claim 1, wherein the first exhaust grooves are formed in a laser manner. A semiconductor package structure comprising the general-purpose substrate of the semiconductor package according to claim 1, wherein the semiconductor package structure further comprises: a wafer disposed on the general-purpose substrate and covering the plurality of a set of the cymbal system 'having a plurality of first fresh sorghum and a plurality of second fresh sputum; a viscous glue solder resist layer, a gas groove; affixing the wafer to the back surface and the universal substrate The viscous gel is further filled into the first opening and the first plurality of first bonding wires, and the plurality of second bonding wires of the universal substrate are electrically connected to the first of the wafers a second set of fingers; and electrically connecting the second pads of the wafer to the third set of fingers of the universal substrate of 30 200950010. 18. The semiconductor package structure of claim 17, wherein the extended ends of the first exhaust slots extend beyond the wafer. 19. The semiconductor package structure of claim 17, further comprising a gel formed on the universal substrate to seal the wafer, the first bonding wires and the second bonding wires. Wherein the adhesive glue is filled in a partial area of the first exhaust groove under the wafer, and the sealant is filled into the remaining area of the first exhaust grooves. The semiconductor package structure of claim 17, wherein the general-purpose substrate further comprises a plurality of wires formed on the surface of the substrate body and connecting the first set of fingers and the first The two sets of fingers, the solder mask further covers the lines. A semiconductor package structure comprising the general-purpose substrate of the semiconductor package according to claim i, wherein the semiconductor package structure further comprises: a wafer is disposed on the general-purpose substrate and located at the first Between the assembly and the third set of fingers, the wafer has a plurality of first pads and a plurality of second pads; the adhesive is attached to the back surface of the wafer and the universal substrate The anti-knowledge layer 'the adhesive layer is not filled in the first opening; the plurality of first bonding wires are electrically connected to the first pads of the wafer to the first groups of the universal substrate And a plurality of second bonding wires ' electrically connecting the second pads of the wafer to the third group of fingers of the universal substrate. 31 200950010 22 23 24 containing (4) the half (four) package structure described in item 21, another package piece, m? system formed on the stomach common 35 substrate to seal the crystal into the line and the first: the welding wire 'where the adhesive crystal is filled The groove is in a partial area under the wafer, and the sealant is filled in the remaining area of the first ranking tow groove, and the sealant is further filled in the R3 τ-» ^2, claim 2, claim 22 The semiconductor package structure is further disposed on the universal 33 substrate and located between the first set of fingers and the second set of fingers. The semiconductor package structure of claim 21, wherein the general-purpose substrate further comprises a plurality of wires formed on the surface of the substrate body and connecting the first set of fingers and the second groups The solder mask further covers the lines. 25. A substrate comprising: a substrate body having a surface; a plurality of fingers disposed on the surface of the substrate body; and a solder resist layer formed on the surface of the substrate body, the solder resist layer having a central opening and at least one peripheral opening to expose the plurality of contacts The plurality of exhaust slots are formed on one of the exposed surfaces of the solder resist layer but do not penetrate the solder resist layer, and the exhaust slots are connected to the central opening and to the side of the surface of the substrate body Extending but not communicating to the peripheral opening. The substrate of claim 25, wherein the extension ends of the venting grooves comprise a plurality of closed groove ends that are stopped in the solder resist layer. 32 200950010 27. The substrate of claim 25, wherein at least - connected to the exposed surface of the anti-tank layer and communicates with the venting grooves to form a mesh channel. The substrate of claim 25, wherein the extended ends of the adjacent first venting grooves are U-shaped. The substrate of claim 4, wherein the solder resist layer further comprises a plurality of overflow storage tanks connected to the extension ends of the first exhaust slots. , 33