TW200939447A - Semiconductor package and multi-chip package using the same - Google Patents

Semiconductor package and multi-chip package using the same Download PDF

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Publication number
TW200939447A
TW200939447A TW097133795A TW97133795A TW200939447A TW 200939447 A TW200939447 A TW 200939447A TW 097133795 A TW097133795 A TW 097133795A TW 97133795 A TW97133795 A TW 97133795A TW 200939447 A TW200939447 A TW 200939447A
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TW
Taiwan
Prior art keywords
layer
redistribution
semiconductor wafer
wafer
lead
Prior art date
Application number
TW097133795A
Other languages
English (en)
Inventor
Myeong-Soon Park
Hyun-Soo Chung
Seok-Ho Kim
Ki-Hyuk Kim
Chang-Woo Shin
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Samsung Electronics Co Ltd
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Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of TW200939447A publication Critical patent/TW200939447A/zh

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Description

c 200939447 九、發明說明： 【發明所屬之技術領域】 本發明的一般概念是關於半導體封裝，以及使用該半 導體封裝的多晶片封裝。 【先前技術】 如今，電子工業的目標是以低成本高可靠性來製造备 種輕、緊湊、快速、多功能且高度有效的半導體產品。實
現此複雜目標的重要方法之一是半導體封裝總成 (assembly)技術。 確切而言，為了提供具有高容量的半導體封裝，已斫 ，出隹半導體晶片的多晶片封裝。所述多晶片封裝的容 篁可根據相對於相同封裝面積的半導體晶片數目而容易地 提高。 然而’在將引線基板及半導體晶片與結合線及凸塊一 ，使用的夕晶片封裝的情況下，必須在所堆疊之半導體晶 一之，，入—插入晶片。當插入一插入晶片時，可堆疊於 -個多晶片封|中之半導體晶 片的數目受限’且整個引線 曰加’因此在封&設計方 。 【發明内容】 本發明的-~ 理以便應用於多 本發明的― 晶片封裝。 般概念是提供一種在晶圓級被作為封裝處 晶片封裴的半導體晶片。 般概念亦提供一種使用該半導體封裴的多 將在以下明中部分地闡述本發㈣-般概念之其他 6 200939447 態樣及用途，且本發明的一般概念之其他態樣及用途將藉 由所述說明而部分地顯而易見’或者可藉由實踐一般發明 概念而得知。 Ο
藉由以下方式來實現本發明的一般概念之前述及/或 其它態樣及用途：提供半導體封裝’該半導體封裝包含半 導體晶片，所述半導體晶片包含形成於包含積體電路之基 板上的晶片概塾，及使所述晶片概塾暴露的純化層。在所 述半導體封裝中，連接至晶片襯墊且在半導體晶片上延伸 的第一重新分佈引線層包含用於線結合的線結合襯墊以及 用於將第一重新分佈引線層連接至第二半導體晶片的第一 焊料襯墊。 在所述半導體封裝中，位於第一重新分佈引線層上的 連接至第一重新分佈引線層上的第二重新分佈引線層包含 第二焊料襯墊，所述第二焊料襯墊用以將第二重新分佈引 線層連接至第三半導體晶片。 可在鈍化層與第-重新分佈5丨線層之間形成重新分佈 緣層’所述賴分心丨輕緣層包含使⑼襯藝暴 重新分佈引線的.部分。可進—步在第一重新 形成使一引線接合襯墊及第-焊料襯墊暴露 f 一 € < i Μ + Μ P #弟二重新分佈引線層上形成使 弟一谇枓襯墊暴露的上部絕緣 第二重新分佈引線層可由你;弟二刀：弓:娜 或周邊部分中形成晶片轉4成。可在基板的中央部分 半V體封4可包3半導體晶片，所述半導體晶片包含 7 200939447 形成於包含積體電路的基板上的晶片襯墊，及使晶片襯墊 暴露的純化層。第一重新分佈引線層連接至所述晶片襯 塾’且在半導體晶片上延伸。 Ο
在第一重新分佈引線層上形成下部絕緣層，且所述下 部絕緣層包含多個使第一重新分佈引線層的一部分暴露的 第一開口部分。第二重新分佈引線層連接至第一重新分佈 引線層，且形成於下部絕緣層上。上部絕緣層形成於第二 重新分佈引線層上，且包含多個使第二重新分佈引線層的 一部分暴露的第二開口部分。 穿過第一開口部分而暴露的第一重新分佈引線層可包 含用於線結合的線結合襯墊及將第一重新分佈引線層連接 至第二半導體晶片的第一焊料襯墊。線結合襯墊可在半導 體晶片的周邊部分中形成，且第—焊料娜可在較該線結 合襯墊更靠近中央的部分中形成。 穿過第二開口部分而暴露的第二重新分佈引線層可以 是將第二f新分佈引線層連接至第三半導體晶片的第二焊 央 二，襯墊的形成位置可較該第-焊料襯塾更 罪近料體㈤片的周邊部分，峨該線結合婦更靠近中 亦可藉由提供包含引線基板之多晶 明一般概念之前述及/吱i它能庐 /笊Λ現本毛 夕车導r曰二 用途。附接至引線基板 片襯 之+¥體4包含軸於包含積 轨，凫梓晶κ鈿舳爸奋.......之·&板上的 8 200939447 c 第一焊料襯墊。結合線連接第一重新分佈引線層之線結合 襯墊及引線基板之引線襯墊。 位於第一重新分佈引線層上方且連接至第一重新分佈 引線層的第二重新分佈引線層具有第二焊料襯墊。設置於 半導體晶片上方之第二半導體晶片經由第一凸塊(bump)而 連接至半導體晶片，所述第一凸塊設置於對應於第一重新 分佈引線層之第一焊料襯墊的位置。 設置於第二半導體晶片上方之第三半導體晶片經由第 ❹二凸塊而連接至第二半導體晶片，所述第二凸塊設置於對 應於第二重新分佈引線層之第二焊料襯墊的位置。用密封 劑密封（或囊封）半導體晶片、重新分佈引線層及結合線。 可進一步在鈍化層與第一重新分佈引線層之間形成重 新分佈引線絕緣層，所述重新分佈引線絕緣層包括使晶片 襯墊暴露以用於重新分佈引線的開口部分。可進一步在第 一重新分佈引線層上形成下部絕緣層，所述下部絕緣層使 線結合襯墊及第一焊料襯墊暴露。 ❹ 可在第二重新分佈引線層上形成上部絕緣層，所述上 部絕緣層使第二焊料襯墊暴露。第二半導體晶片及第三半 導體晶片之尺寸可不同於半導體晶片之尺寸。 亦可藉由提供包含引線基板之多晶片封裝來實現本發 明般概念之前述及/或其它態樣及用途。半導體晶片包含 至引線基板且包含積體電路的晶片襯墊及使晶片襯墊 ^路之鈍化層。連接至晶片襯墊之第一重新分佈引線層在 …導體曰g片上延伸。在第一重新分佈引線層上形成的下部 9 200939447 〇 絕緣層在多個第一開口部分中形成線結合襯墊及第〆焊料 襯墊，所述第一開口部分使第一重新分佈引線層的，部分 暴露。 在下部絕緣層上形成連接至第一重新分佈引線層的第 二重新分佈引線層。在第二重新分佈引線層上形成的上 絕緣層在多個開口部分中形成第二焊料襯墊，所述開口部 分使第二重新分佈引線層的一部分暴露。結合線連接該線 結合襯塾及引線基板的引線襯墊。 〇 形成於半導體晶片上方之第二半導體晶片經由第一凸 塊而連接至半導體晶片，所述第一凸塊設置於對應於第一 焊料襯墊的位置。設置於第二半導體晶片上方之第彡半導 體晶片經由第二凸塊而連接至第二半導體晶片，所述第二 凸塊設置於對應於第二焊料襯墊的位置。用密封劍密封半 導體晶片、重新分佈引線層及該結合線。 線結合觀塾可位於半導體晶片之周邊部分中，立第一 焊料襯墊較該線結合襯墊更靠近半導體晶片中的中央位 〇 置。晶片襯墊可形成於基板的中央部分或周邊部分中。此 半導體晶片之尺寸可大於第二半導體晶片及第三半導體晶 片的尺寸，且第二半導體晶片之尺寸小於第三半導體晶片 之尺寸。 一 亦可藉由提供半導體封裝來實現本發明一般概念之前 述及/或其它態樣及用途，所述半導體封骏包含：半導體晶 片’所述半導體晶片包含形成於包含積體電路之基板上= 晶片襯墊以及使所述晶片襯墊暴露的鈍化層；第一重新分 10 200939447 佈引線層，其連接至晶片襯墊且設置於半導體晶片上方， 所述第一重新分佈引線層包含上方之暴露部分，用以提供 對第一重新分佈引線層的線結合，且連接至位於第一重新 分佈引線層上方的第二半導體晶片；以及第二重新分佈引 線層，其設置於第一重新分佈引線層上方並連接至第一重 新分佈引線層，且包含上方之暴露部分，用以提供對第二 重新分佈引線層的線結合，且連接至位於第二晶片上 第三半導體晶η。 。
所述第 重新分佈引線層及第二重新分佈引線層 露部分可包含線結合襯墊及焊料襯墊。 【實施方式】 =發明一般概念之半導_是指無需切鑛製程 即可在Ba ®峰vd)被處理為封餘型的半導 ⑽之半導體封裝，可同時在晶圓級處理i 干體^，且因此可減少製造成本。此外，由於 =晶片之表面_等於半導體縣之表面 體封裝可更加緊密。 、斤牛^ 根據本發明-般概念之半導體封 成^晶圓級時在半導體晶片中形成 線層t形成具有第二焊料概塾的第二二：:伟?丨 因此，由於根據本發明—般概念之_ =人 個或兩個以上的重新分佈引線層，在杂現二：， 裝時改良半導體晶片的設計靈活性。確切現 200939447 Ο 根，本發明-般概念之半導體针上堆疊半導體晶片而實 ^晶片封裝時，可減小多晶片封裝之總厚度，且可以多 =封裝巾之半$體晶片之間的最小距離來實現電性連 因此’可在—個多晶片封襄中堆疊更多個半導體晶片。 所述半導體晶片封裝可包含兩個或兩個以上的重新分 =引線層’但此處為了方便解釋，將描述兩個重新分佈弓！ 線^。又，根據本發明-般概念之多晶片封裝是藉由堆疊 二!體:曰:片！異質料體晶片而構成。此外，由於根 :又概念之多晶片封裳可實現各種功能，所以其 ^(system in package) ° " 現在將參照附圖更全面來描述根據各實施例之本發明 j I又概心，附圖中I會示例示性實施例。然而，本發明可 實施成許多不同形式，且不應理解為限於本文中闡述的實 ^例，實情為’之所以提供此等實施例，是為了令本揭露 二徹底j a整亚將本㈣之概念全面傳達給熟習此項技術 。在祝明書各處’相同參考標號代表相同元件。 圖1為根據本發明—般概念之實施例而配置半導體封 裝的晶圓W的平面圖； "羊”’田而5 ’已經歷諸如用以形成積體電路之預定製程 ，重新S佈引線形成製程的封裝製造製程的晶圓w包含 二個未之半導體封裳⑽’即晶圓級封裝。藉由使 W中之半導體封裝⑽個體化，完成 一種早70半導體封裳。 圖2至圖6為說明根據本發明―般概念之實施例的半 12 200939447 導體封裝及半導體封裝製造方法的橫截面圖。 了方=====執行，且此處為 =_，=;根：發:= ，…、圖2’槌供+導體晶片110,其 路之基板101，例如矽美柘.帮忐仇* Λ 匕3積篮尾 ^ 1ΛΟ ”㈣純’喊於純101上之晶片襯 ❹
塾103 ;以及使晶片襯墊103暴露之鈍化層1〇5。晶片概塾 103、可形成於基板101之中央部分中，或者若有必要，可 形成於基板101之周邊部分中。可在鈍化層1〇5上形成重 新分佈引線絕緣層106，其包含使晶片襯墊1〇3暴露的開 口部分。重新分佈引線絕緣層106形成於鈍化層1〇5與^ 稍後形成之第一重新分佈引線層之間。然而，本發明二妒 概念不限於此，且可不形成重新分佈引線絕緣層1〇6。又 圖3中省略了重新分佈引線絕緣層1〇6。在鈍化層 上形成第一重新分佈引線層121，其連接至晶片襯塾1〇3 且在半導體晶片110上延伸。第一重新分佈引線層ΐ2ι用 作線結合用的線結合襯墊。又，第一重新分佈引線層l2i 用作連接第二半導體晶片用的第一焊料襯墊。由於第〜重 新分佈引線層121應用作線結合及焊料襯墊’所以其是使 用電鍍方法而用金層形成的。 參照圖4，在第一重新分佈引線層121上形成具有多 個第一開口部分125a、125b及125c的下部絕緣層ι23， 戶斤述第一開口部分使第一重新分佈引線層121的一部分暴 13 200939447 露。穿過第一開口部分125a及125b而暴露之第一重新分 佈引線層121包含提供線結合用的線結合襯墊127a以及稍 後連接第二半導體晶片用的第一焊料襯墊127b。 ❹
穿過第一開口部分125c而暴露的第一重新分佈引線 層121是待連接至第二重新分佈引線層的連接部分。在半 導體晶片110之周邊部分中形成線結合襯墊127a，且第_ 焊料襯墊127b較該線結合襯墊i27a更靠近半導體晶片 no上的中央。因此，第一重新分佈引線層121及下部絕 緣層123構成第一重新分佈引線級13〇。 參照圖5，在下部絕緣層123上形成第二重新分佈引 線層131 ’其連接至第一重新分佈引線層121。第二重新分 佈引線層131亦用作連接第三半導體晶片用的第二焊料襯 墊。由於第二重新分佈引線層131必須用作焊料襯墊，所 以其可使用電鐘方法用金層形成。 ,參照圖6,使用光蝕刻製程在第二重新分佈引線層131 上开>成上部絕緣層133，其具有多個第二開口部分135a， 所述第二開口部分使第二重新分佈引線層131之一部分暴 露。穿過第二開口料135“暴露之第二重新分佈引線層 131包含第二焊料襯墊137a，用以稍後將第二重新分佈引 線層131連接至第二半導體晶片。第二焊料襯塾 第-焊料襯塾127b更靠近半導體晶片11〇 ^邊部= 較該線結合襯墊127a更靠近中央。因此，第二重新分佈引 線層131及上部絕緣層133構成第三重新分佈引線級14〇。 再次參照圖6’將描述根據本實施例之半導體封裝 14 ❹ ❹ 200939447 Η °如圖6中所說明，半導體封裝100包含半導體晶 ⑻.η所述半導體^ UG包含：包含積體電路之基板 ΪΓη、於基板101上之晶片襯墊103 ;以及使晶片襯墊 川j泰路之純化層1〇5。 置ϋίίί體封裝_中，形成第—重新分佈引線層⑵， 入^曰曰片襯墊1〇3且在半導體晶片11〇上延伸，並且 合用的線結合襯墊i27a及將第-重新分佈 此外曰车道接至第二半導體晶片的第一焊料襯塾127b。 =連in100包含第二重新分佈引線層⑶，其 引靜佈引線層121且位於第一重新分佈 接ί; ϋ方’並且包含將第二重新分佈引線層131連 妾第二+導體晶片用的第二焊料襯塾137a。 個或^重::工^體和⑻可包含兩 半導體封裝UK)來實現多晶:，13;改 1〇〇之設計靈活性。_，導體騎 ΨΊ -7*b 1 m 导^ 封裝 l 00 中’繁—、度 枓襯墊I27b及第二烊料禰熱 丫弟知 上之第二半導體晶片及第三半導堆疊於其 提高第二半導體晶片及第三半導體；::=生因而 此外，當使用堆叠有第二半導二二十二舌， 片之半導體封裝_來實❹Βθ ^^衫三半導體晶 晶片’且因此可減小多晶曰:严，’無需任何插人 裝中之半導體晶片之間的最小距45現=晶片封 此可在一個多晶片封農中堆疊更多的半導::;ϊ接，且因 15 200939447 下文中，將描述使用根據本發明一般概念之實施例之 半導體封裝100的多晶片封裝。 圖7為說明根據本發明一般概念之實施例的多晶片封 裝400的橫截面圖；且圖8為說明圖7之多晶片封裝4〇〇 之概塾佈局的平面圖。 詳細而言，圖7及圖8為描述多晶片封裝400的示意 說明。首先，如圖7中所說明，多晶片封裝4〇〇包含引線 基板 301 ’ 例如，印刷電路板（printe(j circuit b〇ar(j，pcb )， 〇 其包含外部連接端子303，且上述半導體封裝100使用黏 合劑（未圖示）附接至引線基板301。半導體封裝1〇〇包 含第一重新分佈引線層121，其包含結合線127&及第一焊 料襯墊127b，如上所述。第一重新分佈引線層121之線結 合襯塾127a及引線基板301之引線襯墊（未圖示）經由結 合線309而連接。 第二半導體晶片311設置於半導體晶片11〇上方，且 經由第一焊料概塾127b及第一凸塊305而連接至半導體晶 ❹ 片110。第二半導體晶片311可以是與半導體晶片u〇相 同或不同類型之晶片。將第二半導體晶片311之尺寸設定 成不同於半導體晶片110之尺寸。 根據本實施例’第二半導體晶片311之尺寸即寬度 W2小於半導體封裝1〇〇之尺寸即寬度wi。又，將第一凸 塊305之高度設定成高於上部絕緣層133之表面。提供第 二半導體晶片311，其具有第一凸塊305，第—凸塊3〇5 設置成對應於第一焊料襯墊127b並根據第—焊料概塾 16 200939447 127b之位置而使用倒裝晶片（flip chip)製程來堆疊。根據半 導體晶片110之第一焊料襯墊127b而提前設計第一凸塊 305。 又’半導體封裝100包含第二重新分佈引線層131， 其包含第二焊料襯墊137a，如上所述。第三半導體晶片313 設置於第二半導體晶片311上方，並經由第二重新分佈引 線層131之第二焊料襯墊137a及第二凸塊307而連接至第 二半導體晶片311。第三半導體晶片313可以是與半導體 © 晶片110及第二半導體晶片31]相同或不同的類型。將第 三半導體晶片313之尺寸設定成與半導體晶片110及第二 半導體晶片311不同。 根據本實施例，第三半導體晶片313之尺寸即寬度 W3小於半導體封裝100之尺寸即寬度W1，且大於第二半 導體晶片311之寬度W2。又，第二凸塊307之高度大於 第二半導體晶片311之高度。提供第三半導體晶片313, 其具有第二凸塊307，第二凸塊307設置成對應於第二焊 0 料襯塾137a，且根據第二焊料襯墊137a的位置而使用倒 裝晶片製程來堆疊。根據半導體晶片110之第二焊料襯墊 137a而提前設計第二凸塊307。 使用密封劑315來密封（或囊封）半導體晶片11〇、 311、313、重新分佈引線層121及131以及結合線309， 因而完成多晶片封裝400。根據本實施例’半導體晶片 之尺寸即寬度W1最大，而第二半導體晶片311之尺寸即 寬度W2小於第三半導體晶片313之尺寸即寬度W3。然 17 200939447 而，可根據重新分佈引線層121或131之焊料概塾㈣ 或137a或者晶片襯塾103之位置來不同地設定第 晶片311或第三半導體晶片313的尺寸。 如上所述，根據本實施例之多晶片封裝4 〇 〇是藉由在 半導體封裝1〇〇中堆叠多個半導體晶片川及313而形 成所述半^體封裝1 00包含兩個或兩個以上的重新分佈 引線層121及131。因此，由於無需插入晶片，且可以多 曰曰片封裝中之半導體晶片之間的最小距離來實現電性連 接，所以可減小根據本實施例之整個多晶片封裝4〇〇的高 度hi，因而在一個多晶片封裝中堆疊更多的半導體晶片。 接下來，將參照圖8來描述多晶片封裝4〇〇的襯墊佈 局。 如圖8中所說明，在半導體晶片11〇之中央部分中設 置晶片襯墊103。晶片襯墊103經由第一重新分佈引線層 121而連接至線結合襯墊i27a。連接至晶片襯墊之線 結合襯墊127a亦經由結合線309而連接至引線基板（圖7 ❹ 中之301)。 在半導體晶片11〇上方堆疊尺寸小於半導體晶片n〇 之第二半導體晶片311。亦即，在半導體晶片110上方堆 $包含於半導體晶片110面積内之第二半導體晶片311。 第二半導體晶片311經由第一焊料襯墊127b及第一重新分 佈引線層121而連接至線結合襯墊127a。經由第一重新分 佈引線層121連接至第二半導體晶片311之線結合襯墊 127a經由結合線309連接至引線基板（圖7中之301)。 18 200939447 在第二半導體晶片311上方堆疊尺寸大於第二半導體 晶片311之第三半導體晶片313。亦即，堆疊第三半導體 晶片以覆蓋第二半導體晶片311。第三半導體晶片313經 由第二焊料襯墊137a及第二重新分佈引線層131而連接至 線結合襯塾127a。連接至第三半導體晶片313及第二重新 分佈引線層131之線結合襯墊127a經由結合線309而連接 至引線基板（圖7中之301)。圖8之襯墊佈局僅為一實例， 其它各種佈局亦有可能。 ® 圖9為根據本發明一般概念之另一實施例之多晶片封 裝400的橫截面圖。 詳細而言’圖9中說明的多晶片封裝400類似於圖8 中之多晶片封裝，區別僅在於晶片襯墊1〇3並非形成於半 導體晶片110之中央部分中，而是形成於其周邊部分中。 如圖9中所說明，可用類似於圖8中之多晶片封裝的方式 來形成多晶片封裝400，即使當晶片襯墊1〇3設置於半導 體晶片110之周邊部分中時亦如此。 G 圖10為將與圖7及圖9中說明之多晶片封裝比較之多 晶片封裝之實例的橫截面圖。 詳細而言’圖1〇中與圖7、圖8及圖9中的參考標號 完全相同的參考標號代表相同元件。半導體晶片110附接 至引線基板301。半導體晶片110之晶片襯墊103使用結 s線309而連接至引線基板。藉由插入黏合層，將 第一插入晶片352附接至半導體晶片11〇。第一插入晶片 352亦使用結合線3〇9而連接至引線基板。 19 200939447 具有第-凸塊354之第-半導體晶片311附接至 插入晶片352。第二插入晶# 356附接至第_ 311。第二插人晶片356亦使用結合線.而連接至引=某 板。具有第二凸塊358之第二半導體晶片313附接至第二 插入晶片356。當使用密封劑36〇而將半導體晶片ιι〇、^ 二半導體晶片311及第三半導體晶片犯以及第一插入晶 片352及第二插人晶片356密封時，多晶片封裝即已完成。 纟於對於圖1〇之多晶片封半導體晶片是使用插入 aBB片加以堆疊，所以圖Η)之多晶片封裝之厚度h2大於圖 7及圖9之多晶片封裝的厚度。因此，由於圖1〇之多晶片 封裝之引線長度與圖8及圖9之引線長度相比更有可能切 割各結合線，所以對於可在一個多晶片封裝内堆疊之半導 體晶片之數目存在著限制。 下文中，將描述使用根據本發明之本實施例之多晶片 封裝400的各種應用實例。 圖11為使用根據本實施例之多晶片封裝400的卡700 ❹ 的示意圖。 詳細而言’可將根據本實施例之多晶片封裝4〇0應用 於卡700。卡700之實例包含多媒體卡（muitimedja car(j， MMC)、安全數位卡（secure digital card，SD)等。卡 700 包含控制器710及記憶體720。記憶體720之實例包含快 閃δ己’fe'體、相變隨機存取記憶體裝置（phase-change random access memory device，pram)、隨機存取記憶體（random access memory ’ RAM)或其他類型之非揮發性記憶體。將 20 200939447 c 控制信號自控制器710傳輸至記憶體72〇，且在控制器71〇 與記憶體720之間傳輸資料或接收資料。 抑此處，將多晶片封裝400 (圖7及圖9中）用作控制 斋710及記憶體720，二者構成根據圖u之本實施例的卡 700。在此情況下，卡700可提高記憶體容量，且包含具有 各種功能之控制器710。又，由於卡7〇〇包含不包含插入 晶片之多晶片封裝400，所以卡700之厚度可減小，且引 線長度亦可減小，因而防止可能因切割一結合線而導致的 ❹ 可靠性降低。 圖12為使用根據本實施例之多晶片封裝4〇〇的封裝模 組500的示意圖。 、 詳細而言，可將根據本實施例之多晶片封裝4〇〇應用 於封裝模組500。在封裝模組5〇〇中，多個多晶片封裝4⑼ 附接至模組基板410。方型扁平形封裝（quad flat package， QFP)類型之封裝400附接至封裝模組5〇〇的一側，且外 部連接端子設置於封裝模組5〇〇的另一侧。根據本發明， 〇 本實施例之多晶片封裝400不限於圖12,且亦可應用於其 它各種模組。 圖13為使用根據本實施例之多晶片封裝的電子系 統800的示意圖。 ,、 詳細而言，電子系統800之實例包含電腦、行動電話、 mpeg-1 音訊層 3 (mpeg-1 audio layer 3，MP3)播放哭、 導航儀等。電子系統800包含處理器810、記憶體82〇以 及輸入/輸出裝置830。使用一通訊通道84〇而在處理器81〇 21 c 200939447 與記憶體820或輸入/輸出裝置830之間傳輸或接收一控制 信號或資料。 在此電子系統800中’將多晶片封裝400實施為處理 器810及記憶體820。因此，電子系統800由於不包含插 入晶片的多晶片封裝400而具有更高的可靠性。因此，根 據本實施例之電子系統800的可靠性提高。
在根據本發明一般概念之各種實施例之半導體封裝 中，在晶圓級時在半導體晶片上形成具有線結合及第一焊 料襯塾的第-重新分佈引線層’且在第—重新分佈引線層 上形成具有第二焊料襯墊的第二重新分佈引線層。因此， 由於在根據本發明-般概念之半導體縣中形成兩個或兩 :=的重新分佈引線層，所以可改良半導體晶片之設計 之半導二:：…料兩個以上的重新分佈引線層 =導體封裝中堆疊半導體⑼而實現多日日日片_時，益 而WfTv晶片’且因此可減小多晶^ 以半導體封裝中之半導體％ 衮之厚度’且可 性)連接，這樣4 = =小距離來實現(電 晶片。 L “封料堆疊更多的半導體 示及ίί本發明—般概念之例示性實施例來特定絡 可在不偏離以下申請糾錢所』此倾*者將瞭解， 精神及範疇的情況下作出形發明-般概念之 【圖式簡單說明】㈣各義Λ及細㈣改變。 22 200939447 附圖般概念之以上及其它雜及用途將藉由參照 圖、彳不性實施例之詳細描述而變得更容易明白。 && s1為根據本發明一般概念之實施例而配置半導體封 裝的晶®的平_。 等輯 導辦，2至圖6為說明根據本發明一般概念之實施例的半 封|及半導體縣製造方法的減面圖。 ❹ 胜7為5兒明根據本發明一般概念之實施例的多晶片封 哀的杈戴面圖。 =8為s兒明圖7之多晶片封袭之襯墊佈局的平面圖。 姑9為根據本發明一般概念之另一實施例之多晶片封 裝的板戴面圖。 曰，10為將與圖7及圖9中說明之多晶片封裝比較之多 日日片封骏之實例的橫戴面圖。 圖11為使用根據本發明一般概念之實施例之多晶片 封裝的卡的示意圖。 圖為使用根據本發明一般概念之實施例之多晶片 © 封I的封裝模組的示意圖。 圖丨3為使用根據本發明一般概念之實施例之多晶片 封裝的電子系統的示意圖。 【主要元件符號說明】 1GG :半導體封裝 1G1 ·基板 103 ·晶片概塾 105 :鈍化層 23 200939447 106 :重新分佈引線絕緣層 110 :半導體晶片 121 :第一重新分佈引線層 123 :下部絕緣層 125a、125b、125c :第一開 口部分 127a :線結合襯墊 127b :第一焊料襯墊 130 :第一重新分佈引線級
131 :第二重新分佈引線層 133 :上部絕緣層 135a :第二開口部分 137a :第二焊料襯墊 140 :第三重新分佈引線級 301 :引線基板 303 :外部連接端子 305 ··第一凸塊 307 :第二凸塊 309 :結合線 311 :第二半導體晶片 313 :第三半導體晶片 315 :密封劑 350 :黏合層 352 :第一插入晶片 356 :第二插入晶片 24 200939447 :第二凸塊 :密封劑 模組基板 :多晶片封裝 :封裝模組 :卡 ❹ :控制器 :記憶體 :電子系統 :處理器 :記憶體 :輸入/輸出裝置 :通訊通道 高度 厚度 晶圓 、W2、W3 :寬度 25

Claims (1)

  1. 200939447 十、申請專利範圍： 1.—種半導體封裝，包括. 半導體晶片’包含：形成於包含積體電路的基板上的 晶片襯墊，及使所述晶片襯墊暴露的鈍化層； 第一重新分佈引線層，其連接至所述晶片襯塾且在所 述半導體晶片上延伸’並包含用於提供線結合的線結合襯 墊以及用於將所述第一重新分佈引線層連接至第-二 晶㈣第-焊料襯塾；以及 第一+導體
    第二重新分佈引線層，其連接至所述第一重新分佈引 線層上的所述第—重新分佈引線層，並包含用以將所述第 二重新分佈弓丨線層連接至第三半導體晶片的第二焊料襯 2.如申凊專利範圍第1項所述之半導體封裝，更包括. ㈣ΙΓί佈引線絕緣層，其包含使所述晶片襯塾暴露以 权/、斤刀佈引線的開口部分，且在所述鈍化層盘所述t 一重新分⑹丨線層之間形成。 I、所述第 3·=申請專利範圍第1項所述之半導體封裝，其中更 ί戶重新分佈引線層上形成使所述引線接合襯墊及 所处弟焊料襯墊暴露的下部絕緣層。 4’.如〃申凊專利範圍第1項所述之半導體封裝，其中更 在所述第二重新分佈引線層上形成使所述第 ς 露的上部絕緣層。 吁丁寸规螯暴 、、α 5·如申請專利範圍第1項所述之半導體封褒，其中所 述第一重新分佈引線層及所述第二重新分佈弓ί線層由金層 26 200939447 形成。 6·如申請專利範圍第丨項所述之半導體封I， 述晶片襯墊在所述基板的中央部分或周邊部分中斤 7. —種半導體封裝，包括： 成。 半導體晶片，其包含：形成於包含積體 的晶片襯墊，及使所述晶片襯墊暴露的鈍❹路的基板上 Ο
    所述=:=，其連接至所述心墊，且在 下部絕緣層，其形成於所述第一重新分佈引線層上， ㈣第一重新分佈引線層的各別部分暴露的 第二重新分佈引線層，其連接至所述第一重新分佈引 線層，且形成於所述下部絕緣層上；以及 上部絕緣層，其形成於所述第二重新分佈引線層上， 且包含多個使所述第二重新分佈引線層的各別部分暴露的 第二開口部分。 8. 如申請專纖㈣丨項所述之半導體封裝，其中所 述f過所述第-開π部分而暴露的第—重新分佈引線層包 含提供線結合的線結合襯墊以及將所述第一重新分佈引線 層連接至第二半導體晶片的第一焊料襯墊。 '' 9. 如申請專利範圍第8項所述之半導體封裝，其中所 述線結合襯墊在所述半導體晶片的周邊部分中形成，且所 述第一焊料襯墊在較所述線結合襯墊更靠近中央的部分中 形成。 27 200939447 ι〇.如申請專利範圍第8項所述之半導體封裝，豆 述第二開口部分而暴露的第二重新分佈引線層是 將所述第二重新分佈引線層連接至所述第三半導體晶 弟^一焊料觀塾。 ' i1.如申請專利範圍第ίο項所述之半導體封裝，其中 所述第二烊料襯墊的形成位置較所述第一焊料襯墊更靠近 • 所述半導體晶片的所述周邊部分，而較所述線結合概塾更 靠近令央。 ❹ 12.-種多晶>{封裝，包括： 引線基板； 半導體晶片，其附接至所述引線基板，且包含：形成 於包含積體電路的基板上之晶片襯塾，及使所述晶片觀塾 暴露的鈍化層； 一第一重新分佈引線層，其連接至所述晶月襯墊且在所 述半導體晶片上延伸，並包含線結合襯墊及第一焊料襯塾； 結合線’其連接所述第一重新分佈引線層之所述線結 φ 合襯墊及所述引線基板之所述引線襯墊； 第二重新分佈引線層’其連接至所述第一重新分佈引 線層上方的所述第一重新分佈引線層，並具有第二焊料襯 墊； 第一半導體晶片，其設置於所述半導體晶片上方，且 經由第一凸塊而連接至所述半導體晶片，所述第一凸塊設 置於對應於所述第一重新分佈引線層之所述第一焊料襯墊 的位置； 28 200939447 第三半導體晶片，其设置於所述弟一半導體晶片上 方，且經由第二凸塊而速换至所述第二半導體晶片，所述 第二凸塊設置於對應於所述第二重新分佈引線層之所述第 二焊料襯墊的位置；以及 密封劑，其密封所述半導體晶片、所述重新分佈引線 層及所述結合線。
    i J .如T晴寻利章巳圍弗U項所迷之夕晶片封裝，其中 重新分佈引線絕緣層進一步形成於所述純化層與所述第一 重新分佈引線層之間，所述重新分佈引線絕緣層包括使所 述晶片襯墊暴露以提供重新分佈引線的開口部分。 下部第12項所述之多晶片封裝，其中 述下部絕緣層使所述tit所第—重新分佈引線層上，所 霧。 4、、·°合襯墊及所述第一焊料襯墊暴 15. 如申請專利範園 上部絕緣層形成於所逑 12項所述之多晶片封裝，其中 ，絕緣層使所述第二痒艇、〜重新分佈引線層上’所述上部 16. 如申請專利範塾暴露。 戶斤述第二半導體晶片及〃 12項所述之多晶片封裝，其中 半導體晶片之尺寸。第二半導體晶片之尺寸不同於所述 Π·—種多晶片封舉， 引線基板； 、包括： 半導體晶片1 . 基板且包含積體電路..晶片襯墊’其附接至所述引線 及趣化層’其使所述晶片襯塾暴露； 29 200939447 + ±第^重新分佈引線層，其連接至所述晶片襯墊且在所 述半導體晶片上延伸； 杜尸 ^ ”緣層，其形成於所述第-重新分佈引線層上’ 且在多個第-開口部分中形成線結合襯墊及第一焊料概 塾’所迭多個第—開口部分使所述第-重新分佈引線層的 一部分暴露； 第二重新分佈引線層，其連接至所述第一重新分佈引 0 線層且形成於所述下部絕緣層上； 上部絕緣層，其形成於所述 第二重新分佈引線層上， 且在多個開口部分中形成第二焊料襯墊，所述多個開口部 分使所述第二重新分佈引線層的一部分暴露； 結合線’其連接所述線結合襯墊及所述引線基板之引 線襯墊； 第二半導體晶片，其形成於所述半導體晶片上方，且 經由第一凸塊而連接至所述半導體晶片，所述第一凸塊設 置於對應於所述第一焊料襯墊之位置； © 第三半導體晶片，其設置於所述第二半導體晶片上方 且經由第二凸塊而連接至所述第二半導體晶片，所述第二 凸塊設置於對應於所述第二焊料襯墊之位置；以及 密封劑，其密封所述半導體晶片、所述重新分佈引線 層及所述結合線。 18.如申請專利範圍第π項所述之多晶片封裝，其中 所述線結合襯墊位在所述半導體晶片的周邊部分中，且所 述第一焊料襯墊在較所述線結合襯墊更靠近所述半導體晶 30 200939447 片中之中央的部分。 19. 如申請專利範圍第17項所述之多晶片封裝，其中 所述晶片襯墊形成於所述基板之中央部分中或周邊部分 中。 20. 如申請專利範圍第17項所述之多晶片封裳，其中 所述半導體晶片之尺寸大於所述第二半導體晶片及第三半 導體晶片的尺寸，且所述第二半導體晶片之尺寸小於所述 第三半導體晶片之尺寸。 © 21. —種半導體封裝，包括： 半導體晶片，其包含形成於包含積體電路的基板上的 晶片襯墊，以及使所述晶片襯墊暴露的鈍化層； 第一重新分佈引線層，其連接至所述晶片襯墊且設置 於所述半導體晶片上方，所述第一重新分佈引線層包含上 方之暴露部分，用以提供對所述第一重新分佈引線層的線 結合’且連接至位於所述第一重新分佈引線層上方的第二 半導體晶片；以及 第一重新分佈引線層，其設置於所述第一重新分佈引 線層上方並連接至所述第一重新分佈引線層，且包含上方 之暴露部分，用以提供對所述第二重新分佈引線層的線結 合，且連接至位於所述第二半導體晶片上方的第三半導體 晶片。 如申請專利範圍第21項所述之半導體封裝，其中 所述=一重新分佈引線層及第二重新分佈引線層的所述暴 霧部分包含線結合襯墊及焊料襯墊。 31
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