TW200939439A - Lead frame and manufacturing method of circuit device using the lead frame - Google Patents
Lead frame and manufacturing method of circuit device using the lead frame Download PDFInfo
- Publication number
- TW200939439A TW200939439A TW097146558A TW97146558A TW200939439A TW 200939439 A TW200939439 A TW 200939439A TW 097146558 A TW097146558 A TW 097146558A TW 97146558 A TW97146558 A TW 97146558A TW 200939439 A TW200939439 A TW 200939439A
- Authority
- TW
- Taiwan
- Prior art keywords
- lead frame
- support portion
- hole
- lead
- frame
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008025930A JP5144294B2 (ja) | 2008-02-06 | 2008-02-06 | リードフレームおよびそれを用いた回路装置の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
TW200939439A true TW200939439A (en) | 2009-09-16 |
Family
ID=41071116
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW097146558A TW200939439A (en) | 2008-02-06 | 2008-12-01 | Lead frame and manufacturing method of circuit device using the lead frame |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP5144294B2 (ja) |
KR (1) | KR20090086148A (ja) |
TW (1) | TW200939439A (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI800266B (zh) * | 2021-05-31 | 2023-04-21 | 日商Towa股份有限公司 | 成型模、樹脂成型裝置及樹脂成型品的製造方法 |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5215980B2 (ja) * | 2009-10-30 | 2013-06-19 | 株式会社三井ハイテック | 半導体装置の製造方法 |
JP5397195B2 (ja) * | 2009-12-02 | 2014-01-22 | 日立化成株式会社 | 光半導体素子搭載用基板の製造方法、及び、光半導体装置の製造方法 |
JP5613463B2 (ja) * | 2010-06-03 | 2014-10-22 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
DE102015100025A1 (de) | 2015-01-05 | 2016-07-07 | Osram Opto Semiconductors Gmbh | Leiterrahmen |
JP6924411B2 (ja) * | 2017-08-28 | 2021-08-25 | 大日本印刷株式会社 | リードフレームおよび半導体装置の製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001077235A (ja) * | 1999-09-06 | 2001-03-23 | Mitsui High Tec Inc | 半導体素子搭載用基板 |
JP3634757B2 (ja) * | 2001-02-02 | 2005-03-30 | 株式会社三井ハイテック | リードフレーム |
JP3628971B2 (ja) * | 2001-02-15 | 2005-03-16 | 松下電器産業株式会社 | リードフレーム及びそれを用いた樹脂封止型半導体装置の製造方法 |
JP2007294715A (ja) * | 2006-04-26 | 2007-11-08 | Renesas Technology Corp | 半導体装置の製造方法 |
-
2008
- 2008-02-06 JP JP2008025930A patent/JP5144294B2/ja active Active
- 2008-12-01 TW TW097146558A patent/TW200939439A/zh unknown
- 2008-12-15 KR KR1020080127219A patent/KR20090086148A/ko active Search and Examination
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI800266B (zh) * | 2021-05-31 | 2023-04-21 | 日商Towa股份有限公司 | 成型模、樹脂成型裝置及樹脂成型品的製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20090086148A (ko) | 2009-08-11 |
JP5144294B2 (ja) | 2013-02-13 |
JP2009188150A (ja) | 2009-08-20 |
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