TW200931526A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
TW200931526A
TW200931526A TW097132539A TW97132539A TW200931526A TW 200931526 A TW200931526 A TW 200931526A TW 097132539 A TW097132539 A TW 097132539A TW 97132539 A TW97132539 A TW 97132539A TW 200931526 A TW200931526 A TW 200931526A
Authority
TW
Taiwan
Prior art keywords
layer
conductive layer
insulating layer
manufacturing
semiconductor device
Prior art date
Application number
TW097132539A
Other languages
English (en)
Other versions
TWI366875B (en
Inventor
Tetsuya Nishizuka
Masahiko Takahashi
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of TW200931526A publication Critical patent/TW200931526A/zh
Application granted granted Critical
Publication of TWI366875B publication Critical patent/TWI366875B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

200931526 九、發明說明： 【發明所屬之技術領域】 本發明係關於半導體裝置之製造，b ^ 電衆進行_處理之步驟之轉體裝置之製關於包3藉由 【先前技術】 垆二積，路，LargeScaleInte_edcircuit)等之半導 3 ί 基板上交互堆疊絕緣層及導電層-^ ❹ 。：、以亥，處理對藉由CVD (化學氣相沉積，❿ t〇sltlQn)處理等而形成於半導縣板上之層進行_化以堆ΡΓ 各曰 '又’#刻處理中係利用平行平板或Icp (感應輕合電衆宜 ycUvdy- coupled Plasma )、ECR (電子迴旋加速器共振， ectron Cyclotron Resoannce)等以各種裝置產生之電聚。 近年來，自高密集化等觀點而言，包含M〇s (金氧^ =etal 〇xlde Sem—tor)電晶體等半導體元件之半導 =要求為3維構造。在此簡單説明關於3維構造M〇s電晶^之 構成。 圖12及圖13係顯示包含3維構造M〇s電晶體之半 之巴卜觀立體圖。圖I2顯示將後述導電層應侧前之狀態^ 顯不將導電層109蝕刻後之狀態。參照圖12及圖13即去Γ，丰導 體裝置101包含自半導體基板（晶圓）1〇2之主表面1〇3朝垂直方 向延=而形成之導電性之複數突條部1〇4。突條部1〇4係朝圖12 中以箭頭χπ表示之方向延伸之形狀。沿各突條部1〇4之縱長方 向，在圖13所示之狀態下於包夾導電層1〇9之位置，分' 源極區域及汲極區域。 j化成有 此半導體基板102上，形成有Si〇2膜所構成之絕緣層1〇5。 且在位於源極區域及没極區域之間之通道區域上形成有薄的si〇2 膜1〇6所構成之閘極氧化膜，俾使其包覆突條部1〇4。在此，關^ 構成閘極氧化膜之Si〇2膜1〇6，因其包覆突條部104而形成，故 200931526 ίϊ条部舰之頂面1G7與面應之間具有堆疊方向之高的高度 為光罩進行圖岽針對 夕導電層109，以光阻110 之既定區域。^餘之導電里去除導電層109 搬上形成3維構造2=„气。如此’在半導體基板 產生钱刻殘餘物L之M0S電明體。此時，於突條部刚之側部 ❹ ❹ 處理時，如曰晶石夕導電層109進行钱刻 ICP等電聚處侧處理係在例如上述 或ci2中添加有^匕=。就侧乳體而言，-般使用於HBr 钱刻處理與處^號$報中’針對多祕導電層，係以主 面積比與選擇 圖二係：餘刻 ，因：=:下層===_ _面 多晶石夕面積&之S 〇2之面積S3之和而言， 為舰刻而露出之12所示之狀態下，_面積比僅 為100。且在隨1，露出之Si〇2之面積s3為〇，故 狀態下，麵刻面積ΐ ϋ侧之多晶石夕消失’所有Si02露出之 铜速率為1時，斜ί曰。又，所謂選擇比’係相對於Si〇A 圖14中，^十對多晶石夕之姓刻速率比。 正確性等觀點而兮s:3未露出之圖12所示之狀態下，自確保形狀 欲餘刻之部分“ °以低選擇比進行主侧處理嘴侧進展， 圖13所示，於突^二小，Si〇2露出之面積S3增大。其結果，如 蝕刻殘餘物U1 ==4之^留下姓刻殘餘物⑴。在此，將 X處理時’會活化因⑽處理產生之SiBr等反 200931526 應產物，此反應產物會降低選擇比。若 ，理’露出之面積增多之薄的Si 4 部1〇4之頂面107之薄的Si〇2膜應即 Him突條 損傷之虞。因此，如圖14所干，、祕到攻擊’有 在^以上之高選擇比進_刻“ /j處理中，需以例如選擇比 _處理述在不同之條件下進行 裝置。 驟數之增加而無法有效率地製造半導體 ❹ 【發明内容】 ίίϊϋ的在於：提供—種可適紅有效率製造 裝置之製造方法 之半導體 依本發明之半導财置製造方法，包含下列步 驟 緣=====層’該突出狀形態之絕 形成導電層俾使包覆觀出狀形態之絕緣層； 及 ❹ 之件下。對該半導體基板施加7_咖2 蝕列ίί 使用以微波為電聚源之微波電衆之 處理圖案化該導電層之既定區域並將其去除 立而，半導體裝置製造方法，藉由偏]處理而將在且有私 之絕緣層上所形成之導電層之既定區域圖Σ 並將，、去除時，在85mToir以上之高壓條件下。掛车墓舻 板施加70mW/cm2以上之偏懕工碰* π 士 ：午下對丰導體基 喈调少妈、由雷將之偏壓功率，並同可進行使用以微波為電 ΐίΪίί處理°藉此可抑制_處理時產生之反應 性維並同時進行蝕刻處理。如此，可確保 ιηίϊΐίί麻亦即，使蝕刻殘餘物不產生於豎立面之侧部，並 狀开ίϋ'ΪΐΪΐ傷等以進雜刻處理。且可在如此具有突出 ΐίΐίϊίϊ蝕刻處理中’以一步驟之蝕刻處理去除導 電層因此可射且有效率製造半導體裝置。 200931526 時對半導體基板施加 160〇Stttt施聽中’進行#顺辦_氣體流量在 =^=1，層係_膜，__石夕。 基板上形_上；^立之之步驟前先在半導體 ===Ϊ電層表面之薄膜絕緣層。 Ο ❹ 高度位於gi面^部。大出狀形態之絕緣層’從面起隔著既定 驟：於本發明之另-祕中，铸魏置之銳方法包含下列步 用域表面朝上方豎立延伸而 用及沒極區域之間之通道區域上形成 形成包覆該突條部及該絕緣層之導 層並同時去除電層以形成閘k。留下該通虹域上之導電 【實施方式】 發明圖，以依本 外觀立體圖。圖1係顯示i電層之蝕列:二裝置11之 係顯示導電層之二 =之=== 200931526 箭頭IV之方向觀察圖3所示之半導體裝 本發明一實施形態之由半導體裝 ^圖又，關於依 η，包含3 _造娜樣紅轉體裝置 漿處理裝置作為蝕刻處理裝置為例說明。、置，且使用例如微波電 首先’在形成絕緣層之步驟前，先 T基板12上形成自轉體基板12之主 半導 多晶石夕複數突條部14。各突條部14剖面 ^方^立延伸之 係朝圖i中箭頭J所示之方向延伸之形狀接二= 条部Μ ❹ ❾ 向，如圖3所示，於包夾後述钱刻處理縱長方 形成源極區域及汲極區域。 导冤層21之位置’分別 之半;齡突條部-外 薄膜之沿〇2膜16，因包覆著突條部14而形 -—, 丑旦立面丄9、及從面18起隰荽ρϊ中 $面19上部之頂面2〇。且面18與頂面 ㈣ΐ次形成多晶石夕導電層21以包覆Si〇2膜16。又，針對此導 V罐22為遮罩對為閉電極之部分進行圖案化= if 所示’留下位於源極區域奴極區域之間之通道區 ，上之導電層2〗並同時藉由姓刻處理去除導電層仏盆餘之^ ^ 1為閘電I如此’在半導體基板12上形成3轉造之腦 电日日體。 在此’侧處理中係在85mToIT以上之高麼之條件下對 J基板施加70mW/cm2以上之偏壓功率，並同時使用以微波為電 水源之微波電漿進行。又，此時之蝕刻氣體係以混合有C12、HBr 與Ar之混合氣體為材料氣體。 200931526 依此一半導體裝置11之絮纟止古、土 ％丄 立面19之突出狀形態17之 丄，刻處理將於具有豎 定區域圖案化並加以去除之際緣^153形成之導電層Μ之既 對半導體基板施加7GmW/em2 ^ ^ 條件下， 如此即可確崎之正雜= 處理。 面19之側部，並同時防止係絕緣層之Si〇"膜16 生於豎立 ❹ 侧處理。此時可防止SiQ膜16巾 2β、 ^鱗以進行 頂錢部仅祕。 21。® U之侧處理中’以一步驟之餘刻處理去除導^層 。此不兩如習知例進行2次蝕刻處理即可，n%米、 率製造料體裳置1卜 他PT故可適當且有效 之概^係顯示使上述電裝產生以進行處理之電衆處理裳置構成 參照圖5即知，電聚處理裝置31，包含:收納半 3ίίϊί板36施以處理之可密封腔室32，與使由波i管供電 之微波所造成之電漿在腔室32内產生之天線部33。 电 在此簡單說明關於使用圖5所示之電漿處理裝置3ι， 行以電聚實行之侧處理之方法。首先將係處《1 象之+導體基板36載置於腔室32内之基座34上。其次吏 32内減壓至係上述微波電漿之放電條件之壓力為止，並 ^ 36賦予既定之偏電壓。其後藉由高頻電源產生微波 I V官對天線部33供電。如此電漿自天線部33產生於電漿產# 域37。所產生之電漿通過氣體喷淋頭35抵達電漿擴散^域％品 在電漿擴散區域38與由氣體喷淋頭35所供給之材料氣 以進行抛慎理。 繼US’ '天線部33其構成:具有包含自下方侧觀察時形成為τ字形 複數槽孔之圓板狀狹缝板，自此複數槽孔朝腔室32内放射由$皮導 200931526 官所供電之微;皮。藉此可產生具有均—電子密度分布之 且如此構成之電漿處理裝置31，因可任奄變更茂 賴之解，故綠變更偏碰之條件。〜1鱗功率或偏 署车如麟絲_理裝置31之一例’例如可選擇·避 導體基板36之基座34與天線部33之間之距離 載 土座34與氣體喷淋頭35之間之距離約為 40mm °且‘ ▲條件瓶 Ο °在如此構成之《處理裝置31中，若以自 =方侧之距離為A (mm)，則之範圍成為電 - 且50$Α-120之範圍，成為電漿擴散區域38。^ ^ 電子域中，半導體基板36表面Hi j=n〇，縱軸表示選擇比（多晶補i〇2)。又，此力 ，之偏壓功率為7〇mw/cm2。參照圖6即知’堡力為7〇偷 2，擇比最低，隨壓力昇高為8〇mT〇rr、9〇 擇 订 ;此5圖13所示之~與中，若要使選擇 lOOmTorr以上則可找實確保選擇比為5()以上。右-為 遷功ΐ 圖7中橫轴表示偏 圖7中&砉干懕六如^擇比又使用拍00mm之半導體基板。 功y即可提昇選擇比。然而，若在5響以下，^小ς降 曰難以控制形狀，故有侧面带 ίί:=免S=*功率定為5_上丄ί== 選擇比在60以上/ '在此’即使偏®功率為100W亦可確保 且關於偏電屢之頻率，過高則電漿會產生於半導縣板上。 11 200931526 ί壓ί ==會降低上述偏壓功率之效率。因此，藉由使偏 ϊίϊί ί! 上2MHz以下’可迴避上述問題並且減少因 蝕刻處理而產生之反應產物再解離，可維持更高選擇比。 導體ϋίΐ雖偏電壓頻率高於2MHz°，會導致電聚在半 而一i n 但，、右為更南頻，例如ι〇ΜΗζ〜i5MHz，具體 貝1相較f2應’因高頻而使半導體基板對離 ===頻ΐ可減少對半導體基板之損害。因此，亦可 8係顯賴5所示之電漿處理裝置中，壓力與電子溫产之 i糸圖。圖8中橫軸表示壓力（mT〇 ) ^ ，藉由使壓力在 50以上需#雷早Λ 丨方兩便璉擇比在 以下，以下。因此，藉由使電子溫度在1麟 之越)4，★同選擇比朗時進行蝴處理。如此，可確伴雜 Ο ==緣==物，於暨立面19之侧部，=時 沿〇2膜16中曰特別3異命之祕等以進仃蝕刻處理。此時可防止 處理巾W 另大^狀形悲' 17之+導體裝置11之蝕刻 又，在此，電t声,丨’/^適#且有效率製造半導體裝置1卜 且進杆斜二又夕〉彳誤差’誤差中至少包含1O5ev以下者。 j處理時蝕刻氣體之流量宜在1600sccm以上。圖1() 圖η所示之圖中在此，所謂推拔角度係 又，圖11係=ίΐ之側㈣23與面18所構成之角度… /'圖4所不之箭頭ΙΠ之方向觀察圖4所示之半導體 12 200931526 裝置11之圖。參照圖10及圖u即知，隨氣體流量增加，推 度變得趨於垂直。亦即成料電層21之侧壁面23垂直於面18】 豎立形狀’此垂直形狀佳。在此，藉由使氣體流量在1600scc 上’可使推拔角度相較於88 (deg)更接近垂直。又，自適用 述電聚處理裝置之-般渦輪泵之能力而言，氣體流量宜在 2200sccm 以下。 Ο ❹ 又，上述實施賴巾，_級本發明—實卿態之 =製造方法’包含職包制面魏㈣之紐部14而形成之 二有突出狀形態17之絕緣層之步驟，但並不限於此，例如亦= s形成剖面為階梯狀，具有面及自此面朝上方豐立之登立匕 ，狀^態之絕緣層之步驟。此係_於如此之突出狀形態， 面之間留有蝕刻殘餘物之虞’於蝕刻處理時需要高選 且於上述實施形態’雖係在導電料多晶⑪，形成 之=極蝕刻處理㈣上述綠進行酬處理 = I?二?層之難蝴處理時。=層二： 含Τι (鈦）或Ta (组）、W (鶴）等者而言亦適用。 伸並實魏化物（Sl〇2)雖適用為絕緣層， 仁並不限於此，例如包含Hf (銓）或 化膜亦可適用為絕緣層。 ~⑻等之氧 體作ϋίί施^態Γ雖已説明關於使用3維構造之聰電晶 體作為+導體讀之例，但並不祕此
Charge Coupled Dev1Ce^i|^：iT 維構造半導體裝置時。 導體το件之3 以上雖已參照圖式説明本發明實施形態 ==加範圍喊是犧圍二 【產業上利用性】 依本發明之半導體裝置製造方法，可在需適當且有效率製造 13 200931526 時有效利用。 【圖式簡單說明] 圖1係顯示依本發明之轉 外觀立體®。 1所τ之半導體裝置之 圖3係顯示對圖j所示之 ϋ裝置之外觀立軸。 ㈣裝置細糊處理後之半導 圖4係自圖3中箭頭JV之方向觀容 外觀立體圖。 和鄕圖3所不之半導體裝置之 圓5係顯示依本發明一實 用之電漿處理|置之概略圖。 +導體裝置製造方法所使 圖6,顯示壓力與選擇比之關係圖。 圖7係顯示偏壓功率與選擇比之關係圖。 圖8係顯示壓力與電子溫度之關係圖。 圖9係顯示電子溫度與選擇比之關係圖。 圖10係顯示氣體流量與推拔角度之關係圖。 ❹ 係自圖4中箭頭ΙΠ之方向觀察圖4所示之 觀立ϊ ί係顯示包含3維構造之腦電晶體之半導體裝置it 之 狀態12穌之轉齡置巾訂拽刻殘餘物 圖14係顯示蝕刻面積比與選擇比之關係圖。 【主要元件符號說明】 A...距離 高度差 1、II、III、.IV、XIL··箭頭 14 200931526
Si、S2、S3…面積 a..角度 a、b、c...情形 11、101…半導體裝置 12、 102.. ·半導體基板（晶圓） 13、 103...主表面 14、 104...突條部 15、 105…絕緣層 16、 106...SiO2膜 q 17...突出狀形態 18、108··.面 19.. .豎立面 20、 107...頂面 21、 109...導電層 22.. .51. 23.. .側壁面 31.. .電漿處理裝置 32.. .腔室 33.. .天線部 © 34...基座 35.. .氣體喷淋頭 3 6...半導體基板 37…電漿產生區域 38.. .電漿擴散區域 110.. .光阻 111.. .蝕刻殘餘物 15

Claims (1)

  1. 200931526 十、申請專利範圍： 1· 一種半導體裝置之製造方法’包含下列步驟： 基板上形成突出狀形態之絕緣層，該突出_態 緣層具有一面及自該面朝上方豎立之豎立面； 形成導電層，而使其包覆該突出狀形態之絕緣層；及 在85m^brr以上之高壓之條件下，對該半導體基板施加 微壓神，_由制以微波作為賴源之 被波之侧處理’將該導f層之既定區域圖案化 。 2. 如申請專利_第丨項之半導體裝置之製造方法，在& ❹ ❹ 理時，對該半導體基板施加馳Hz以上2MHz' g 之偏電壓。 + 3. 如申請專利範圍第1項之半導體震置之製造方法，其中進行兮 蝕刻處理時之蝕刻氣體流量在1600sccm以上。 tv如ί請專利範圍第1項之半導體裝置之製造方法，其中該絕緣 層係氧化矽膜，該導電層係多晶矽。 、、 5·如申請專利範圍帛i項之半導體裝置之製造方法，其中 ϊΐί絕Ϊ層之步驟前，先在該半導體基板上形成朝上方登立之 ίϊΪΪΪ之導電層之步驟，且該絕緣層包含形成於該突出狀形 態之導電層表面之薄膜絕緣層。 6狀ΐΐϊΐΐΐ 項之半導财置之製造方法，其中該突出 狀祕之絕緣層，自該面隔魏定高度位於該賢立面之上部。 7. -種半導财置之製造方法，包含下列步驟： 用 、在半導體基板之主表面上形成自該主表面朝上方登立延伸 以形成為源極區域及汲極區域之突條部； 形 、在位於該突條部之源極區域及汲極區域之間的通道區域上 成用以形成閘極絕緣膜之絕緣層； 形成包覆該突條部及該絕緣層之導電層；及 在85m^brr以上之高壓之條件下，對該半導體基板施加 mW/cm以上之偏壓功率’並㈤時藉由使肖以微丨皮為電漿源之微 16 200931526 波電漿之蝕刻處理，將該導電層圖案化，留下該通道區域上之導 電層並同時去除該導電層以形成閘電極。 十一、圖式：
    17
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Families Citing this family (128)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9324576B2 (en) 2010-05-27 2016-04-26 Applied Materials, Inc. Selective etch for silicon films
US10283321B2 (en) 2011-01-18 2019-05-07 Applied Materials, Inc. Semiconductor processing system and methods using capacitively coupled plasma
US8999856B2 (en) 2011-03-14 2015-04-07 Applied Materials, Inc. Methods for etch of sin films
US9064815B2 (en) 2011-03-14 2015-06-23 Applied Materials, Inc. Methods for etch of metal and metal-oxide films
US8808563B2 (en) 2011-10-07 2014-08-19 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US9267739B2 (en) 2012-07-18 2016-02-23 Applied Materials, Inc. Pedestal with multi-zone temperature control and multiple purge capabilities
US9373517B2 (en) 2012-08-02 2016-06-21 Applied Materials, Inc. Semiconductor processing with DC assisted RF power for improved control
US9034770B2 (en) 2012-09-17 2015-05-19 Applied Materials, Inc. Differential silicon oxide etch
US9023734B2 (en) 2012-09-18 2015-05-05 Applied Materials, Inc. Radical-component oxide etch
US9390937B2 (en) 2012-09-20 2016-07-12 Applied Materials, Inc. Silicon-carbon-nitride selective etch
US9132436B2 (en) 2012-09-21 2015-09-15 Applied Materials, Inc. Chemical control features in wafer process equipment
US8969212B2 (en) 2012-11-20 2015-03-03 Applied Materials, Inc. Dry-etch selectivity
US8980763B2 (en) 2012-11-30 2015-03-17 Applied Materials, Inc. Dry-etch for selective tungsten removal
US9111877B2 (en) 2012-12-18 2015-08-18 Applied Materials, Inc. Non-local plasma oxide etch
US8921234B2 (en) 2012-12-21 2014-12-30 Applied Materials, Inc. Selective titanium nitride etching
US10256079B2 (en) 2013-02-08 2019-04-09 Applied Materials, Inc. Semiconductor processing systems having multiple plasma configurations
US9362130B2 (en) 2013-03-01 2016-06-07 Applied Materials, Inc. Enhanced etching processes using remote plasma sources
US9040422B2 (en) 2013-03-05 2015-05-26 Applied Materials, Inc. Selective titanium nitride removal
US20140271097A1 (en) 2013-03-15 2014-09-18 Applied Materials, Inc. Processing systems and methods for halide scavenging
US9493879B2 (en) 2013-07-12 2016-11-15 Applied Materials, Inc. Selective sputtering for pattern transfer
JP2015041724A (ja) * 2013-08-23 2015-03-02 東京エレクトロン株式会社 半導体デバイスを製造する方法
US9773648B2 (en) 2013-08-30 2017-09-26 Applied Materials, Inc. Dual discharge modes operation for remote plasma
US9576809B2 (en) 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9520303B2 (en) 2013-11-12 2016-12-13 Applied Materials, Inc. Aluminum selective etch
US9245762B2 (en) 2013-12-02 2016-01-26 Applied Materials, Inc. Procedure for etch rate consistency
US9287095B2 (en) 2013-12-17 2016-03-15 Applied Materials, Inc. Semiconductor system assemblies and methods of operation
US9287134B2 (en) 2014-01-17 2016-03-15 Applied Materials, Inc. Titanium oxide etch
US9396989B2 (en) 2014-01-27 2016-07-19 Applied Materials, Inc. Air gaps between copper lines
US9293568B2 (en) 2014-01-27 2016-03-22 Applied Materials, Inc. Method of fin patterning
US9385028B2 (en) 2014-02-03 2016-07-05 Applied Materials, Inc. Air gap process
US9499898B2 (en) 2014-03-03 2016-11-22 Applied Materials, Inc. Layered thin film heater and method of fabrication
US9299575B2 (en) 2014-03-17 2016-03-29 Applied Materials, Inc. Gas-phase tungsten etch
US9299537B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9299538B2 (en) 2014-03-20 2016-03-29 Applied Materials, Inc. Radial waveguide systems and methods for post-match control of microwaves
US9903020B2 (en) 2014-03-31 2018-02-27 Applied Materials, Inc. Generation of compact alumina passivation layers on aluminum plasma equipment components
US9309598B2 (en) 2014-05-28 2016-04-12 Applied Materials, Inc. Oxide and metal removal
US9406523B2 (en) 2014-06-19 2016-08-02 Applied Materials, Inc. Highly selective doped oxide removal method
US9378969B2 (en) 2014-06-19 2016-06-28 Applied Materials, Inc. Low temperature gas-phase carbon removal
US9425058B2 (en) 2014-07-24 2016-08-23 Applied Materials, Inc. Simplified litho-etch-litho-etch process
US9496167B2 (en) 2014-07-31 2016-11-15 Applied Materials, Inc. Integrated bit-line airgap formation and gate stack post clean
US9378978B2 (en) 2014-07-31 2016-06-28 Applied Materials, Inc. Integrated oxide recess and floating gate fin trimming
US9659753B2 (en) 2014-08-07 2017-05-23 Applied Materials, Inc. Grooved insulator to reduce leakage current
US9553102B2 (en) 2014-08-19 2017-01-24 Applied Materials, Inc. Tungsten separation
US9355856B2 (en) 2014-09-12 2016-05-31 Applied Materials, Inc. V trench dry etch
US9368364B2 (en) 2014-09-24 2016-06-14 Applied Materials, Inc. Silicon etch process with tunable selectivity to SiO2 and other materials
US9355862B2 (en) 2014-09-24 2016-05-31 Applied Materials, Inc. Fluorine-based hardmask removal
US9613822B2 (en) 2014-09-25 2017-04-04 Applied Materials, Inc. Oxide etch selectivity enhancement
US9355922B2 (en) 2014-10-14 2016-05-31 Applied Materials, Inc. Systems and methods for internal surface conditioning in plasma processing equipment
US9966240B2 (en) 2014-10-14 2018-05-08 Applied Materials, Inc. Systems and methods for internal surface conditioning assessment in plasma processing equipment
US11637002B2 (en) 2014-11-26 2023-04-25 Applied Materials, Inc. Methods and systems to enhance process uniformity
US10573496B2 (en) 2014-12-09 2020-02-25 Applied Materials, Inc. Direct outlet toroidal plasma source
US10224210B2 (en) 2014-12-09 2019-03-05 Applied Materials, Inc. Plasma processing system with direct outlet toroidal plasma source
US9502258B2 (en) 2014-12-23 2016-11-22 Applied Materials, Inc. Anisotropic gap etch
US9343272B1 (en) 2015-01-08 2016-05-17 Applied Materials, Inc. Self-aligned process
US11257693B2 (en) 2015-01-09 2022-02-22 Applied Materials, Inc. Methods and systems to improve pedestal temperature control
US9373522B1 (en) 2015-01-22 2016-06-21 Applied Mateials, Inc. Titanium nitride removal
US9449846B2 (en) 2015-01-28 2016-09-20 Applied Materials, Inc. Vertical gate separation
US9728437B2 (en) 2015-02-03 2017-08-08 Applied Materials, Inc. High temperature chuck for plasma processing systems
US20160225652A1 (en) 2015-02-03 2016-08-04 Applied Materials, Inc. Low temperature chuck for plasma processing systems
US9881805B2 (en) 2015-03-02 2018-01-30 Applied Materials, Inc. Silicon selective removal
US9741593B2 (en) 2015-08-06 2017-08-22 Applied Materials, Inc. Thermal management systems and methods for wafer processing systems
US9691645B2 (en) 2015-08-06 2017-06-27 Applied Materials, Inc. Bolted wafer chuck thermal management systems and methods for wafer processing systems
US9349605B1 (en) 2015-08-07 2016-05-24 Applied Materials, Inc. Oxide etch selectivity systems and methods
US10504700B2 (en) 2015-08-27 2019-12-10 Applied Materials, Inc. Plasma etching systems and methods with secondary plasma injection
KR102576706B1 (ko) 2016-04-15 2023-09-08 삼성전자주식회사 반도체 소자의 제조 방법
US10522371B2 (en) 2016-05-19 2019-12-31 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US10504754B2 (en) 2016-05-19 2019-12-10 Applied Materials, Inc. Systems and methods for improved semiconductor etching and component protection
US9865484B1 (en) 2016-06-29 2018-01-09 Applied Materials, Inc. Selective etch using material modification and RF pulsing
US10062575B2 (en) 2016-09-09 2018-08-28 Applied Materials, Inc. Poly directional etch by oxidation
US10629473B2 (en) 2016-09-09 2020-04-21 Applied Materials, Inc. Footing removal for nitride spacer
US9679780B1 (en) * 2016-09-28 2017-06-13 International Business Machines Corporation Polysilicon residue removal in nanosheet MOSFETs
US9721789B1 (en) 2016-10-04 2017-08-01 Applied Materials, Inc. Saving ion-damaged spacers
US10062585B2 (en) 2016-10-04 2018-08-28 Applied Materials, Inc. Oxygen compatible plasma source
US10546729B2 (en) 2016-10-04 2020-01-28 Applied Materials, Inc. Dual-channel showerhead with improved profile
US9934942B1 (en) 2016-10-04 2018-04-03 Applied Materials, Inc. Chamber with flow-through source
US10062579B2 (en) 2016-10-07 2018-08-28 Applied Materials, Inc. Selective SiN lateral recess
US9947549B1 (en) 2016-10-10 2018-04-17 Applied Materials, Inc. Cobalt-containing material removal
US9768034B1 (en) 2016-11-11 2017-09-19 Applied Materials, Inc. Removal methods for high aspect ratio structures
US10163696B2 (en) 2016-11-11 2018-12-25 Applied Materials, Inc. Selective cobalt removal for bottom up gapfill
US10026621B2 (en) 2016-11-14 2018-07-17 Applied Materials, Inc. SiN spacer profile patterning
US10242908B2 (en) 2016-11-14 2019-03-26 Applied Materials, Inc. Airgap formation with damage-free copper
US10566206B2 (en) 2016-12-27 2020-02-18 Applied Materials, Inc. Systems and methods for anisotropic material breakthrough
US10403507B2 (en) 2017-02-03 2019-09-03 Applied Materials, Inc. Shaped etch profile with oxidation
US10431429B2 (en) 2017-02-03 2019-10-01 Applied Materials, Inc. Systems and methods for radial and azimuthal control of plasma uniformity
US10043684B1 (en) 2017-02-06 2018-08-07 Applied Materials, Inc. Self-limiting atomic thermal etching systems and methods
US10319739B2 (en) 2017-02-08 2019-06-11 Applied Materials, Inc. Accommodating imperfectly aligned memory holes
US10943834B2 (en) 2017-03-13 2021-03-09 Applied Materials, Inc. Replacement contact process
US10319649B2 (en) 2017-04-11 2019-06-11 Applied Materials, Inc. Optical emission spectroscopy (OES) for remote plasma monitoring
US11276559B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Semiconductor processing chamber for multiple precursor flow
US11276590B2 (en) 2017-05-17 2022-03-15 Applied Materials, Inc. Multi-zone semiconductor substrate supports
US10497579B2 (en) 2017-05-31 2019-12-03 Applied Materials, Inc. Water-free etching methods
US10049891B1 (en) 2017-05-31 2018-08-14 Applied Materials, Inc. Selective in situ cobalt residue removal
US10920320B2 (en) 2017-06-16 2021-02-16 Applied Materials, Inc. Plasma health determination in semiconductor substrate processing reactors
US10541246B2 (en) 2017-06-26 2020-01-21 Applied Materials, Inc. 3D flash memory cells which discourage cross-cell electrical tunneling
US10727080B2 (en) 2017-07-07 2020-07-28 Applied Materials, Inc. Tantalum-containing material removal
US10541184B2 (en) 2017-07-11 2020-01-21 Applied Materials, Inc. Optical emission spectroscopic techniques for monitoring etching
US10354889B2 (en) 2017-07-17 2019-07-16 Applied Materials, Inc. Non-halogen etching of silicon-containing materials
US10043674B1 (en) 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10170336B1 (en) 2017-08-04 2019-01-01 Applied Materials, Inc. Methods for anisotropic control of selective silicon removal
US10297458B2 (en) 2017-08-07 2019-05-21 Applied Materials, Inc. Process window widening using coated parts in plasma etch processes
US10283324B1 (en) 2017-10-24 2019-05-07 Applied Materials, Inc. Oxygen treatment for nitride etching
US10128086B1 (en) 2017-10-24 2018-11-13 Applied Materials, Inc. Silicon pretreatment for nitride removal
US10256112B1 (en) 2017-12-08 2019-04-09 Applied Materials, Inc. Selective tungsten removal
US10903054B2 (en) 2017-12-19 2021-01-26 Applied Materials, Inc. Multi-zone gas distribution systems and methods
US11328909B2 (en) 2017-12-22 2022-05-10 Applied Materials, Inc. Chamber conditioning and removal processes
US10854426B2 (en) 2018-01-08 2020-12-01 Applied Materials, Inc. Metal recess for semiconductor structures
US10964512B2 (en) 2018-02-15 2021-03-30 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus and methods
US10679870B2 (en) 2018-02-15 2020-06-09 Applied Materials, Inc. Semiconductor processing chamber multistage mixing apparatus
TWI716818B (zh) 2018-02-28 2021-01-21 美商應用材料股份有限公司 形成氣隙的系統及方法
US10593560B2 (en) 2018-03-01 2020-03-17 Applied Materials, Inc. Magnetic induction plasma source for semiconductor processes and equipment
US10319600B1 (en) 2018-03-12 2019-06-11 Applied Materials, Inc. Thermal silicon etch
US10497573B2 (en) 2018-03-13 2019-12-03 Applied Materials, Inc. Selective atomic layer etching of semiconductor materials
US10573527B2 (en) 2018-04-06 2020-02-25 Applied Materials, Inc. Gas-phase selective etching systems and methods
US10490406B2 (en) 2018-04-10 2019-11-26 Appled Materials, Inc. Systems and methods for material breakthrough
US10699879B2 (en) 2018-04-17 2020-06-30 Applied Materials, Inc. Two piece electrode assembly with gap for plasma control
US10886137B2 (en) 2018-04-30 2021-01-05 Applied Materials, Inc. Selective nitride removal
US10755941B2 (en) 2018-07-06 2020-08-25 Applied Materials, Inc. Self-limiting selective etching systems and methods
US10872778B2 (en) 2018-07-06 2020-12-22 Applied Materials, Inc. Systems and methods utilizing solid-phase etchants
US10672642B2 (en) 2018-07-24 2020-06-02 Applied Materials, Inc. Systems and methods for pedestal configuration
US11049755B2 (en) 2018-09-14 2021-06-29 Applied Materials, Inc. Semiconductor substrate supports with embedded RF shield
US10892198B2 (en) 2018-09-14 2021-01-12 Applied Materials, Inc. Systems and methods for improved performance in semiconductor processing
US11062887B2 (en) 2018-09-17 2021-07-13 Applied Materials, Inc. High temperature RF heater pedestals
US11417534B2 (en) 2018-09-21 2022-08-16 Applied Materials, Inc. Selective material removal
US11682560B2 (en) 2018-10-11 2023-06-20 Applied Materials, Inc. Systems and methods for hafnium-containing film removal
US11121002B2 (en) 2018-10-24 2021-09-14 Applied Materials, Inc. Systems and methods for etching metals and metal derivatives
US11437242B2 (en) 2018-11-27 2022-09-06 Applied Materials, Inc. Selective removal of silicon-containing materials
US11721527B2 (en) 2019-01-07 2023-08-08 Applied Materials, Inc. Processing chamber mixing systems
US10920319B2 (en) 2019-01-11 2021-02-16 Applied Materials, Inc. Ceramic showerheads with conductive electrodes

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5495287A (en) 1992-02-26 1996-02-27 Hitachi, Ltd. Multiple-tone display system
JP2574094B2 (ja) * 1992-02-27 1997-01-22 株式会社日本製鋼所 エッチング方法
JPH0799295A (ja) * 1993-06-07 1995-04-11 Canon Inc 半導体基体の作成方法及び半導体基体
US5437765A (en) * 1994-04-29 1995-08-01 Texas Instruments Incorporated Semiconductor processing
JP2822952B2 (ja) 1995-08-30 1998-11-11 日本電気株式会社 半導体装置の製造方法
US5907170A (en) * 1997-10-06 1999-05-25 Micron Technology, Inc. Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
US6599829B2 (en) * 1998-11-25 2003-07-29 Texas Instruments Incorporated Method for photoresist strip, sidewall polymer removal and passivation for aluminum metallization
KR100377174B1 (ko) * 2000-08-31 2003-03-26 주식회사 하이닉스반도체 캐패시터의 제조 방법
JP2002261043A (ja) 2001-03-05 2002-09-13 Hitachi Ltd 半導体装置およびその製造方法
KR100458288B1 (ko) 2002-01-30 2004-11-26 한국과학기술원 이중-게이트 ＦｉｎＦＥＴ 소자 및 그 제조방법
US6759286B2 (en) * 2002-09-16 2004-07-06 Ajay Kumar Method of fabricating a gate structure of a field effect transistor using a hard mask
US20040077178A1 (en) * 2002-10-17 2004-04-22 Applied Materials, Inc. Method for laterally etching a semiconductor structure
KR100555512B1 (ko) * 2003-07-31 2006-03-03 삼성전자주식회사 폴리실리콘 식각 마스크를 이용한 반도체 소자의 제조방법
US7094613B2 (en) * 2003-10-21 2006-08-22 Applied Materials, Inc. Method for controlling accuracy and repeatability of an etch process
US20050188922A1 (en) * 2004-02-26 2005-09-01 Tokyo Electron Limited. Plasma processing unit
JP2005277397A (ja) * 2004-02-26 2005-10-06 Tokyo Electron Ltd プラズマ処理装置
US7326611B2 (en) * 2005-02-03 2008-02-05 Micron Technology, Inc. DRAM arrays, vertical transistor structures and methods of forming transistor structures and DRAM arrays
KR100653536B1 (ko) * 2005-12-29 2006-12-05 동부일렉트로닉스 주식회사 반도체 소자의 핀 전계효과 트랜지스터 제조방법

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