200926371 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種氧化鋁基板及其製法，尤指一種不 易彎曲且具高線路密度之氧化鋁基板及其製法。 5 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 ❹ （Integration)以及微塑化（Miniaturization)的封裝要求， 10 提供多數主被動元件及線路連接之封裝基板，亦逐漸由單 層板演變成多層板，以使在有限的空間下，藉由層間連接 技術（Interlayer connection)擴大封裝基板上可利用的佈 線面積而配合高電子密度之積體電路（Integrated circuit) 需求。 15 一般半導體裝置之製程，首先係由晶片載板製造業者 生產適用於該半導體裝置之晶片載板，如基板或導線架。 β 之後再將該些晶片載板交由半導體封裝業者進行置晶、打 線、封膠以及植球等封裝製程。又一般半導體封裝是將半 導體晶片背面黏貼於封裝基板頂面進行打線接合（wire 20 bonding )，或者將半導體晶片之作用面以覆晶接合（flip chip)方式與封裝基板接合，再於基板之背面植以焊料球以 供與其他電子裝置如印刷電路板進行電性連接。 上述之封裝基板可參考圖1所示之結構。目前業界常用 BT樹脂（BismaleimideTriazineResin)作為核心板 11 的材 5 200926371 5 ❾ 10 15 ❷ 20 料，而後進行線路製程，以於核心板11表面形成線路12及 導通核心板11兩側表面線路12之電鍍導通孔121 ’再利用增 層技術形成增層結構13,其中，該增層結構13係包括導電 盲孔131及增層線路層132及介電層134，最後於增層結構13 表面形成一防焊層14,形成一封裝基板1〇。 然而，因上述核心板採用BT樹脂（Bismaleimide TriazineResin)作為材料，而增層結構13之介電層134之材 料大多為ABF樹脂（Ajinomoto build-up film)，通常不同 材料所具有之熱膨脹係數（Coefficient of thermal expansion，CTE)不同。封裝基板10常因核心板u (Βτ樹 脂）與介電層134( ABF樹脂）兩者熱膨脹係數之差異（cte difference )，或者因核心板11兩表面之增層結構η不對稱， 致使以BT樹脂為材質之硬度低封裝基板1〇因不對稱應力產 生_勉情況’導致生產成品良率偏低且可靠度不佳。 另外，上述之封裝基板1〇需要核心板u，而其線路佈 局（例如線路12及增層線路層132)僅配置於核心板丨丨及介 電層134表面，但核心板11内之電鍍導通孔121常佔用較大 空間，且核心板11内亦無法配置線路，而浪費了線路佈局 空間。因此，若能降低封裝基板產生板彎翹情況，並且提 高封裝基板之生產良率，同時提高線路佈局之密度，將使 封裝基板之應用性提高》 【發明内容】 6 200926371 本發明之主要目的係在提供一種氧化鋁基板及其製 法。本發明所提供之氧化鋁基板，不僅具有不易因應力弯 曲=性’且其厚度較薄並充分利用氧化铭基板線路佈局 以提高線路密度，俾能取代傳統核心板。 5 Ο 10 15 ❹ 為達上述目的，本發明提供一種氧化鋁基板，其包括： 一氧化鋁層，係具有複數開口區，且該複數開口區貫穿該 氧化铭層·’-第—線路層，係配置並嵌人該氧化銘層之該 複數開口區中，且該第一線路層與該氧化鋁層相對兩表面 齊平；以及一第二線路層，係配置於該氧化鋁層及該第一 線路層表面，並直接電性連接於該第一線路層。 上述之氧化鋁基板，較佳更可選擇性包括一防焊層， 係覆蓋該氧化鋁層、該第一線路層、及該第二線路層表面， 且其具有複數開孔以顯露部分該第二線路層以作為電性連 接塾。上述之氧化铭基板中’該第一線路層或該第二 層之材質不限，較佳係選自由銅、錫、鎳、鉻、鈇、銅/鉻 合金、以及錫/鉛合金所組成群組其中之一者。 本發明另提供-種氧㈣基板之製法，其包括：提供 一鋁層，係具有一第一表面及一相對之第二表面；氧化該 鋁層之該第二表面，以形成一氧化鋁層於該第二表面；圖 案化該氧化鋁層，使該氧化鋁層具有複數第一開口區；形 成一第一線路層於該複數第一開口區中，且該第一線路層 與該氧化鋁層之表面齊平；移除該鋁層；以及形成第二 線路層於該第一線路層及該氧化鋁層表面，其中，該第: 線路層係直接電性連接於該第一線路層。 20 200926371 200926371 5 ❹ 10 15 ❹ 上述製法中，氧化該紹層之第二表面時，較佳係透過 形成-第-阻料該㈣之該第_表面上，以保護該第— 表面案化該氧化㈣時，較佳係透過形成 案化之第二阻層於該氧化鋁層表面，並利用蝕刻圖荦化該 氧化紹層，以形成該複數第—開口區顯露部分該銘層。其 中，移除該複數第-開口區内所顯露之該氧輪層之方法 不限’較佳係利用電漿似彳㈤嶋咖㈣卜化學钱刻、 或電溶解（ele_disSGluticm )。另外，形成__第一線路層 於該複數第-開口區前’係較佳移除該第一阻層及該第二 阻層。再者’形成一第—線路層於該複數第一開口區前， 較佳係形成-第三阻層於該銘層之第—表面，並且該第三 阻層係顯露部分該銘層作為導電用。上述製法中，該第— 阻層、第二阻層、及第三阻層之材質不限，較佳係分別為 液態光阻或乾膜。 上述之製法中，形成該第二線路層可選擇性透過下列 兩種方式’其中之-的步驟包含：形成—晶種層覆蓋該第 線路層及該氧化鋁層兩側表面；形成一圖案化之第四阻 ^於各該晶種層表面，且該第四阻層具有複數第二開口 區’電鑛形成該第二線路層於該複數第二開口區中；以及 =除該第四阻層及未受覆蓋之該晶種層。另一則步驟包 3.形成一晶種層覆蓋該第一線路層及該氧化鋁層表面， 並利用該晶種層導電以電鍍形成一金屬層；形成一圖案化 之第四阻層覆蓋該金屬層表面；钱刻未受該第四阻層覆蓋 20 200926371 二線路層；以及移除 之該金屬層及該晶種層，以形成該第 該第四阻層。 5 10 15 ❹ 20 上述之製法中，形成該第二線路層後’更可選擇性包 含形成-防焊層覆蓋該第二線路層、㈣―線㈣及_ 化銘層表面，#中，該防焊層具有複數開孔顯露作為電性 連接墊之部分該第二線路層。 由上述氧化銘基板及其製法得知，其將第一線路配置 於氧化銘層中，第二線路層亦可電性連接至該第一線路 層’故可4分㈣氧仙基板線路佈局”，並取代習 知的電鑛導通孔，以及減少整體封裝基板之厚度，提高封 裝基板之應用性。另-方面，習知以阶樹脂為材質之核心 板常因硬度*足而無法承受增層結構或熱膨脹係數差所產 生之不對稱應力’所會發生基板彎曲情形；然而本發明所 使用之材質為硬度較高之氧仙作為基板，因此可減少上 述基板彎曲情形，進而使成品良率及可靠度提高。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式’熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效^發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更^ 9 200926371 本發明之實施例中該等圖式均為簡化之示意圖。惟該 等圖式僅顯示與本發明有關之元件，其所顯示之元件非為 實際實施時之態樣，其實際實施時之元件數目、形狀等比 例為一選擇性之設計，且其元件佈局型態可能更複雜。 5 實施例1 參考圖2A至圖2N，其為製作本發明氧化鋁基板之流程 示意剖視圖。 首先，如圖2A所示，提供一鋁層21，此鋁層21係具有 10 一第一表面21a及一相對之第二表面21b。接著，如圖2B所 示，形成一形成一第一阻層22於鋁層21之第一表面21a上， 以保護該第一表面21a。形成此第一阻層22之方式，可透過 壓合乾膜或塗佈液態光阻所形成。 如圖2C所示，利用陽極處理，將未受第一阻層22保護 15 的鋁層21之第二表面21b氧化，以形成一氧化鋁層23於第二 表面21b。而後，如圖2D所示，形成一圖案化之第二阻層24 於氧化鋁層23表面。形成此圖案化之第二阻層24之方式，200926371 IX. Description of the Invention: [Technical Field] The present invention relates to an alumina substrate and a method for producing the same, and more particularly to an alumina substrate which is not easily bendable and has a high line density and a method for producing the same. 5 [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, 10 package substrates with most active and passive components and line connections are also gradually evolved from single-layer boards to multi-layer boards. In a limited space, the interlayer area available on the package substrate is expanded by an interlayer connection technology to meet the demand for a high electron density integrated circuit. 15 The general semiconductor device process begins with a wafer carrier manufacturer producing a wafer carrier, such as a substrate or leadframe, suitable for the semiconductor device. After the β carrier, the wafer carrier is then subjected to a packaging process such as crystallization, wire bonding, encapsulation, and ball implantation by a semiconductor package manufacturer. In a general semiconductor package, the back surface of the semiconductor wafer is adhered to the top surface of the package substrate for wire bonding, or the active surface of the semiconductor wafer is bonded to the package substrate by flip chip bonding, and then on the back surface of the substrate. The solder balls are implanted for electrical connection with other electronic devices such as printed circuit boards. The above package substrate can be referred to the structure shown in FIG. At present, BT resin (Bismaleimide Triazine Resin) is commonly used in the industry as the core material 11 200926371 5 ❾ 10 15 ❷ 20 material, and then the line process is performed to form the circuit 12 on the surface of the core board 11 and the plating of the surface 12 on both sides of the core board 11 is turned on. The via hole 121' is further formed into a build-up structure 13 by a build-up technique, wherein the build-up structure 13 includes a conductive via hole 131 and a build-up wiring layer 132 and a dielectric layer 134, and finally an anti-layer structure is formed on the surface of the build-up structure 13 The solder layer 14 forms a package substrate 1 . However, since the core plate is made of BT resin (Bismaleimide Triazine Resin) as a material, and the material of the dielectric layer 134 of the build-up structure 13 is mostly ABF resin (Ajinomoto build-up film), usually the coefficient of thermal expansion of different materials (Coefficient) The thermal expansion (CTE) is different. The package substrate 10 is often caused by a difference in thermal expansion coefficient between the core plate u (Βτ resin) and the dielectric layer 134 (ABF resin), or because the build-up structure η of both surfaces of the core plate 11 is asymmetrical, resulting in BT The hardness of the resin is low, and the package substrate 1 has a low yield and low reliability due to the asymmetry stress. In addition, the above-mentioned package substrate 1 requires a core board u, and its circuit layout (for example, the line 12 and the build-up line layer 132) is disposed only on the surface of the core board and the dielectric layer 134, but the plating in the core board 11 is conducted. The hole 121 often occupies a large space, and the line cannot be disposed in the core board 11, thereby wasting the line layout space. Therefore, if the bending of the package substrate is reduced, and the production yield of the package substrate is improved, and the density of the layout is increased, the applicability of the package substrate is improved. [Invention] 6 200926371 The main object of the present invention is An alumina substrate and a method of making the same are provided. The alumina substrate provided by the present invention not only has a tendency to be bent due to stress = thinness, but also has a thin thickness and makes full use of the oxide substrate layout to increase the line density, and can replace the conventional core plate. 5 Ο 10 15 ❹ In order to achieve the above object, the present invention provides an alumina substrate comprising: an aluminum oxide layer having a plurality of open regions, and the plurality of open regions penetrate the oxidized layer · '-the first circuit layer, Arranging and embedding the plurality of open regions of the oxidized layer, and the first circuit layer is flush with the opposite surfaces of the aluminum oxide layer; and a second circuit layer is disposed on the aluminum oxide layer and the first a circuit layer surface and directly electrically connected to the first circuit layer. Preferably, the alumina substrate further includes a solder resist layer covering the aluminum oxide layer, the first wiring layer, and the surface of the second wiring layer, and having a plurality of openings to expose a portion of the aluminum oxide substrate The two circuit layers serve as electrical connections. In the above-mentioned oxidized substrate, the material of the first circuit layer or the second layer is not limited, and is preferably selected from the group consisting of copper, tin, nickel, chromium, ruthenium, copper/chromium alloy, and tin/lead alloy. One of the groups. The invention further provides a method for preparing an oxygen (tetra) substrate, comprising: providing an aluminum layer having a first surface and an opposite second surface; oxidizing the second surface of the aluminum layer to form an aluminum oxide layer On the second surface; patterning the aluminum oxide layer such that the aluminum oxide layer has a plurality of first open regions; forming a first wiring layer in the plurality of first open regions, and the first wiring layer and the aluminum oxide The surface of the layer is flush; the aluminum layer is removed; and a second circuit layer is formed on the first circuit layer and the surface of the aluminum oxide layer, wherein the first circuit layer is directly electrically connected to the first circuit layer. 20 200926371 200926371 5 ❹ 10 15 ❹ In the above method, when oxidizing the second surface of the layer, it is preferred to pass through the first surface of the (-)-blocking material to protect the first surface. Preferably, when oxidizing (4), the second resist layer is formed on the surface of the aluminum oxide layer, and the oxide layer is etched by an etching pattern to form a portion of the plurality of exposed regions. The method for removing the oxygen wheel layer exposed in the plurality of first opening regions is not limited to the use of plasma like 彳 (5) 嶋 ( 四 四 四 四 四 化学 化学 化学 或 或 或 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 In addition, forming the first circuit layer before the plurality of first opening regions preferably removes the first resist layer and the second resist layer. Further, 'forming a first-circuit layer before the first plurality of open regions, preferably forming a third resist layer on the first surface of the layer, and the third resist layer revealing the portion of the layer as a conductive use. In the above method, the materials of the first resist layer, the second resist layer, and the third resist layer are not limited, and are preferably liquid photoresist or dry film, respectively. In the above method, the step of forming the second circuit layer to selectively pass through the following two methods includes: forming a seed layer covering the first circuit layer and both sides of the aluminum oxide layer; forming a pattern The fourth resist is on the surface of each of the seed layers, and the fourth resistive layer has a plurality of second open regions 'electrical ore forming the second circuit layer in the plurality of second open regions; and = except the fourth resistance The layer and the seed layer that is not covered. Another step includes forming a seed layer covering the first circuit layer and the surface of the aluminum oxide layer, and conducting electricity to form a metal layer by using the seed layer; forming a patterned fourth resist layer covering the metal a layer surface; the carbon layer is not covered by the fourth resist layer 20 200926371 two circuit layers; and the metal layer and the seed layer are removed to form the fourth fourth resist layer. 5 10 15 ❹ 20 In the above method, after forming the second circuit layer, 'more selectively comprises forming - the solder resist layer covers the second circuit layer, (4) - line (4) and _ ing layer surface, #中, The solder mask has a plurality of openings that expose the second circuit layer as part of the electrical connection pads. According to the above-mentioned oxidized substrate and the method for preparing the same, the first circuit is disposed in the oxidized inscription layer, and the second circuit layer is electrically connected to the first circuit layer, so that the wiring layout of the oxon substrate can be 4 points (four) And replace the conventional electric ore conduction hole, and reduce the thickness of the whole package substrate, and improve the applicability of the package substrate. On the other hand, it is known that the core plate made of the step resin is often unable to withstand the buildup due to the hardness* foot. The substrate may be bent by the asymmetric stress generated by the difference in structure or coefficient of thermal expansion. However, the material used in the present invention is a substrate having a higher hardness as a substrate, thereby reducing the bending of the substrate and thereby improving the yield of the finished product. [Embodiment] The following describes the embodiments of the present invention by way of specific embodiments. Those skilled in the art can easily understand other advantages and functions of the present invention from the disclosure of the present disclosure. The details of the present specification can also be applied based on different viewpoints and applications by other different embodiments. Various modifications and changes are possible in the spirit of the invention. The present invention is a simplified schematic diagram of the embodiments of the present invention. However, the drawings only show elements related to the present invention, and the components shown are not actual. In the implementation, the number of components, the shape and the like in actual implementation are a selective design, and the component layout pattern may be more complicated. 5 Embodiment 1 Referring to FIG. 2A to FIG. 2N, the present invention is made. A schematic cross-sectional view of the alumina substrate. First, as shown in Fig. 2A, an aluminum layer 21 having a first surface 21a and an opposite second surface 21b is provided. Next, as shown in Fig. 2B. Forming a first resist layer 22 on the first surface 21a of the aluminum layer 21 to protect the first surface 21a. The first resist layer 22 is formed by embossing dry film or coating liquid light. The second surface 21b of the aluminum layer 21 not protected by the first resist layer 22 is oxidized by anodization to form an aluminum oxide layer 23 on the second surface 21b. As shown in FIG. 2D, a patterned pattern is formed. Two resistive layer 24 on the surface of the alumina layer 23. This second embodiment of the patterned resist layer 24 is formed of,
I 可透過壓合乾膜或塗佈液態光阻形成阻層，再以曝光顯影 形成圖案化之第二阻層24。接著，如圖2E所示，透過蝕刻 20 以圖案化氧化鋁層23，便使氧化鋁層23具有複數第一開口 區23,1顯露部分鋁層21。本實施例蝕刻方式可為電漿蝕刻 (plasma etching )、化學蚀刻、或電溶解（electrodissolution ) 等，以使氧化鋁層23圖案化。 然後，如圖2F所示，移除第一阻層22及第二阻層24。 25 剝除之方式係可取決於第一阻層22及第二阻層24之材質， 200926371 而選擇使用物理性移除或化學性溶除之方式。再參考圖2G 所示，形成一第三阻層26於鋁層21之第一表面21a，形成此 第三阻層26之方式，可透過壓合乾膜或塗佈液態光阻形成 阻層，並顯露鋁層21之周緣的部分第一表面21a(圖中未 5 示）。接著，如圖2H所示，利用該鋁層21顯露之部分第三阻 層26所顯露之部分鋁層21導通電流，進行電鍍，，形成一 第一線路層27於第一開口區231中。其中，第一線路層27與 氧化鋁層23之表面齊平。另外，第一線路層27之材質可選 ^ 自由銅、錫、鎳、鉻、鈦、銅鉻合金、以及錫鉛合金所組 10 成群組其中之一者。 如圖21所示，剝除第三阻層26。剝除第三阻層26之方 式可類似前述移除第一阻層22及第二阻層24之方式。接 著，如圖2J所示，蝕刻移除鋁層21。接續，如圖2K所示， 利用氧化鋁基板40，於其氧化鋁層23及第一線路層27兩側 15 表面先形成一晶種層28。形成此晶種層28之方式，可利用 物理電鍍如濺鍍或蒸鍍或化學電鍍。而後，參考圖2L所示， @ 於該氧化鋁層23及第一線路層27兩侧形成有晶種層28之表 面，壓合一圖案化之第四阻層29，且第四阻層29具有複數 第二開口區291。圖案化第四阻層29以形成第二開口區291 20 之方式及所使用之材質，可如前述第二阻層24。 而後，如圖2M所示，利用晶種層28導通電流，電鍍形 成一第二線路層30於第二開口區291中，其中，第二線路層 30表面齊平於第四阻層29表面，並電性連接於第一線路層 27。此第二線路層30及晶種層28之材質可類似於第一線路 11 200926371 層27。接著，如圖2N所示，剝除第四阻層29及蝕刻移除未 受覆蓋之晶種層29。即可得本發明之氧化鋁基板，其包含 一氧化鋁層23、一第一線路層27及一第二線路層30。此氧 化鋁層23具有複數第一開口區231，且第一開口區231貫穿 5 氧化鋁層23。第一線路層27係配置並嵌入氧化鋁層23之第 一開口區231中，且第一線路層27與氧化鋁層23相對兩表面 齊平。第二線路層30係配置於氧化鋁層23及第一線路層27 表面，並直接接觸電性連接於第一線路層27。若需要更高 © 密度之線路配置，可進行習知的線路增層製程，壓合介電 10 層，再形成導電盲孔及增層線路層，以增加線路的層數。 此外，如圖20所示，選擇形成一防焊層31覆蓋氧化鋁 層23、第一線路層27、及第二線路層30表面。此防焊層31 具有複數開孔3 12顯露部分第二線路層30作為電性連接墊 303。其中，防焊層3 1覆蓋部分電性連接墊303，此電性連 15 接墊303為防焊層定義型電性連接塾（solder mask defined pads，SMD pads)。前述防焊層31開孔312之型式及大小僅 ^ 係作為舉例說明，其實施並不以此為限。 20 實施例2 參考圖2A至2K、圖2L’至20’，其為製作本發明氧化鋁 基板之流程示意剖視圖。 首先，如實施例1中圖2A至2K所示之步驟，先製出一 氧化鋁層23中嵌埋有一第一線路層27。而後，參照圖2L’所 25 示，利用晶種層28導通電流，電鑛形成一金屬層30’覆蓋該 12 200926371 晶種層28之表面。此金屬層30’的材質，可選擇使用如實施 例1中第一線路層27所述之材質。 之後，如圖2M’所示，壓合一圖案化之第四阻層29於金 屬層30’表面。參考圖2N’所示，將金屬層30’及晶種層29沒 5 有受到第四阻層29保護的部分利用蝕刻的方式移除，接著 剝除第四阻層29，以形成一第二線路層30。如此亦可得本 發明之氧化鋁基板。後續，可選擇性如實施例1形成防焊層 31。如圖20’所示，此防焊層31具有複數開孔312顯露部分 〇 第二線路層30作為電性連接墊303，其防焊層31未覆蓋電 10 性連接墊303，此電性連接墊303則為非防焊層定義型電性 連接塾（non-solder mask defined pads，NSMD pads )。前 述防焊層31開孔312之型式及大小僅係作為舉例說明，其實 施並不以此為限。 15 綜上所述，本發明使用具優良熱與機械特性之氧化銘 作為基板，因此若需進行習知機械鑽孔加工製作時，其通 ^ 孔可由一般之100μπι等級到10μιη等級，有利於細微化佈 線，從而提高覆晶基板之佈線密度，不會如同習知ΒΤ樹脂 為材質之核心板，因材質限制而造成製作之孔洞直徑無法 20 低於50 μιη以下，而難以形成更小的孔徑，無法達到更高佈 線密度之缺失。另一方面，本發明製作氧化鋁基板之過程 中，亦利用鋁層、氧化鋁層及非鋁金屬層（如銅）三者不 同之蝕刻選擇性，而於蝕刻過程中僅會使上述其中之一受 到蝕刻，而可進行線路製程，並製得細線路結構，亦可視 25 所需製作增層結構於氧化鋁基板表面以增加線路佈局。 13 200926371 由於將第一線路配置於氧化鋁層中，第二線路層亦可 電性連接至該第一線路層，故可以充分利用氧化鋁基板線 路佈局空間，並取代習知的電鍍導通孔，以及減少整體封 裝基板之厚度，提高封裝基板之應用性。 5 Ο 10 15 ❹ 另外’由於習知以ΒΤ樹脂為材質之核心板常因硬度不 足’而無法承受增層結構或熱膨脹係數差所產生之不對稱 應力’所會發生基板彎曲情形。然而本發明所使用之材質 為硬度較高之氧化鋁作為基板，因此可減少上樹基板彎曲 情形，進而使成品良率及可靠度提高，亦具細微化佈線容 易、尺寸穩定性高等優點。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 【圖式簡單說明】 圖1係習知封裝基板結構之刮視示意圖。 圖2Α〜20係本發明實施例1製作氧化鋁基板之流程剖視示 意圖。 圖2L’〜2〇’係本發明實施例2製作氧化鋁基板之部分流程剖 視示意圖。 【主要元件符號說明】 核心板 增層結構 封裝基板 11 線路 13 12 20 200926371 121 電鍍導通孔 131 導電盲孔 132 增層線路層 134 介電層 21 鋁層 21a * 第一表面 21b 第二表面 22 第一阻層 23 氧化鋁層 24 第二阻層 231 第一開口區 26 第三阻層 27 第一線路層 28 晶種層 273, 303 電性連接墊 29 第四阻層 291 第二開口區 30 第二線路層 30， 金屬層 31, 14 防焊層 312 開孔 15I can form a resist layer by pressing a dry film or coating a liquid photoresist, and then forming a patterned second resist layer 24 by exposure development. Next, as shown in Fig. 2E, the aluminum oxide layer 23 is patterned by etching 20 so that the aluminum oxide layer 23 has a plurality of first opening regions 23, and a portion of the aluminum layer 21 is exposed. The etching method of this embodiment may be plasma etching, chemical etching, or electrodissolution, etc., to pattern the aluminum oxide layer 23. Then, as shown in FIG. 2F, the first resist layer 22 and the second resist layer 24 are removed. 25 The method of stripping may depend on the material of the first resist layer 22 and the second resist layer 24, and the method of physical removal or chemical dissolution is selected in 200926371. Referring to FIG. 2G, a third resist layer 26 is formed on the first surface 21a of the aluminum layer 21. The third resist layer 26 is formed by forming a resist layer by pressing a dry film or coating a liquid photoresist. A portion of the first surface 21a (not shown in the figure) of the periphery of the aluminum layer 21 is exposed. Next, as shown in FIG. 2H, a portion of the aluminum layer 21 exposed by the portion of the third barrier layer 26 exposed by the aluminum layer 21 is electrically connected to the first opening region 231. Among them, the first wiring layer 27 is flush with the surface of the aluminum oxide layer 23. In addition, the material of the first circuit layer 27 can be selected from the group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloy, and tin-lead alloy. As shown in FIG. 21, the third resist layer 26 is stripped. The manner of stripping the third resist layer 26 may be similar to the manner of removing the first resist layer 22 and the second resist layer 24 as described above. Next, as shown in Fig. 2J, the aluminum layer 21 is removed by etching. Next, as shown in Fig. 2K, a seed layer 28 is first formed on the surface of both sides of the aluminum oxide layer 23 and the first wiring layer 27 by the alumina substrate 40. The manner in which the seed layer 28 is formed may be by physical plating such as sputtering or evaporation or chemical plating. Then, as shown in FIG. 2L, a surface of the seed layer 28 is formed on both sides of the aluminum oxide layer 23 and the first wiring layer 27, and a patterned fourth resist layer 29 is pressed, and the fourth resist layer 29 is pressed. There are a plurality of second open areas 291. The manner in which the fourth resist layer 29 is patterned to form the second opening region 291 20 and the material used may be the second resist layer 24 as described above. Then, as shown in FIG. 2M, the current is conducted by the seed layer 28, and a second wiring layer 30 is formed in the second opening region 291 by electroplating, wherein the surface of the second wiring layer 30 is flush with the surface of the fourth resist layer 29, And electrically connected to the first circuit layer 27. The material of the second circuit layer 30 and the seed layer 28 can be similar to the first line 11 200926371 layer 27. Next, as shown in Fig. 2N, the fourth resist layer 29 is stripped and the uncovered seed layer 29 is removed by etching. The alumina substrate of the present invention comprises an aluminum oxide layer 23, a first wiring layer 27 and a second wiring layer 30. The aluminum oxide layer 23 has a plurality of first open regions 231, and the first open regions 231 extend through the aluminum oxide layer 23. The first wiring layer 27 is disposed and embedded in the first opening region 231 of the aluminum oxide layer 23, and the first wiring layer 27 and the aluminum oxide layer 23 are flush with respect to both surfaces. The second circuit layer 30 is disposed on the surface of the aluminum oxide layer 23 and the first circuit layer 27, and is electrically connected to the first circuit layer 27 in direct contact. If a higher density line configuration is required, a conventional line build-up process can be performed to laminate 10 dielectric layers and form conductive blind vias and build-up wiring layers to increase the number of layers. Further, as shown in Fig. 20, a solder resist layer 31 is selected to cover the surfaces of the aluminum oxide layer 23, the first wiring layer 27, and the second wiring layer 30. The solder resist layer 31 has a plurality of openings 3 12 to expose portions of the second wiring layer 30 as electrical connection pads 303. The solder mask layer 31 covers a portion of the electrical connection pad 303. The electrical connection pad 303 is a solder mask defining type (SMD pads). The type and size of the opening 312 of the solder resist layer 31 are only exemplified, and the implementation thereof is not limited thereto. 20 Embodiment 2 Referring to Figures 2A to 2K and Figures 2L' to 20', which are schematic cross-sectional views showing the flow of the alumina substrate of the present invention. First, as in the steps shown in Figs. 2A to 2K of Embodiment 1, a first wiring layer 27 is embedded in an alumina layer 23. Then, referring to Fig. 2L', the current is conducted by the seed layer 28, and the electric ore forms a metal layer 30' covering the surface of the 12 200926371 seed layer 28. The material of the metal layer 30' may be selected from the materials described in the first wiring layer 27 of the first embodiment. Thereafter, as shown in Fig. 2M', a patterned fourth resist layer 29 is laminated to the surface of the metal layer 30'. Referring to FIG. 2N', portions of the metal layer 30' and the seed layer 29 which are protected by the fourth resist layer 29 are removed by etching, and then the fourth resist layer 29 is stripped to form a second. Circuit layer 30. Thus, the alumina substrate of the present invention can be obtained. Subsequently, the solder resist layer 31 may be selectively formed as in Embodiment 1. As shown in FIG. 20', the solder resist layer 31 has a plurality of openings 312 and a portion of the second circuit layer 30 as an electrical connection pad 303. The solder resist layer 31 does not cover the electrical connection pad 303. Pad 303 is a non-solder mask defined type of electrical connection (non-solder mask defined, NSMD pads). The type and size of the opening 312 of the solder resist layer 31 are merely illustrative, and are not limited thereto. 15 In summary, the present invention uses an oxide having excellent thermal and mechanical properties as a substrate. Therefore, if a conventional mechanical drilling process is required, the through hole can be from a general level of 100 μm to a level of 10 μm, which is advantageous for subtle The wiring is increased to increase the wiring density of the flip-chip substrate, and is not like the core plate of the conventional resin. Because of the material limitation, the diameter of the hole to be fabricated cannot be less than 50 μm, and it is difficult to form a smaller aperture. The lack of higher wiring density cannot be achieved. On the other hand, in the process of fabricating the alumina substrate of the present invention, the etching selectivity of the aluminum layer, the aluminum oxide layer and the non-aluminum metal layer (such as copper) is also utilized, and only the above-mentioned ones are used in the etching process. Once etched, the line process can be performed, and a fine line structure can be obtained. It is also possible to create a build-up structure on the surface of the alumina substrate to increase the layout of the line. 13 200926371 Since the first line is disposed in the aluminum oxide layer, the second circuit layer can also be electrically connected to the first circuit layer, so that the layout space of the aluminum oxide substrate can be fully utilized, and the conventional plating via hole is replaced. And reducing the thickness of the overall package substrate, improving the applicability of the package substrate. 5 Ο 10 15 ❹ In addition, the substrate bending is caused by the fact that the core plate made of enamel resin is often incapable of being subjected to the agglomerated structure or the asymmetric stress caused by the difference in thermal expansion coefficient. However, the material used in the present invention is a substrate having a high hardness as a substrate, thereby reducing the bending of the upper substrate, thereby improving the yield and reliability of the finished product, and also having the advantages of fine wiring and high dimensional stability. The above-described embodiments are merely examples for the convenience of the description, and the scope of the claims is intended to be limited by the scope of the claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing the structure of a conventional package substrate. 2 to 20 are schematic cross-sectional views showing the process of fabricating an alumina substrate in Example 1 of the present invention. 2L' to 2'' are schematic cross-sectional views showing a part of the process for producing an alumina substrate in the second embodiment of the present invention. [Main component symbol description] Core board build-up structure package substrate 11 Line 13 12 20 200926371 121 Plating via 131 Conductive blind via 132 Additive wiring layer 134 Dielectric layer 21 Aluminum layer 21a * First surface 21b Second surface 22 a resist layer 23 aluminum oxide layer 24 second resist layer 231 first open region 26 third resist layer 27 first circuit layer 28 seed layer 273, 303 electrical connection pad 29 fourth resist layer 291 second open region 30 Two circuit layer 30, metal layer 31, 14 solder resist layer 312 opening 15