200924594 九、發明說明： 【發明所屬之技術領域] 本發明係關於一種配線基板之製造方法，尤其關於… 種特徵上具有爲了形成鍍覆阻劑之乾膜材及其剝離的配線 基板之製造方法。 【先前技術】 近年來，隨著電子機器之小型化、高性能化，已要求 電子元件之高密度構裝化，適合於達成如此之高密度構裝 化’配線基板的多層化技術已受到重視。使用多層化技術 之具體例’習知爲一種印刷配線基板（所謂層疊（bul id-up ) 印刷配線基板）’其係在已設置貫穿孔（through h〇le)部之 核心基板的單面或雙面，設置已交替積層形成樹脂絕緣層 與導體之層疊層。此種印刷配線基板中之層疊層，例如能 夠利用如下之製程加以製作： 首先，在樹脂絕緣層之整個表面形成鍍銅層。接著， 將具有感光性之乾膜材黏貼於鍍銅層上之後，進行曝光及 因鹼所造成之顯像，形成既定圖案之鍍覆阻劑。接著，進 行鍍銅而在鍍覆阻劑之開口部形成配線圖案層之後，使用 驗剝離液以使鍍覆阻劑膨潤而剝離。接著，藉由進行除去 位於鍍覆阻劑正下方之鍍銅層的蝕刻’形成所希望形狀之 配線圖案層。其後’在配線圖案層上進一步形成樹脂絕緣 層，進行通孔（via hole)貫穿後，再進行鍍銅而形成通孔導 體及鍍銅層。而且’必要時藉由重複數次如此之製程’使 層疊層多層化。還有，針對如此之層疊製程’具有習知數 200924594 個例子（例如’參照專利文獻1 )。還有近年來，尋求配 線圖案層之微細間距化要求正逐漸升高，例如，使配線圖 案層之線寬與相鄰接的配線圖案間之線間隔成爲2 0 μιη以 下（期望爲1 5 μιη以下）。因而，於鍍覆阻劑中，也尋求 正確形成同樣的微細阻劑圖案。 專利文獻1 :日本特開2 0 0 5 - 1 5 0 5 5 4號公報 【發明內容】 發明所欲解決之技術問題 然而’最初用於上述習知配線基板之製造方法的乾膜 材係弱的耐鹼性。因此，於使用鹼的顯像步驟之際，乾膜 材膨潤的結果’由於具有微細阻劑圖案剝離之情形，將遭 遇顯像步驟中之良率差的問題。 因此’於習知技術中，預先將鍍銅層之表面作成超過 〇 . 4 μιη之粗糙面’藉由採取提高乾膜材緊貼性的對策，以 防止微細阻劑圖案之剝離，期望提高顯像步驟中之良率的 方式來進行。然而，進行如此對策之情形，由於鍍銅層表 面凹凸之影響，光於曝光時將散射，解像度將惡化的結果， 變得無法形成形狀佳的微細阻劑圖案。因此，具有得到形 狀上優越的微細配線圖案層將變得困難之問題。 本發明係有鑑於上述課題而予以進行，其目的在於提 供一種配線基板之製造方法，能夠期望提高顯像步驟中之 良率的同時，也能夠確實形成形狀上優越的微細配線圖案 層。 解決問題之技術手段 200924594 爲了解決上述課題之手段係一種配線基板之製造方 法，包含：在樹脂絕緣層之表面形成金屬層的步驟；將具 有耐鹼性之感光性乾膜材黏貼於該金屬層上之後’進行曝 光與利用鹼所造成之顯像，以形成既定圖案之鍍覆阻劑的 步驟；進行鍍覆而在該鍍覆阻劑之開口部形成配線圖案層 的步驟；使用有機胺系剝離液以剝離該鍍覆阻劑的步驟； 及去除位於該鍍覆阻劑正下方之該金屬層的步驟。 因而，若根據上述手段，由於使用具有耐鹼性之感光 性乾膜材，於曝光後，即使進行因鹼所造成之顯像，乾膜 材也完全或幾乎不會膨潤。因此，能夠期望乾膜材之剝離 將被防止，提高顯像步驟中之良率。另外，防止乾膜材剝 離之對策係由於即使不進行金屬層之表面粗糙化也將變得 良好，因而金屬層表面之凹凸程度將變小，曝光時之光散 射的影響將變小。其結果，能夠實現高解像度，形狀佳的 微細阻劑圖案將變得可能形成，進而能夠確實形成形狀上 優越的微細圖案層。 於上述手段之如此製造方法中，首先，在樹脂絕緣層 之表面進行形成金屬層的步驟。只要爲將具有導電性之物 作爲金屬層的話，並未予以特別限定，基於成本性或生產 性等之觀點，較佳爲經由無電解鍍銅所形成的銅薄膜層。 該金屬層之表面狀態並未予以特別限定而爲任意的， 例如可以作成表面粗糙度Ra爲〇·2μιη以上、〇_4μιη以下之 粗糙面。此情形下，如上所述’金屬層表面之凹凸程度將 變小、曝光時之光散射影響變小的結果，成爲容易實現高 200924594 解像度。還有，若表面粗糖度尺3成爲未滿〇·2μηι時，由於 具有乾膜材之緊貼性成爲不足的可能性而不佳。 將具有耐鹼性之感光性乾膜材黏貼於金屬層上的步驟 中’所謂「具有耐驗性」係指具有對氫氧化鈉等之強驗完 全不膨潤，或是具有較習知物更難膨潤之性質。如此性質 上之差異係歸因於例如乾膜材主要成分之樹脂材料交聯密 度高低的差異。亦即，相較於習知物，具有耐鹼性之上述 手段的乾膜材係樹脂材料之交聯密度變高。但是，上述手 段的乾膜材不具有對有機胺之承受性，若曝露於有機胺 時，具有些微溶解於其中之性質。此係意指相對於上述乾 膜材，因爲無法將通常之驗作爲剝離液使用，有機胺能夠 取代鹼而作爲剝離液使用。 於貼附乾膜材之後，進行曝光’進一步進行因鹼所造 成之顯像，形成既定圖案之鍍覆阻劑。線寬與線間隔皆形 成1 5 μ m以下之微細配線圖案之情形下，與此相一致，必 須預先設定微細阻劑圖案的寬度與相鄰接之微細阻劑圖案 間的間隙尺寸。 進行鍍覆而將配線圖案層形成於該鍍覆阻劑開口部之 步驟中，使鍍覆析出於開口部之底面所曝露之金屬層上， 使得該部分變厚。還有，底層之該金屬層係藉由無電解鍍 銅所形成的銅薄膜層之情形，也針對用於形成配線圖案層 之鍍覆，較佳爲選擇無電解鍍銅。 於剝離該鍍覆阻劑之步驟中’必須使用有機胺系剝離 液，於其中，作爲主要成分所含之有機胺，例如，可舉出： 200924594 單乙醇胺、二乙醇胺、三乙醇胺、單甲胺、二甲胺、三甲 胺、乙二胺、異丙胺、異丙醇胺、2-胺基-2-甲基-1-丙醇、 2-胺基-2-甲基-1,3-丙二醇等。此等有機胺之中，特別理想 之有機胺爲含有單乙醇胺之剝離液。其理由係已確認含有 單乙醇胺之剝離液滲透入具有耐鹼性之上述乾膜材而能夠 將其加以溶解，與上述手段關聯之製造方法中，因而在使 用上適合。還有，於鍍覆阻劑剝離步驟中所用之有機胺系 剝離液中，也可以添加一些所謂之肼或TMH等添加劑。 於此步驟中，有機胺系剝離液之處理方法，並未予以 特別限定，可以採用習知之方法，例如，噴淋處理或浸漬 處理等爲適合。進行使用有機胺系剝離液之噴淋處理之情 形，較佳爲將溫度設爲40°C以上、70°C以下，將壓力設爲 0.1 MPa以上、0.4MPa以下，將時間設爲3分鐘以上、低於 3 〇分鐘之處理條件。另外，進行使用有機胺系剝離液之浸 漬處理之情形，較佳爲將溫度設爲40°C以上、70°C以下， 將時間設爲3分鐘以上、低於3 0分鐘之處理條件。如此之 處理條件係不會使生產性或成本性降低，係能夠確實剝離 鍍覆阻劑之條件，因而較佳。 於此，若將溫度設爲低於 4 0 °C 、將壓力設爲低於 0 . 1 MPa或將時間設爲低於3分鐘時，藉由使處理條件變 弱，有機胺系剝離液並未充分作用’將有產生鍍覆阻劑剝 離殘留的可能性。相反的，若將溫度設爲超過70°C、將壓 力設爲超過0.4 Μ P a、將時間設爲3 0分鐘以上時’能夠使 有機胺系剝離液充分作用，另一方面，將有引起生產性降 200924594 低或高製造成本之問題的可能性。另外’藉由使處理條件 變強，具有與原本需要剝離之鍍覆阻劑以外的樹脂部分之 脆化、劣化相關聯的擔憂。 於去除位於該鍍覆阻劑正下方之該金屬層的步驟中’ 使用能溶解已形成金屬層之金屬的蝕刻液以進行餓刻，若 經歷此步驟時，金屬層將被部分切離’關聯的配線圖案層 彼此間相互獨立。 【實施方式】 發明之最佳實施形態 以下，根據第1圖〜第1 3圖，以詳細說明使本發明予 以具體化之一實施形態的配線基板K及其製造方法。 如第1圖所示，本實施形態的配線基板κ係在表背兩 面具有層疊（bulid-up)層BUI、BU2之所謂的層疊多層印 刷配線基板。構成此配線基板K之核心基板1係呈現具有 表面2及背面3之平板狀。 於核心基板1之表面2側所配置之層疊層BU 1係具有 交替積層樹脂絕緣層1 2、1 6、3 0與配線圖案層1 0、2 8、 2 8 a、3 4、3 4 a之構造。於樹脂絕緣層1 2中形成有通孔形成 用孔1 2 a，於其內部形成有使配線圖案層1 〇與內層配線層 4予以導通的場連絡導體（fieid via conductor) 14。於樹脂 絕緣層1 6中形成有通孔形成用孔1 8，於其內部形成有使 配線圖案層i 0、2 8間予以導通之場連絡導體2 6。 於核心基板1之背面3側所配置之層疊層B U 2係具有 交替積層樹脂絕緣層1 3、1 7、3 1與配線圖案層1 1、2 9、 2 9a、35、3 5a之構造。於樹脂絕緣層13中形成有通孔形成 -10- 200924594 用孔1 3 a，於其內部形成有使配線圖案層1 1與內層配線層 5予以導通之場連絡導體1 5。於樹脂絕緣層1 7中’形成有 通孔形成用孔1 9 ’於其內部形成有使配線圖案層1 1、2 9 間予以導通之場連絡導體2 7。 樹脂絕緣層3 0係藉由在既定位置上具有開口部3 6之 阻焊劑3 2而予以整體被覆。此等之開口部3 6係使樹脂絕 緣層3 0上所形成的配線圖案層3 4曝露於第1主面3 2 a側， 其結果，使該配線圖案層3 4得以發揮作爲第1主面側脊槽 (land)之功能。另一方面，樹脂絕緣層31係藉由在既定位 置上具有開口部3 7之阻焊劑3 3而予以整體被覆。此等之 開口部3 7係使樹脂絕緣層3 1上所形成的配線圖案層3 5曝 露於第2主面3 3 a側，其結果，使該配線圖案層3 5得以發 揮作爲第2主面側脊槽之功能。 另外，於第1主面側脊槽之配線圖案層3 4上，形成有 較第1主面3 2 a爲高所突出的焊錫凸塊3 8。然後，於此等 之焊錫凸塊38上，便可能透過焊錫而接合未圖示之1C晶 片等之電子元件。另一方面，第2主面側脊槽之配線圖案 層3 5係成爲與未圖示之母板等印刷配線基板電性相連結。 如第1圖所示，於此配線基板K之內部設置有貫穿孔。 本實施形態之貫穿孔係使圓筒狀之貫穿孔導體7析出於貫 穿核心基板1及樹脂絕緣層1 2、1 3之貫穿孔形成用孔6之 內壁面的同時，也具有利用塡充樹脂9以塡補其貫穿孔導 體7之空洞部的構造。然後，藉由此貫穿孔之貫穿孔導體 7 ’期望核心基板1之表面2側的層疊層B U 1中之導體部 200924594 分與核心基板1之背面3側的層疊層B U 2中之導體部分之 間的導通。 接著’根據第2圖〜第1 3圖之觀點，以說明本實施形 態之配線基板K的製造方法。 第2圖係以雙馬來酸酐縮亞胺三阱（B T )樹脂作爲主 體之厚度約爲0.7mm之核心基板1的槪略剖面圖。在核心 基板1之表面2及背面3，預先黏貼有厚度約70μιη之銅筢 4a、5a。利用習知之手法（於此爲扣除（subtractive )法）， 以將如此核心基板1的銅箔4 a、5 a圖案化，在表面2上及 背面3上形成內層配線層4、5 (參照第3圖）。還有，使 用採取許多個具有複數核心基板1的面板，也可以對於各 核心基板1進行同樣之步驟。 接著，如第4圖所示，藉由在核心基板1中之表面2 上及背面3上，被覆由含有無機塡料之環氧樹脂而成的絕 緣性薄膜，形成樹脂絕緣層1 2、1 3。如此之樹脂絕緣層1 2、 13，厚度約爲40μηι，含有30〜50重量％之由約略球狀之 二氧化矽而成的無機塡料。還有，上述無機塡料之平均粒 徑較佳爲1 · 〇 μιη以上、1 0.0 μιη以下。 接著，相對於樹脂絕緣層1 2、1 3之表面上的既定位 置，沿著其厚度方向以照射未圖示之雷射（於本實施形態 爲二氧化碳氣體雷射）。其結果，如第5圖所示，貫穿樹 脂絕緣層1 2、1 3而形成有使內層配線層4、5裸露於其底 面的約略圓錐形之通孔形成用孔1 2a、1 3 a。再者，藉由使 用鑽孔機以鑿穿既定之位置，形成貫穿核心基板1及樹脂 200924594 絕緣層12、13之內徑約200μπι的貫穿孔形成用孔6° 接著，於含有通孔形成用孔1 2 a、1 3 a之樹脂絕緣層 12、13的整個表面及貫穿孔形成用孔6之內壁面’塗布含 有鈀等之鍍覆觸媒後，再於其上實施無電解鍍銅及電解鍍 銅。其結果，如第6圖所示，在樹脂絕緣層1 2 ' 1 3的整個 表面形成有鍍銅覆膜8 a、8 b，於貫穿孔形成用孔6內形成 有厚度約40μπι且約略圓筒狀之貫穿孔導體7。同時’藉由 在通孔形成用孔1 2 a、1 3 a內，實施追加的鍍銅以形成有場 連絡導體1 4、1 5。 接著，如第6圖所示，將含有無機塡料的塡充樹脂9 之糊塡充於貫穿孔導體7之空洞部內之後，使其熱硬化。 還有，用以形成塡充樹脂9之糊也可以爲含有金屬粉末之 導電性糊。再者，如第7圖所不，進行電解鑛銅而在鑛銅 覆膜8a、8b上形成鍍銅覆膜l〇b、1 lb。此時’同時作成 利用鍍覆蓋l〇a、11a以覆蓋塡充樹脂9之兩端面。還有， 鍍銅覆膜 8 a、1 0 b及鍍銅覆膜8 b、1 1 b之厚度分別約爲 1 5 μ m。 接著，利用習知之扣除法以蝕刻鍍銅覆膜8 a、1 1 b及 鍍銅覆膜8 b、1 1 b，分別形成如第8圖所示之配線圖案層 1 0、1 1。還有，此等之配線圖案層1 0、1 1係成爲層疊層 B U 1、B U 2中之第1層的配線圖案層，位於其內層側之樹 脂絕緣層係成爲第1層的樹脂絕緣層。 接著，如第9圖所示，將上述同樣之絕緣性薄膜貼附 於第1層的樹脂絕緣層1 2及第1層的配線圖案層1 0之上， 200924594 丨樣之絕緣 丨配線圖案 >，相對於 丨由沿著其 :約略圓錐 1 9係貫穿 、1 1 之一 丨觸媒塗布 f脂絕緣層 ί層形成步 菱約0 _ 5 μ m r此時點之 Ϊ主體的厚 i貼於銅薄 :體之習知 2 3係具備 :。將未圖 J狀態下曝 【行顯像。 J各步驟， ' 23a、23b200924594 IX. EMBODIMENT OF THE INVENTION The present invention relates to a method of manufacturing a wiring board, and more particularly to a method of manufacturing a wiring board having a dry film material for forming a plating resist and peeling thereof. . [Prior Art] In recent years, with the miniaturization and high performance of electronic equipment, high-density mounting of electronic components has been required, and multilayer technology suitable for achieving such high-density packaging of wiring boards has been paid attention to. . A specific example of using a multilayering technique is a printed wiring board (so-called bul id-up printed wiring board) which is one side of a core substrate on which a through hole portion is provided or On both sides, a laminated layer in which a resin insulating layer and a conductor are alternately laminated is formed. The laminated layer in such a printed wiring board can be produced, for example, by the following process: First, a copper plating layer is formed on the entire surface of the resin insulating layer. Next, the photosensitive dry film is adhered to the copper plating layer, and then exposed and developed by alkali to form a plating resist of a predetermined pattern. Next, after copper plating is performed and a wiring pattern layer is formed in the opening portion of the plating resist, the plating resist is used to swell and peel off the plating resist. Next, a wiring pattern layer having a desired shape is formed by etching etched to remove the copper plating layer directly under the plating resist. Thereafter, a resin insulating layer is further formed on the wiring pattern layer, a via hole is formed, and then copper plating is performed to form a via conductor and a copper plating layer. Further, the layered layer is multi-layered by "repeating the process several times as necessary". Further, there are known examples of such a lamination process '200924594 (for example, 'refer to Patent Document 1). In recent years, the demand for the fine pitch of the wiring pattern layer is gradually increasing. For example, the line width between the line width of the wiring pattern layer and the adjacent wiring pattern is 20 μm or less (expected to be 15 μm). the following). Therefore, in the plating resist, it is also sought to correctly form the same fine resist pattern. [Patent Document 1] Japanese Patent Laid-Open Publication No. H05- 1 5 0 5 5 4 SUMMARY OF THE INVENTION PROBLEM TO BE SOLVED BY THE INVENTION However, the dry film material which is originally used in the above-described conventional method for manufacturing a wiring substrate is weak. Alkali resistance. Therefore, at the time of the development step using the alkali, the result of the swelling of the dry film material "due to the peeling of the fine resist pattern", there is a problem that the yield in the developing step is poor. Therefore, in the conventional technique, the surface of the copper plating layer is formed in advance to exceed the roughness of 〇. 4 μιη by taking measures to improve the adhesion of the dry film to prevent the peeling of the fine resist pattern, and it is desired to improve the display. It works like the yield in the steps. However, in the case of such a countermeasure, the surface of the copper plating layer is affected by the unevenness of the surface of the copper plating layer, and the light is scattered during the exposure, and the resolution is deteriorated, so that the fine resist pattern having a good shape cannot be formed. Therefore, it is difficult to obtain a fine wiring pattern layer superior in shape. The present invention has been made in view of the above-described problems, and an object of the invention is to provide a method for producing a wiring board, which is capable of improving the yield in the developing step and reliably forming a fine wiring pattern layer having a superior shape. Technical Solution for Solving the Problem 200924594 A method for manufacturing the wiring substrate according to the method for producing the above-mentioned problem, comprising: a step of forming a metal layer on a surface of a resin insulating layer; and adhering a photosensitive dry film material having alkali resistance to the metal layer a step of performing exposure and development by alkali to form a plating resist of a predetermined pattern; a step of forming a wiring pattern layer in the opening of the plating resist by plating; using an organic amine system a step of stripping the plating resist; and removing the metal layer directly under the plating resist. Therefore, according to the above means, since the photosensitive dry film having alkali resistance is used, the dry film is completely or hardly swollen even after exposure by alkali. Therefore, it can be expected that the peeling of the dry film material is prevented, and the yield in the developing step is improved. Further, the countermeasure against the peeling of the dry film material is good even if the surface of the metal layer is not roughened, so that the degree of unevenness on the surface of the metal layer is small, and the influence of light scattering at the time of exposure becomes small. As a result, a high resolution can be realized, and a fine resist pattern having a good shape can be formed, and a fine pattern layer excellent in shape can be surely formed. In the manufacturing method of the above means, first, a step of forming a metal layer is performed on the surface of the resin insulating layer. The material having conductivity is not particularly limited as long as it has a conductive layer, and a copper thin film layer formed by electroless copper plating is preferred from the viewpoint of cost, productivity, and the like. The surface state of the metal layer is not particularly limited, and may be, for example, a rough surface having a surface roughness Ra of 〇·2 μm or more and 〇_4 μm or less. In this case, as described above, the degree of unevenness on the surface of the metal layer is small, and the effect of light scattering at the time of exposure becomes small, and the high resolution of 200924594 is easily achieved. Further, when the surface coarse sugar level 3 becomes less than 2 μm, the adhesion of the dry film material may be insufficient. In the step of adhering the alkali-resistant photosensitive dry film to the metal layer, the term "having a testability" means having no sensitivity to sodium hydroxide or the like, or having a more conventional property. The nature of difficulty in swelling. Such a difference in properties is attributed to the difference in the cross-linking density of the resin material such as the main component of the dry film. That is, the cross-linking density of the dry film-based resin material having the above-described means of alkali resistance is higher than that of the conventional one. However, the dry film of the above-mentioned means does not have the property of being resistant to an organic amine, and if exposed to an organic amine, it has a property of being slightly dissolved therein. This means that the organic amine can be used as a peeling liquid in place of a base because it cannot be used as a peeling liquid with respect to the above dry film. After the dry film material is attached, exposure is carried out to further develop a plating resist formed by a base to form a predetermined pattern. In the case where the line width and the line interval are each formed into a fine wiring pattern of 15 μm or less, in accordance with this, the gap size between the width of the fine resist pattern and the adjacent fine resist pattern must be set in advance. The plating is performed in the step of forming the wiring pattern layer in the opening portion of the plating resist, and the plating is deposited on the metal layer exposed on the bottom surface of the opening portion to make the portion thick. Further, in the case where the metal layer of the underlayer is a copper thin film layer formed by electroless copper plating, and also for plating for forming a wiring pattern layer, electroless copper plating is preferably selected. In the step of peeling off the plating resist, it is necessary to use an organic amine-based stripping liquid, and the organic amine contained as a main component, for example, 200924594 monoethanolamine, diethanolamine, triethanolamine, monomethylamine , dimethylamine, trimethylamine, ethylenediamine, isopropylamine, isopropanolamine, 2-amino-2-methyl-1-propanol, 2-amino-2-methyl-1,3-propanediol Wait. Among these organic amines, a particularly preferred organic amine is a stripping solution containing monoethanolamine. The reason for this is that it has been confirmed that the peeling liquid containing monoethanolamine penetrates into the above-mentioned dry film material having alkali resistance and can be dissolved therein, and is suitable for use in the production method described above. Further, in the organic amine-based stripping liquid used in the plating resist stripping step, some additives such as hydrazine or TMH may be added. In the step, the method for treating the organic amine-based stripping solution is not particularly limited, and a conventional method such as a shower treatment or an immersion treatment may be employed. In the case of performing the shower treatment using the organic amine-based stripper, the temperature is preferably 40° C. or higher and 70° C. or lower, and the pressure is 0.1 MPa or more and 0.4 MPa or less, and the time is set to 3 minutes or longer. , less than 3 minutes of processing conditions. Further, in the case of performing the immersion treatment using the organic amine-based peeling liquid, the temperature is set to 40 ° C or higher and 70 ° C or lower, and the treatment time is set to 3 minutes or longer and less than 30 minutes. Such a treatment condition is preferable because it does not deteriorate the productivity or the cost, and it is possible to surely peel off the conditions of the plating resist. Here, when the temperature is set to be lower than 40 ° C, the pressure is set to be lower than 0.1 MPa, or the time is set to be less than 3 minutes, the organic amine-based stripping solution is obtained by weakening the processing conditions. Insufficient action 'will have the possibility of peeling off the plating resist. On the other hand, when the temperature is more than 70 ° C, the pressure is more than 0.4 Μ P a , and the time is set to 30 minutes or more, the organic amine-based stripping liquid can be sufficiently acted, and on the other hand, it will be caused. Productivity down 200924594 Possibility of low or high manufacturing costs. Further, by increasing the processing conditions, there is a concern that embrittlement and deterioration of the resin portion other than the plating resist which is required to be peeled off may be associated. In the step of removing the metal layer directly under the plating resist, 'using an etching solution capable of dissolving the metal forming the metal layer to perform the hungry, if the metal layer is partially cut away from the correlation The wiring pattern layers are independent of each other. [Embodiment] BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a wiring board K and a method for manufacturing the same according to an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 1 . As shown in Fig. 1, the wiring board κ of the present embodiment is a so-called laminated multi-layer printed wiring board having bud-up layers BUI and BU2 on both front and back sides. The core substrate 1 constituting the wiring board K has a flat plate shape having a front surface 2 and a back surface 3. The laminated layer BU 1 disposed on the surface 2 side of the core substrate 1 has alternating laminated resin insulating layers 1 2, 16 6 and 30 and wiring pattern layers 10, 28, 2 8 a, 3 4, 3 4 a Construction. A via hole forming hole 12a is formed in the resin insulating layer 12, and a fieid via conductor 14 for electrically connecting the wiring pattern layer 1 and the inner wiring layer 4 is formed therein. A through hole forming hole 18 is formed in the resin insulating layer 16 and a field connecting conductor 26 for conducting the wiring pattern layers i 0 and 28 is formed therein. The laminated layer B U 2 disposed on the back surface 3 side of the core substrate 1 has a structure in which the resin insulating layers 13, 17 and 31 and the wiring pattern layers 1 1 , 2 9 , 2 9a, 35 and 35a are alternately laminated. A through hole is formed in the resin insulating layer 13. -10-200924594 A hole 13a is formed, and a field connecting conductor 15 for electrically connecting the wiring pattern layer 1 and the inner wiring layer 5 is formed therein. A via hole forming hole 17 is formed in the resin insulating layer 17, and a field connecting conductor 27 that electrically connects the wiring pattern layers 1 1 and 29 is formed therein. The resin insulating layer 30 is entirely covered by the solder resist 32 having the opening portion 36 at a predetermined position. In the opening portion 36, the wiring pattern layer 34 formed on the resin insulating layer 30 is exposed on the first main surface 3 2 a side, and as a result, the wiring pattern layer 34 is rendered as the first main The function of the side ridge. On the other hand, the resin insulating layer 31 is entirely covered by the solder resist 3 having the opening portion 37 in the positioning position. The opening portion 3 7 exposes the wiring pattern layer 35 formed on the resin insulating layer 31 to the second main surface 3 3 a side, and as a result, the wiring pattern layer 35 is used as the second main The function of the side ridge groove. Further, on the wiring pattern layer 34 of the first main surface side land groove, solder bumps 38 which are higher than the first main surface 3 2 a are formed. Then, on the solder bumps 38, it is possible to bond electronic components such as 1C wafers (not shown) through solder. On the other hand, the wiring pattern layer 35 of the second main-surface-side ridge groove is electrically connected to a printed wiring board such as a mother board (not shown). As shown in FIG. 1, a through hole is provided inside the wiring board K. In the through hole of the present embodiment, the cylindrical through-hole conductor 7 is deposited through the inner wall surface of the through-hole forming hole 6 of the core substrate 1 and the resin insulating layers 1 2 and 13 and also has a resin-filled resin. 9 is to compensate for the structure of the cavity portion of the through-hole conductor 7. Then, the conductor portion 200924594 in the laminated layer BU1 on the surface 2 side of the core substrate 1 is destined to be the through-hole conductor 7' of the through-hole, and the conductor portion in the laminated layer BU2 on the back surface 3 side of the core substrate 1 Conduction between. Next, a method of manufacturing the wiring board K of the present embodiment will be described based on the viewpoints of Figs. 2 to 13 . Fig. 2 is a schematic cross-sectional view of the core substrate 1 having a thickness of about 0.7 mm as a main body of a bismaleimide triad (B T ) resin. On the surface 2 and the back surface 3 of the core substrate 1, copper plaques 4a and 5a having a thickness of about 70 μm are adhered in advance. The inner layer wiring layers 4 and 5 are formed on the front surface 2 and the back surface 3 by patterning the copper foils 4 a and 5 a of the core substrate 1 by a conventional method (in this case, a subtractive method). Figure 3). Further, it is also possible to perform the same steps for each of the core substrates 1 by using a plurality of panels having a plurality of core substrates 1. Next, as shown in FIG. 4, an insulating film made of an epoxy resin containing an inorganic pigment is coated on the surface 2 and the back surface 3 of the core substrate 1 to form a resin insulating layer 1 2, 1 3. Such a resin insulating layer 1 2, 13 has a thickness of about 40 μm and contains 30 to 50% by weight of an inorganic tantalum material consisting of approximately spherical cerium oxide. Further, the average particle diameter of the inorganic binder is preferably 1 · 〇 μηη or more and 1 0.0 μηη or less. Then, with respect to the position on the surface of the resin insulating layers 1 2, 1 3, a laser (not shown) is irradiated along the thickness direction thereof (carbon dioxide gas laser in the present embodiment). As a result, as shown in Fig. 5, the approximately conical through hole forming holes 1 2a, 1 3 a are formed through the resin insulating layers 1 2 and 13 to expose the inner wiring layers 4 and 5 to the bottom surface thereof. . Further, by using a drilling machine to cut through a predetermined position, a through hole forming hole 6 having an inner diameter of about 200 μm is formed through the insulating layers 12 and 13 of the core substrate 1 and the resin 200924594, and then the through hole is formed. The entire surface of the resin insulating layers 12 and 13 of the holes 1 2 a and 1 3 a and the inner wall surface of the through hole forming hole 6 are coated with a plating catalyst containing palladium or the like, and then electroless copper plating is performed thereon. Electrolytic copper plating. As a result, as shown in Fig. 6, copper plating films 8a and 8b are formed on the entire surface of the resin insulating layer 1 2' 1 3, and a thickness of about 40 μm is formed in the through hole forming hole 6 and is approximately round. A cylindrical through-hole conductor 7. At the same time, additional copper plating is performed in the via hole forming holes 1 2 a, 1 3 a to form the field contact conductors 14 and 15. Next, as shown in Fig. 6, the paste containing the inorganic tantalum-containing filling resin 9 is filled in the cavity portion of the through-hole conductor 7, and then thermally cured. Further, the paste for forming the filling resin 9 may be a conductive paste containing a metal powder. Further, as shown in Fig. 7, electrolytic copper ore is formed to form a copper plating film l〇b and 1 lb on the ore copper coatings 8a and 8b. At this time, the both ends of the filling resin 9 are covered by the plating cover l〇a, 11a. Further, the thickness of the copper plating film 8 a, 10 b and the copper plating film 8 b, 1 1 b is about 15 μm, respectively. Next, the copper plating films 8 a and 1 1 b and the copper plating films 8 b and 1 1 b are etched by a conventional subtractive method to form wiring pattern layers 10 and 1 1 as shown in Fig. 8, respectively. Further, the wiring pattern layers 10 and 1 1 are the wiring pattern layers of the first layer among the laminated layers BU 1 and BU 2 , and the resin insulating layer on the inner layer side is the resin insulating layer of the first layer. Floor. Next, as shown in Fig. 9, the same insulating film is attached to the resin insulating layer 1 2 of the first layer and the wiring pattern layer 10 of the first layer, and the insulating wiring pattern of 200924594 is used. ;, relative to the 丨 by along: about a conical 1 9 system through, 1 1 丨 丨 涂布 涂布 涂布 涂布 脂 脂 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 形成 约 约 约 约 约Copper thin: The traditional knowledge of the body 2 3 series has: Will not be exposed in the J state [line imaging. J steps, '23a, 23b
形成第2層的樹脂絕緣層16。同樣的，將上述同 性薄膜貼附於第1層的樹脂絕緣層1 3及第1層的 層1 1之上，形成第2層的樹脂絕緣層1 7。再考 上述樹脂絕緣層16、17之表面上的既定位置，藉 厚度方向而照射該同樣之雷射（未圖示），形成 形之通孔形成用孔1 8、1 9。通孔形成用孔1 8、 樹脂絕緣層1 6、1 7的同時，也使配線圖案層1 〇 部分露出其底面。然後，預先將上述同樣的鍍覆 於含有上述通孔形成用孔1 8、1 9之內壁面的橫 16、17整個表面上之後，實施無電解鍍銅（金屬 驟）。若經歷如此之金屬層形成步驟時，形成有厚f 之銅薄膜層2 0、2 1 (參照第9圖中之虛線）。：& 銅薄膜層20、21的表面粗糙度Ra約爲0_2μιη。 接著，如第1 〇圖所示’將以丙烯酸系樹脂怎 度約25 μπι之感光性及絕緣性的乾膜材22、23 | 膜層2 0、2 1之整個表面。相較於以環氧樹脂爲兰 物的乾膜材，於本實施形態所選擇的乾膜材2 2、 於強鹼中較難以膨潤之性質。因此’具有耐鹼它 示之曝光用光罩配置於如此之乾膜材22、23上白 光，其後，使用氫氧化鈉溶液等之驗顯像液以自 然後，依照如上述之乾膜材黏貼、曝光及顯像白 形成如第11圖之既定圖案的鍍覆阻劑22a、22b (鍍覆阻劑形成步驟）。 此等鍍覆阻劑22a、22b、23a、23b之中’針對狹小的 200924594 鍍覆阻劑22b、23b，成爲線寬爲15μιη以下（於本實 態之情形爲1 〇 μπι )之微細阻劑圖案。另外，狹小的鍍 劑22b、22b間，或是23b、23b間之開口部24a、25a 寸（亦即，線間隔）成爲1 5 μπι以下（於本實施形態 形爲1 Ομιη )。還有，狹小的鍍覆阻劑22b與相鄰於此 覆阻劑2 2 a之間，或是狹小的鍍覆阻劑2 3 b與相鄰於 鍍覆阻劑2 3 a之間的開口部2 4 b、2 5 b之尺寸也成爲同 尺寸。同時，在鄰接於通孔形成用孔1 8、1 9之左右的 膜層20、21之表面上，形成有較廣面積之開口部24、 接著，相對於位於開口部2 4、2 4 a、2 5、2 5 a之底 通孔形成用孔1 8、1 9之底面的銅薄膜層2 0、2 1，利 知之手法以進行電解鍍銅而使鍍銅析出。其結果，如 圖所示，場連絡導體2 6、2 7將形成於通孔形成用孔 1 9內，與場連絡導體2 6、2 7 —體之配線圖案層2 8、 形成於開口部2 4、2 5中。同時，剖面爲縱向長的長^ 寬度爲1 5 μ m以下（於本實施形態之情形爲1 〇 μ m )、 約爲25 μπι之微細配線圖案層28a、29a形成於各開 24a、25a中（配線圖案層形成步驟）。 接著’如第1 3圖所示，使用含有以單乙醇胺作爲 成分之有機胺系剝離液（0.5重量％以上、5 〇 °C以上） 離鍍覆阻劑2 2 a、2 2 b、2 3 a、2 3 b (鍍覆阻劑剝離步驟 其後，利用鈾刻液以軟蝕刻處理位於鍍覆阻劑2 2 a (23a、23b)之正下方的銅薄膜層20(21)後而加以 (鈾刻步驟）。若經歷此步驟時，銅薄膜層2 0 ( 2 1 ) 施形 覆阻 之尺 之情 之鍍 此之 樣之 銅薄 25。 面或 用習 第12 18、 29將 ί形、 厚度 口部 主要 ，剝 :)^ 、22b .去除 將被 200924594 切離。由以上之結果，含有線寬及線間隔皆約爲1 0 μιη之 微細配線圖案層2 8 a、2 9 a的配線圖案層2 8、2 8 a、2 9、2 9 a 將予以形成。 再者，於形成有配線圖案層2 8、2 8 a之第2層樹脂絕 緣層1 6之表面上將形成新的樹脂絕緣層（第3層樹脂絕緣 層）30。另一方面’於形成有配線圖案層29、29a之第2 層樹脂絕緣層1 7之表面上將形成新的樹脂絕緣層（第3層 樹脂絕緣層）3 1。然後，於此等樹脂絕緣層3 〇、3 1上之既 定位置’根據上述方法而形成未圖示之通孔形成用孔。其 後’在樹脂絕緣層3 0、3 1之表面及通孔形成用孔內形成銅 薄膜層’進行由如上述之乾膜材黏貼、曝光及顯像之各步 驟而成的鍍覆阻劑形成步驟，進一步進行配線圖案層形成 步驟、鍍覆阻劑剝離步驟、蝕刻步驟。其結果，含有線寬 及線間隔皆約爲1 Ο μ m之微細配線圖案層3 4 a、3 5 a的配線 圖案層34、34a、35、35a將分別形成於第3層的樹脂絕緣 層3 0、3 1上。 進一步分別將厚度2 5 μ m之阻焊劑3 2、3 3設置於第3 層樹脂絕緣層3 0、3 1上的同時，也在開口部3 6之底面所 曝露之配線圖案34上形成焊錫凸塊38;在開口部37之底 面所曝露之配線圖案3 5上實施鎳-金鍍覆。以上之結果， 能夠得到於如第1圖所示之表背兩面具備層疊層BU1、BU2 的配線基板K。 因而’右根據本實施形態，能夠得到以下之效果： (1 )於本實施形態之製造方法中，由於使用具有耐鹼 -16- 200924594 性之感光性乾膜材22、23而進行圖案形成，即使於曝光後 進行因鹼所造成之顯像，乾膜材22、23也完全不或幾乎不 膨潤。因此，能夠期望於經歷顯像步驟之時點的乾膜材2 2、 2 3之剝離將被防止，提高顯像步驟中之良率。因而，以高 良率製造配線基板K將成爲可能，另外，低成本化也將變 得容易達成。 (2 )另外，若根據本實施形態之製造方法時，乾膜材 2 2、2 3之剝離防止對策，則無進行銅薄膜層2 0、2 1之表 面粗糙化的必要性。因此，相較於將表面粗糙化設爲必要 之習知方法，銅薄膜層2 0、2 1表面之凹凸程度將變小，曝 光時之光散射的影響將變小。其結果，能夠實現以高解像 度之曝光，尺寸精確度佳的微細阻劑圖案22b、23b將變得 可能形成。因此，使確實形成線寬與線間隔皆爲1 5 μιη以 下，並且形成形狀上優越之微細配線圖案的微細配線圖案 層2 8 a ' 2 9 a將成爲可能。 (3 )於本實施形態之製造方法中，使用含有以單乙醇 胺作爲主要成分之有機胺系剝離液而進行鍍覆阻劑22a、 2 2b ' 23a、23b (乾膜材22、23 )之剝離。因此，能夠確 實使剝離液對於具有耐鹼性之上述乾膜材2 2、2 3予以作 用，故能夠確實剝離此乾膜材。 還有，本發明之實施形態也可以變更爲如下之方式： *於上述實施形態中，雖然選擇BT樹脂作爲形成核心 基板1之材料，但是並不受此樹脂所限定，例如，也可以 使用環氧樹脂、聚醯亞胺樹脂等，或是，也可以使用使具 200924594 有連續氣孔之P T F E等三次元網狀構造的氟系樹脂中含有 玻璃纖維等之複合材料等。還有，核心基板1可以爲氧化 鋁、氮化矽、氮化硼、氧化鈹、矽酸、玻璃陶瓷、氮化鋁 等之由陶瓷等而成的高溫燒結基板以外’也可以爲於約 1 00 〇°C以下之較低溫進行燒結的低溫燒結基板。再者，核 心基板1也可以爲由銅合金或Fe-42wt% Ni合金等而成的 金屬核心基板。另外，於本發明中，由於核心基板1並非 必要的構造，例如，採用無核心基板之形態也將被容許。 f '' i *於上述實施形態中，雖然選擇銅作爲形成配線圖案層 10、11或連絡導體（via conductor) 26、27等導體部的金屬 材料，但是並不受銅所限定，也可能採用銀、鎳、金、銅 合金、鐵鎳合金等。或是利用塗布導電性樹脂等之方法， 以取代使用金屬之鍍覆層而形成上述導體部。 *於上述實施形態中，雖然連絡導體2 6、2 7之形態係 採用以導體完全塡補內部之場連絡導體，當然也可以採用 內部並未完全被導體所塡補之倒圓錐形的準型A resin insulating layer 16 of the second layer is formed. Similarly, the above-mentioned isotropic film is attached to the resin insulating layer 13 of the first layer and the layer 1 1 of the first layer to form a resin insulating layer 17 of the second layer. Further, the predetermined position on the surface of the resin insulating layers 16 and 17 is irradiated, and the same laser (not shown) is irradiated in the thickness direction to form through-hole forming holes 18 and 19. The through hole forming holes 18 and the resin insulating layers 16 and 17 are also exposed to the bottom surface of the wiring pattern layer 1 。. Then, the same plating as described above is applied to the entire surfaces of the horizontal portions 16 and 17 including the inner wall surfaces of the through hole forming holes 18 and 19, and then electroless copper plating (metal step) is performed. When subjected to such a metal layer forming step, a copper thin film layer 20 and 2 1 having a thickness f are formed (see a broken line in Fig. 9). :& The copper film layers 20, 21 have a surface roughness Ra of about 0_2 μιη. Next, as shown in Fig. 1, the entire surface of the film layers 20, 23 and the film layers 20 and 21 which are photosensitive and insulating with an acrylic resin of about 25 μm are used. The dry film material 2 selected in the present embodiment is more difficult to swell in a strong alkali than the dry film material in which the epoxy resin is a blue material. Therefore, the exposure mask having the alkali resistance is disposed on the dry film materials 22 and 23 for white light, and thereafter, after using the sodium hydroxide solution or the like to visualize the image liquid, the dry film material is as described above. Pasting, exposing, and developing white form plating resists 22a, 22b (plating resist forming step) of a predetermined pattern as shown in Fig. 11. Among these plating resists 22a, 22b, 23a, and 23b, the '200924594 plating resists 22b and 23b are narrow and have a line width of 15 μm or less (in the case of the actual state, 1 〇μπι). pattern. Further, the openings 24a and 25a (i.e., the line spacing) between the narrow plating agents 22b and 22b or between 23b and 23b are 1 5 μm or less (in the present embodiment, the shape is 1 Ομιη). Also, between the narrow plating resist 22b and the adjacent resisting agent 2 2 a, or between the narrow plating resist 2 3 b and the opening adjacent to the plating resist 2 3 a The sizes of the portions 2 4 b and 2 5 b also become the same size. At the same time, on the surface of the film layers 20, 21 adjacent to the through hole forming holes 18, 19, a wide area of the opening portion 24 is formed, and then, with respect to the opening portion 2 4, 2 4 a The copper thin film layers 20 and 2 on the bottom surface of the via hole forming holes 18 and 19 of 2, 5, and 5 5 a are known to perform electrolytic copper plating to deposit copper plating. As a result, as shown in the figure, the field contact conductors 26, 27 are formed in the via hole forming hole 19, and the wiring pattern layer 28 of the field connection conductors 26, 27 is formed in the opening. 2 4, 2 5 in. At the same time, the fine wiring pattern layers 28a and 29a having a length of a longitudinal length of 15 μm or less (in the case of the present embodiment, 1 〇μm) and about 25 μm are formed in the respective openings 24a and 25a. (Wiring pattern layer forming step). Next, as shown in Fig. 1 3, an organic amine-based stripping solution containing a monoethanolamine as a component (0.5% by weight or more, 5 〇 ° C or more) is used to remove the plating resist 2 2 a, 2 2 b, and 2 3 . a, 2 3 b (plating resist stripping step thereafter, using a uranium engraving solution to softly etch the copper thin film layer 20 (21) directly under the plating resist 2 2 a (23a, 23b) (Uranium engraving step). If you go through this step, the copper film layer 20 ( 2 1 ) is shaped like a copper-plated copper plate. 25 or 29:18 The shape and thickness of the mouth are mainly stripped:)^, 22b. The removal will be cut off by 200924594. From the above results, the wiring pattern layers 28, 28a, 2 9 and 2 9 a of the fine wiring pattern layers 2 8 a and 2 9 a each having a line width and a line interval of about 10 μm are formed. Further, a new resin insulating layer (third resin insulating layer) 30 is formed on the surface of the second resin insulating layer 16 on which the wiring pattern layers 28, 28a are formed. On the other hand, a new resin insulating layer (third resin insulating layer) 31 is formed on the surface of the second resin insulating layer 17 on which the wiring pattern layers 29 and 29a are formed. Then, a hole for forming a through hole (not shown) is formed in accordance with the above method at a predetermined position on the resin insulating layers 3 〇, 31. Thereafter, 'a copper thin film layer is formed on the surface of the resin insulating layers 30 and 31 and the through hole forming holes', and a plating resist is formed by the steps of adhering, exposing and developing the dry film as described above. In the forming step, the wiring pattern layer forming step, the plating resist stripping step, and the etching step are further performed. As a result, the wiring pattern layers 34, 34a, 35, and 35a including the fine wiring pattern layers 3 4 a and 3 5 a having a line width and a line interval of about 1 μm are formed in the resin insulating layer of the third layer, respectively. 3 0, 3 1 on. Further, solder resists 3 2 and 3 3 having a thickness of 25 μm are respectively disposed on the third resin insulating layers 30 and 31, and solder is also formed on the wiring pattern 34 exposed on the bottom surface of the opening portion 36. The bump 38 is formed by performing nickel-gold plating on the wiring pattern 35 exposed on the bottom surface of the opening 37. As a result of the above, the wiring board K having the laminated layers BU1 and BU2 on both sides of the front and back sides as shown in Fig. 1 can be obtained. Therefore, according to the present embodiment, the following effects can be obtained: (1) In the production method of the present embodiment, pattern formation is performed by using the photosensitive dry film materials 22 and 23 having alkali resistance of -16, 2009,594, Even after the exposure due to the alkali after the exposure, the dry film materials 22 and 23 did not swell at all or hardly. Therefore, it can be expected that the peeling of the dry film 2 2, 2 3 at the time point of the developing step is prevented, and the yield in the developing step is improved. Therefore, it is possible to manufacture the wiring board K at a high yield, and it is also easy to achieve cost reduction. (2) In the production method according to the present embodiment, the countermeasure against peeling of the dry film members 2, 2, 3 is not necessary to roughen the surface of the copper thin film layers 20 and 21. Therefore, compared with the conventional method of roughening the surface, the degree of unevenness of the surface of the copper thin film layers 20 and 21 becomes small, and the influence of light scattering upon exposure becomes small. As a result, it is possible to realize exposure with high resolution, and fine resist patterns 22b, 23b excellent in dimensional accuracy are likely to be formed. Therefore, it is possible to form the fine wiring pattern layer 2 8 a ' 2 9 a in which the line width and the line interval are all formed to be 15 μm or less and the fine wiring pattern excellent in shape is formed. (3) In the production method of the present embodiment, the plating resist 22a, 2 2b ' 23a, 23b (dry film 22, 23) is peeled off using an organic amine-based stripping liquid containing monoethanolamine as a main component. . Therefore, it is possible to surely apply the peeling liquid to the above-mentioned dry film members 2, 2 3 having alkali resistance, so that the dry film material can be surely peeled off. Further, the embodiment of the present invention may be modified as follows: * In the above embodiment, the BT resin is selected as the material for forming the core substrate 1, but it is not limited by the resin. For example, a ring may be used. An oxygen resin, a polyimide resin, or the like may be used, or a composite material such as glass fiber may be used in a fluorine-based resin having a three-dimensional network structure such as PTFE having continuous pores in 200924594. Further, the core substrate 1 may be a high-temperature sintered substrate made of ceramics such as alumina, tantalum nitride, boron nitride, tantalum oxide, niobic acid, glass ceramics, or aluminum nitride, or may be about 1 A low-temperature sintered substrate sintered at a lower temperature of 00 ° C or lower. Further, the core substrate 1 may be a metal core substrate made of a copper alloy or a Fe-42 wt% Ni alloy. Further, in the present invention, since the core substrate 1 is not in a necessary structure, for example, a form in which a coreless substrate is used is also tolerated. f '' i * In the above embodiment, copper is selected as the metal material forming the conductor portions such as the wiring pattern layers 10 and 11 or the via conductors 26 and 27, but it is not limited by copper, and may be used. Silver, nickel, gold, copper alloy, iron-nickel alloy, etc. Alternatively, the conductor portion may be formed by a method of applying a conductive resin or the like instead of using a plating layer of a metal. * In the above embodiment, the form of the contact conductors 26 and 27 is a field-connected conductor in which the conductor is completely compensated, and it is of course possible to use an inverted conical shape in which the inside is not completely compensated by the conductor.
I (conformal)連絡導體。 接著’除了於申請專利範圍所揭示之技術性思想之 外，以下列舉根據上述之實施形態所掌握之技術性思想： (1 ) 一種配線基板之製造方法，其特徵係包含：在樹 脂絕緣層之表面形成藉由無電解鑛銅所形成的銅薄膜層的 步驟；將具有耐強驗性而另一方面不具有耐有機胺性之感 光性乾膜材黏貼於§亥銅薄膜層上之後，進行曝光與利用強 驗所導致之顯像’形成既疋圖案之鍍覆阻劑的步·,驟；進行 -18- 200924594 無電解鍍銅而在該鍍覆阻劑之開口部形成配線圖案層的步 驟；使用含有乙醇胺之有機胺系剝離液以剝離該鍍覆阻劑 的步驟；及蝕刻以去除位於該鍍覆阻劑正下方之該銅薄膜 層的步驟。 (2) —種層疊多層配線基板之製造方法，該層疊多層 配線基板係分別於核心基板之表面側與背面側具備層疊 層，其特徵係包含：在樹脂絕緣層之表面形成具有藉由無 電解鍍銅所形成的表面粗糙度Ra爲0.2μηι以上、〇.4μπι以 下粗糙面之銅薄膜層的步驟；將具有耐強鹼性而另一方面 不具有耐有機胺性之感光性乾膜材黏貼於該銅薄膜層上之 後，進行曝光與利用強鹼所導致之顯像，形成既定圖案之 鍍覆阻劑的步驟；進行無電解鍍銅而在該鍍覆阻劑之開口 部形成含有線寬與線間隔皆爲1 5 μιη以下之微細配線圖案 層之配線圖案層的步驟；使用含有單乙醇胺之有機胺系剝 離液以剝離該鍍覆阻劑的步驟：及蝕刻以去除位於該鍍覆 阻劑正下方之該銅薄膜層的步驟。 【圖式簡單說明】 第1圖係顯示具體化本實施形態之一實施形態之配線 基板的部分槪略剖面圖。 第2圖係爲了說明上述配線基板之製程的部分槪略剖 面圖。 第3圖係爲了說明上述配線基板之製程的部分槪略剖 面圖。 第4圖係爲了說明上述配線基板之製程的部分槪略剖 -19- 200924594 面圖。 第5圖係爲了說明上述配線基板之製程的部分槪略剖 面圖。 第6圖係爲了說明上述配線基板之製程的部分槪略剖 面圖。 第7圖係爲了說明上述配線基板之製程的部分槪略剖 面圖。 第8圖係爲了說明上述配線基板之製程的部分槪略剖 面圖。 第9圖係爲了說明上述配線基板之製程的部分槪略剖 面圖。 第1 〇圖係爲了說明上述配線基板之製程的部分槪略 剖面圖。 第1 1圖係爲了說明上述配線基板之製程的部分槪略 剖面圖。 第1 2圖係爲了說明上述配線基板之製程的部分槪略 剖面圖。 第1 3圖係爲了說明上述配線基板之製程的部分槪略 剖面圖。 【主要元件符號說明】 1 核心基板 2 表面 3 背面 4 ' 5 內層配線層 -20 - 200924594 4a、 5 a 銅 箔 6 -g* 穿 孔 形成用孔 7 -eg- 穿 孔 導體 8a、 8b 、 10a、 1 Ob 鍍 銅 膜 9 塡 充 樹 脂 10、11 、28、28a ' 29、 ‘ 29a、34 、34a、35、35a 酉己 線 圖 案層 12、 13、 16、 1 7、30 、3 1 樹 脂 絕 緣層 12a 、1 3 a、18、 19 通 孔 形 成用孔 14、 15 場 連 絡 導體 20 > 2 1 作 爲 金屬層之銅薄膜層 22、 23 乾 膜 材 22a 、2 2 b、2 3a 、2 3b 鍍 覆 阻 劑 24、 24a 、 25 、 25a 鏟 覆 阻 劑之開口部 26、 2 7 連 絡 導 體 2 8a 、29a 配線圖案 層: 之中的微細配線圖; 32、 3 3 阻 焊 劑 32a 第 1 主 面 3 3a 第 2 主 面 36、 3 7 開 □ 部 3 8 焊 錫 凸 塊 K 配 線 基 板 BUI 、BU2 層 疊 層I (conformal) contact conductor. Next, in addition to the technical idea disclosed in the scope of the patent application, the following is a technical idea according to the above embodiments: (1) A method of manufacturing a wiring substrate, comprising: a resin insulating layer a step of forming a copper thin film layer formed by electroless copper ore; and adhering the photosensitive dry film material having strong resistance to the organic amine to the copper film layer; Exposure and development by the use of a strong test 'step of forming a plating resist of the ruthenium pattern, step; -18-200924594 electroless copper plating to form a wiring pattern layer in the opening portion of the plating resist a step of removing the plating resist by using an organic amine-based stripping liquid containing ethanolamine; and etching to remove the copper thin film layer directly under the plating resist. (2) A method of manufacturing a multilayer printed wiring board comprising a laminated layer on a front side and a back side of a core substrate, wherein the laminated insulating layer is formed on the surface of the resin insulating layer by electroless plating a step of forming a copper thin film layer having a surface roughness Ra of 0.2 μm or more and a roughness of less than 4 μm under copper plating; and sticking a photosensitive dry film material having strong alkali resistance and no organic amine resistance on the other hand After the copper thin film layer, a step of exposing and developing by using a strong alkali to form a plating resist of a predetermined pattern; performing electroless copper plating to form a line width in the opening portion of the plating resist a step of patterning a wiring pattern layer of a fine wiring pattern layer having a line spacing of less than 15 μm; using an organic amine-based stripping solution containing monoethanolamine to strip the plating resist: and etching to remove the plating resist The step of the copper film layer directly below the agent. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a portion of a wiring board according to an embodiment of the present embodiment. Fig. 2 is a schematic cross-sectional view showing the process of the wiring board described above. Fig. 3 is a schematic cross-sectional view showing the process of the wiring board described above. Fig. 4 is a partial cross-sectional view showing the process of the wiring board described above, -19-200924594. Fig. 5 is a schematic cross-sectional view showing the process of the wiring board described above. Fig. 6 is a schematic cross-sectional view showing the process of the wiring board described above. Fig. 7 is a schematic cross-sectional view showing the process of the wiring board described above. Fig. 8 is a schematic cross-sectional view showing the process of the wiring board described above. Fig. 9 is a schematic cross-sectional view showing the process of the wiring board described above. Fig. 1 is a schematic cross-sectional view showing a part of the wiring board process. Fig. 1 is a schematic cross-sectional view showing a part of the wiring board process. Fig. 1 is a schematic cross-sectional view showing a part of the wiring board process. Fig. 1 is a schematic cross-sectional view showing a part of the wiring board process. [Description of main component symbols] 1 Core substrate 2 Surface 3 Back surface 4' 5 Inner wiring layer-20 - 200924594 4a, 5 a Copper foil 6 - g* Perforation forming hole 7 -eg - Perforated conductors 8a, 8b, 10a, 1 Ob copper plating film 9 enamel resin 10, 11, 28, 28a '29, '29a, 34, 34a, 35, 35a 酉 line pattern layer 12, 13, 16, 1 7, 30, 3 1 resin insulating layer 12a, 1 3 a, 18, 19 through hole forming holes 14, 15 field contact conductors 20 > 2 1 as a metal layer of copper film layers 22, 23 dry film materials 22a, 2 2 b, 2 3a, 2 3b plating Resistors 24, 24a, 25, 25a Scrape resist opening 26, 2 7 contact conductors 28a, 29a Wiring pattern among wiring pattern layers: 32, 3 3 Solder resist 32a 1st main surface 3 3a 2nd main surface 36, 3 7 opening □ part 3 8 solder bump K wiring board BUI, BU2 layer