JP5359821B2 - Manufacturing method of build-up wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a build-up wiring board having a narrow gap pattern that reduces fault occurrence ratio by separating a dry film resist without a failure. <P>SOLUTION: At a step of separating the dry film resists in the process of manufacturing a buildup wiring substrate according to a semi-additive method, an electromagnetic induction coil for enclosing a transfer portion of a buildup wiring substrate 51 is formed to ensure that an insulating-coated conductor 61 for flowing high-frequency current reciprocates for many times between cores of an upper transfer roll 71 and a lower transfer roll 72. After a separation fluid is sprayed into the buildup wiring substrate, the buildup wiring substrate is transferred into the electromagnetic induction coil to which high-frequency current is applied, thus vibrating a copper wiring layer and an electrolytic copper plating layer, and facilitating the separation of the dry film resist. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a build-up wiring board that can provide a build-up wiring board having a narrow gap conductor pattern with an interval between conductor wirings of 15 μm or less at low cost.

In recent years, in response to demands for higher functionality, miniaturization, weight reduction, and the like for electronic devices, there are increasing demands for higher density and thinner thickness for multilayer printed wiring boards incorporated therein. One of the construction methods of the multilayer printed wiring board corresponding to these requirements is a build-up construction method. In this method, a multilayer printed wiring board is manufactured by overlapping a thermosetting insulating resin layer and a conductor wiring layer. Hereinafter, the multilayer printed wiring board manufactured by the build-up method is referred to as a build-up wiring board.
In this manufacturing method of the build-up wiring board, further narrowing of the conductor wiring is required. For example, in the rule of the conductor wiring pitch of 30 μm, the conductor wiring width / conductor gap width (hereinafter referred to as line / space) is 15/15 μm. A conductor wiring gap width of 15 μm, which is half the conductor wiring pitch, is required, as in the case of the conductor pattern.

As a method for forming a narrow-pitch conductor pattern having a conductor wiring pitch of 100 μm or less, a semi-additive method is generally employed. In the semi-additive method, a copper foil layer having a thickness of about 1 μm without a conductor pattern called a seed layer is formed on an insulating resin layer. Next, a dry film resist is laminated on the seed layer, and a desired pattern shape is exposed and developed to form a dry film resist pattern in which the seed layer is exposed in a desired conductor pattern. Furthermore, electrolytic copper plating is performed while feeding the seed layer. Next, after the dry film resist is peeled off, a part of the seed layer exposed at the bottom of the conductor pattern formed by electrolytic copper plating is etched to form an independent conductor pattern.
The semi-additive method is a method suitable for narrow-pitch conductor patterns because it has a smaller conductor width than the subtractive method.

  Here, a negative dry film resist generally used in a build-up wiring board will be described. When the dry film resist is exposed to light, the photopolymerization initiator radically polymerizes the binder polymer and the monomer to crosslink three-dimensionally. The exposed and three-dimensionally cross-linked portion exhibits hydrophobicity, and a weak alkaline solution such as an aqueous sodium carbonate solution does not penetrate, so it does not dissolve in the sodium carbonate solution, and a desired pattern is formed by a dry film resist. .

  To remove a three-dimensionally cross-linked dry film resist that cannot be dissolved in a sodium carbonate solution after electrolytic copper plating, it is brought into contact with a strong alkaline sodium hydroxide aqueous solution, and the carboxylic acid groups and sodium hydroxide in the dry film resist are contacted. As a result of the neutralization reaction, a salt is formed and becomes hydrophilic, and the release liquid is absorbed and swollen in the three-dimensionally cross-linked dry film resist, causing mechanical distortion due to the volume expansion of the dry film resist and peeling. doing.

JP 2003-204138 A JP 2003-298205 A

In recent years, in the multilayer printed circuit board market, it has been required to reduce the pitch of conductor patterns as described above. In the manufacturing process of a build-up wiring board having a conductor pattern with a gap between conductor wires of 15 μm or less, the dry film resist peeling residue masks the etching of the seed layer, causing a problem of wiring failure due to a short circuit. It's getting easier.
This is due to the fact that the high-strength material is designed so that it does not fall down even if the dry film resist becomes thinner in order to narrow the gap between copper wirings in order to achieve high-density wiring. is there. For example, the binder polymer is further polymerized, and the amount of the photopolymerizable monomer is increased. For this reason, since the relative content of carboxylic acid groups decreases and the amount of dry film resist that absorbs and swells the stripping solution is small, the amount of mechanical strain decreases, making it difficult to strip.

  The dry film resist with high cross-linking density that can form a narrow pattern in this way has reduced penetration of weakly alkaline developer and stripper, and swelled and stripped with a conventionally used sodium hydroxide solution Then, peeling failure occurred frequently, and it became impossible to supply an inexpensive product to the market.

  In general, if the gap between conductor wirings is a narrow gap of 15 μm or less, the dry film resist pattern has a high aspect ratio of 1 to less than 5 in the pattern width and height of the dry film resist. The thickness of the dry film resist is reduced or the thickness of the electrolytic copper plating is reduced so that the peelability does not deteriorate. However, this method has a problem that the wiring width is reduced and the wiring height is also lowered, resulting in an increase in resistance as a conductor.

  The present invention has been made in view of the above-described problems of the background art, and an object thereof is a build-up wiring having a narrow gap pattern in which the thickness of the electrolytic copper plating is 15 μm or more and the gap between the conductor wirings is 15 μm or less. An object of the present invention is to provide a method for manufacturing a build-up wiring board that leads to a reduction in the occurrence of defects by allowing a dry film resist to be peeled without peeling defects in a semi-additive method of substrate.

  In order to solve the above-mentioned problems, the invention according to claim 1 is a method for manufacturing a build-up wiring board having a fine conductor wiring pattern with a narrow gap, and a conductor wiring layer having a pattern shape on both sides or one side of a core layer. Forming an insulating resin layer having via holes on both sides or one side of the core layer on which the conductor wiring layer is formed, covering the conductor wiring layer and the core layer, and the insulating resin layer Forming a seed layer having no conductor pattern on the surface opposite to the core layer, forming a resist pattern on the surface of the seed layer opposite to the core layer, and the resist pattern A step of forming the fine conductor wiring pattern on a non-formed portion of the shape, and a resist for peeling the resist constituting the resist pattern shape from the laminate obtained by the step A peeling step and an etching step for etching the seed layer in a portion where the fine conductor wiring pattern is not formed. The resist peeling in the resist peeling step is performed by applying a stripping solution to the laminate. The method is characterized in that a high-frequency vibration is applied to the conductor of the conductor wiring layer or the fine conductor wiring pattern by passing through an electromagnetic induction coil to which a high-frequency current is applied, and a mechanical vibration force is applied.

  In the invention according to claim 2, the frequency of the applied high-frequency current is 20 to 50 kHz when the thickness of the fine conductor wiring is 15 μm or more and the interval between the adjacent fine conductor wirings is 15 μm or less. It is characterized by being.

  The invention according to claim 3 is characterized in that, in the resist stripping step, the conductor wiring layer is locally overheated by dielectrically heating the conductor wiring layer by applying a high frequency current to an electromagnetic induction coil. .

According to the present invention, in a semi-additive construction method of a build-up wiring board having a narrow gap pattern with a conductor wiring gap of 15 μm or less, the build-up can be peeled off without a dry film resist peeling residue, thereby reducing the occurrence rate of peeling defects. A method for manufacturing a wiring board can be provided.
In addition, it is expected to improve the releasability of dry film resists with narrow gap patterns, so there is no need to switch to thin film resists with thin film thickness, and electrolytic copper plating thickness can be formed according to the conventional wiring thickness rule even if it becomes fine wiring A method for manufacturing a build-up wiring board can be provided.

It is explanatory drawing which shows one Example of the manufacturing method of the buildup wiring board of this invention. It is a perspective view which shows the example of installation of the electromagnetic induction coil which concerns on this invention. It is sectional drawing cut | disconnected by the surface parallel to a board | substrate conveyance direction which shows the electromagnetic induction coil installation example shown in FIG.

  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS With reference to the accompanying drawings, the best mode for improving dry film resist peelability by electromagnetic induction according to the present invention will be described in detail below.

FIG. 1 is an explanatory view showing a process of forming a wiring in one embodiment of a method for manufacturing a buildup wiring board according to the present invention.
First, the copper wiring layer 12 having a desired pattern shape is formed on one side or both sides of the core layer 11. Here, the copper wiring layer 12 corresponds to the conductor wiring layer in claims 1 and 3.
Then, an insulating resin is applied on the core layer 11 on which the copper wiring layer 12 is formed, vacuum lamination is performed at a temperature of about 120 ° C., and post baking is performed at a high temperature to form the insulating resin layer 21 (step A). ). Here, through holes are not shown in the core layer 11 for convenience, but through hole copper wirings that penetrate the core layer 11 may be formed as necessary.

  Next, a via hole 22 having a diameter of about 50 μm is formed in the insulating resin 21 with a laser drill so as to reach the copper wiring layer 12. Thereafter, desmear treatment is performed in order to remove smear generated by the laser drill (step B).

Then, the electroless copper plating layer 31 without a 1 μm-thick conductor pattern is formed by electroless copper plating (step C).
The electroless copper plating layer 31 is a layer called a seed layer in the conventional semi-additive method, and is fed onto the electroless copper plating layer 31 by supplying power to the electroless copper plating layer 31 in a later step E. This is for performing electrolytic copper plating of the pattern.

Next, a dry film resist is laminated on the electroless copper plating layer 31. The dry electrophotographic copper plating layer 31 is exposed in a desired pattern shape as a final conductor pattern by the procedure described below. A resist pattern shape 41 of a film resist is formed (process D).
The dry film resist is, for example, a photosensitive resin layer having a thickness of about 25 μm sandwiched between a support film and a protective layer, and the support film is removed while peeling off the dry film resist protective layer from the electroless copper plating layer 31. The substrate is laminated on the substrate at a roll temperature of about 120 ° C. by a hot roll laminator toward the side opposite to the core layer 11. Thereafter, a photomask having a desired pattern is placed on the support film side of the dry film resist, and exposure is performed from above the photomask to obtain a dry film resist having a cured resist pattern. Next, the support film is peeled off, and the base material is dipped in an aqueous Na2CO3 solution and developed to obtain a resist pattern shape 41 having a desired resist pattern.

Next, the electroless copper plating layer 42 is formed by supplying power to the electroless copper plating layer 31 on the electroless copper plating 31 exposed from the gap between the formed resist pattern shapes 41. (Process E).
Here, the electrolytic copper plating layer 42 corresponds to the fine conductor wiring pattern in claims 1 and 2. That is, the electrolytic copper plating layer 42 constitutes a conductor pattern having a gap between wirings of 15 μm or less.

After the electrolytic copper plating layer 42 is formed, the dry film resist is peeled off (step F). The present invention is characterized by this peeling method.
The peeling method will be described with reference to FIGS.

FIG. 2 is a perspective view showing a transport unit that can supply a high-frequency current through the electromagnetic induction coil through the substrate created by the steps A to E in the present embodiment.
In FIG. 2, the electromagnetic induction coil that surrounds the transport portion of the build-up wiring board 51 so that the conductor 61 with an insulation coating for flowing a high-frequency current reciprocates the cores of the upper transport roll 71 and the lower transport roll 72 many times. Is forming. FIG. 2 shows a simple four-round state. The electromagnetic induction coil is a core material of the transport rolls 71 and 72, but has a structure independent of the transport rotation of the transport roll. Moreover, the surface of the conveyance rolls 71 and 72 is coated with olefin rubber, and has a structure that does not damage the conveyance of the build-up wiring board 51.

FIG. 3 is a cross-sectional image diagram of the transport unit of FIG. 2 cut along a plane parallel to the transport direction of the substrate.
In FIG. 3, a spray nozzle 81 for the stripping liquid is arranged between adjacent transport rolls, and the stripping liquid 82 is sprayed on the upper and lower surfaces of the build-up wiring board 51, so that a high frequency current is applied to the transport roll. Then, the axis of the upper and lower transport rolls becomes an electromagnetic induction coil, and vibrates the copper wiring layer 12 of the buildup wiring board 51. The electromagnetic force acting between the induction coil and the copper wiring layer 12 is dominated by the electromagnetic repulsion force generated between the current flowing through the induction coil and the induction current induced in the copper wiring layer 12. This electromagnetic repulsive force acts on the entire build-up wiring board.

As a result, the copper wiring layer 12 vibrates at a specific resonance frequency that depends on the shape of the copper wiring pattern. This resonance frequency is twice the current frequency or current harmonic flowing in the induction coil. Since this doubled frequency is in the ultrasonic frequency band, ultrasonic vibration is generated in the build-up wiring board 51.
The mechanical movement by the ultrasonic vibration contributes to the improvement of the peelability of the resist pattern shape 41, but the cavitation of the stripping solution induced by this vibration further contributes to the improvement of the peelability.

The high-frequency current used here is preferably 20 to 50 kHz as described in claim 2. In this frequency band, cavitation tends to occur in the stripping solution, and it tends to stay in a narrow space where the aspect ratio of the wiring adjacent to the electrolytic copper plating layer 42 is 1 or more. The cavitation generated in the stripping solution has an effect that the dry film resist is physically easily peeled off by an impact generated when the cavity disappears near the surface of the resist pattern shape 41.
Further, when the stripping solution penetrates into the part where peeling has started and cavitation occurs, the cavitation cavity repeatedly expands and contracts at the interface between the copper wiring layer 12 and the dry film resist, so that the physical property that causes the dry film resist to rise Force is generated. This physical force expands from the microscopic part that begins to peel off and floats so as to widen the gap at the interface between the copper wiring layer 12 and the dry film resist, which is effective in improving the peeling speed of the dry film resist. is there.

  In general, dielectric heating uses a high-frequency power source in the vicinity of 22.5 kHz, but there is no problem if the high-frequency power source uses 20 to 50 kHz. By applying such a high-frequency current to the electromagnetic induction coil, as described in claim 3, the copper wiring layer 12 is dielectrically heated, and the stripping solution temperature rises at the contact interface between the copper wiring layer 12 and the dry film resist, It can contribute to the improvement of the penetration rate of dry film resist.

  After the dry film resist is peeled off by the above method, the electroless copper plating layer 31 exposed at the bottom of the conductor pattern formed by the electrolytic copper plating layer 42 is etched to form an independent conductor pattern (step G). ).

  Manufacturing a build-up wiring board having a narrow gap pattern in which the dry film resist can be peeled without peeling defects and the thickness of the conductor wiring is 15 μm or more and the gap is 15 μm or less by the process of the semi-additive method described above. Can do.

<Example 1>
A method of manufacturing a conductor pattern with a pitch of 30 μm and L / S = 15/15 μm will be described with reference to FIG.
First, ABF GX-13 (trade name, manufactured by Azinomoto Fine Techno Co., Ltd.) as an insulating resin is vacuum-laminated at a laminating temperature of 120 ° C. on the copper wiring layer 12 formed in the core layer 11, and then post-processed at 180 ° C. The insulating resin layer 21 was obtained by baking (Step A). Next, a via hole 22 having a diameter of 50 μm was formed in the insulating resin layer 21 with a laser drill, and then desmear treatment was performed in order to remove smear generated by the laser drill (step B).

Further, an electroless copper plating layer 31 having a thickness of 1 μm was formed by electroless copper plating (step C).
Further, Sunfort (registered trademark) UFG-255 (trade name, manufactured by Asahi Kasei Electronics Co., Ltd.) was used as a dry film resist. This uses a polyethylene terephthalate film as the support film and a polyethylene film as the protective layer, and the photosensitive resin layer thickness is 25 μm.
The electroless copper plating layer 31 having a thickness of 1 μm was laminated on a substrate at a roll temperature of 120 ° C. with a hot roll laminator (Asahi Kasei Co., Ltd., AL-70) while peeling the protective layer of the dry film resist. The air pressure was 0.3 MPa, and the laminating speed was 1.0 m / min.

A photomask having a pattern of L / S = 22/8 μm is placed on the support film side of the dry film resist, and exposed at an exposure amount of 120 mJ / cm 2 with an ultra-high pressure mercury lamp (OMW Seisakusho, HMW-201KB). A dry film resist having a cured resist pattern was obtained. Next, the support film is peeled off and the substrate is developed by immersing in a 1% by mass Na2CO3 aqueous solution at 30 ° C. for 50 seconds to form a resist pattern shape 41 having an 8 μm wide resist pattern adjacent to a 22 μm wide gap. Obtained (step D).
Next, electrolytic copper plating was performed on the electroless copper plating portion exposed from the 22 μm wide gap to form an electrolytic copper plating layer 42 having a thickness of 20 μm (step E).

Here, a 3% by mass NaOH aqueous solution was prepared as a dry film resist stripping solution. While spraying at 50 ° C. and a pressure of 0.2 MPa, the build-up wiring board 51 is inserted into the induction coil shown in FIGS. 2 and 3, sprayed for 60 seconds from the spray nozzle 81, and a high frequency current is applied to form a resist pattern. After peeling, the film was washed with water and dried to complete the peeling of the dry film resist. (Process F).
Here, the dry film resist peeling was completed using a high frequency power source of 40 kHz.
As a result, it was possible to peel off the dry film resist without peeling failure, and it was possible to manufacture a build-up wiring board having a conductor pattern of L / S = 15/15 μm at a pitch of 30 μm.

<Comparative Example 1>
The process up to Step E for electrolytic copper plating was performed on the base material in the same manner as in Example 1.
Here, a 3 wt% NaOH aqueous solution was prepared as a dry film resist stripping solution. Next, the substrate was put into an in-line spray filming apparatus and sprayed at 300C at a pressure of 0.3 MPa for 300 seconds. Although a cured resist pattern of 13 μm or more (photomask pattern size L / S = 27/13 μm) could be peeled off, a resist pattern having a width of 8 μm (photomask pattern size L / S = 32/8 μm) was obtained by electrolytic copper plating layer 42. With the dry film resist still sandwiched between the two, it was not possible to peel off well.

  INDUSTRIAL APPLICABILITY The present invention can be used in a method for manufacturing a build-up wiring board having fine wiring with a narrow gap, reduces the frequency of occurrence of defective products due to defective peeling of a dry film resist, increases product reliability, and is inexpensive. New products can be supplied to the market.

DESCRIPTION OF SYMBOLS 11 Core layer 12 Copper wiring layer 21 Insulating resin layer 22 Laser via hole 31 formed in the insulating resin layer Electroless copper plating layer 41 Resist pattern shape 42 formed by dry film resist Electrolytic copper plating layer 51 Build-up wiring board 61 Electromagnetic induction Coil 71 Upper transport roll 72 Lower transport roll 81 Spray nozzle 82 Stripping solution

Claims (3)

A manufacturing method of a build-up wiring board having a fine conductor wiring pattern with a narrow gap,
Forming a conductive wiring layer having a pattern shape on both sides or one side of the core layer;
Forming an insulating resin layer having via holes on both sides or one side of the core layer on which the conductor wiring layer is formed so as to cover the conductor wiring layer and the core layer;
Forming a seed layer having no conductor pattern on the surface of the insulating resin layer opposite to the core layer;
Forming a resist pattern shape on the surface of the seed layer opposite to the core layer;
Forming the fine conductor wiring pattern in a non-formed portion of the resist pattern shape;
A resist stripping step of stripping the resist constituting the resist pattern shape from the laminate obtained by the above steps;
An etching step of etching the seed layer in a portion where the fine conductor wiring pattern is not formed;
The resist stripping in the resist stripping step is performed by passing the layered product coated with a stripping solution through an electromagnetic induction coil to which a high-frequency current is applied, so that the conductor wiring layer or the fine conductor wiring pattern can be removed. This is done by vibrating the conductor at high frequency and applying mechanical vibration force.
A method for manufacturing a build-up wiring board.   The frequency of the high-frequency current to be applied is 20 to 50 kHz when the thickness of the fine conductor wiring is 15 μm or more and the interval between the adjacent fine conductor wirings is 15 μm or less. The manufacturing method of the build-up wiring board of description.   2. The buildup wiring board according to claim 1, wherein in the resist stripping step, the copper wiring layer is locally overheated by subjecting the conductor wiring layer to dielectric heating by applying a high frequency current to an electromagnetic induction coil. 3. Manufacturing method.

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