JP2013206958A - Printed wiring board and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a printed wiring board which, by realizing thinning of a first metal film in a wiring portion and formation of a metal film with excellent covering around via holes, restrains reduction in electrical characteristic and reduction in reliability due to ion residues and also can secure the reliability of electrical connection between wiring layers.SOLUTION: A first resist film 8 is formed so as to cover a first metal film 7 to be deposited in a via hole 4, and a first metal coat to be formed in an insulation layer other than the via hole is etched to make the first metal coat to be formed in an insulation layer other than the via hole thinner than the first metal film to be formed in the via hole, in which way a first thinned metal film 9 is formed.

Description

  The present invention relates to a printed wiring board and a manufacturing method thereof.

  Printed wiring boards are widely used for mounting electronic components, semiconductor elements, and the like. With recent demands for downsizing and higher functionality of electronic devices, printed wiring boards are desired to have higher circuit density and thickness.

  As a method for manufacturing this high-density printed wiring board, a multilayer build-up wiring board using a build-up method is known. In this method, a multilayer build-up is performed by repeating the steps of forming an insulating layer on a core layer having a wiring layer formed on an insulating substrate, further forming a wiring layer thereon, and further forming an insulating layer. A wiring board is formed.

  A conventional method for manufacturing a printed wiring board will be described with reference to the drawings, taking a multilayer build-up wiring board as an example. 5 and 6 are schematic sectional views showing an example of a conventional method for manufacturing a printed wiring board.

  First, a layer serving as a base of a build-up wiring board generally called a core layer will be described. As shown in FIG. 5 (a), a through hole 22 is formed in a double-sided copper-clad substrate 21 made of a rigid material such as a glass epoxy substrate using a drill or a laser, and immersed in a high-pressure cleaning or permanganate bath. Thus, the resin residue in the hole is removed. Next, electroless copper plating and electrolytic copper plating are performed to form a copper film 23 on the substrate surface and in the through holes. After the through-hole 22 covered with the copper film 23 is filled with the hole-filling ink 24 by screen printing, excess resin protruding to the surface is removed by polishing such as buffing.

  Next, as shown in FIG. 5B, after a photosensitive photoresist is applied to the entire surface of the substrate, a resist pattern 25 is formed by photolithography.

  Next, as shown in FIG. 5C, the copper film portion not covered with the resist pattern 25 is removed using an etching solution such as cupric chloride solution, and the resist pattern 25 is further peeled off. A first wiring layer 26 is formed. These are generally called the core layer 27.

  Next, the buildup layer formed on the upper and lower layers of the core layer 27 will be described. After the surface of the wiring layer of the core layer 27 is roughened, as shown in FIG. 6D, a sheet-like insulating resin is adhered to form the insulating layer 28. In forming the insulating layer 28, a method of adhering a sheet-like resin is preferable from the viewpoint of easily forming a resin layer having a uniform thickness, but a method of applying a liquid resin may also be used. As a material of the insulating layer 28, an epoxy resin, a polyimide resin, or the like is used.

  Next, a via hole 29 reaching the first wiring layer 26 from the surface of the insulating layer 28 is formed by laser irradiation. A laser such as a UV laser, a carbon dioxide laser, or an excimer laser is used as the laser. Then, the surface of the insulating layer 28 is roughened and the inside of the via hole 29 is cleaned by being immersed in a permanganate bath. Since the via hole 29 serves as a via for electrically connecting the upper and lower wiring layers, the size and shape of the hole are very important from the viewpoint of high density and high reliability.

  Next, the formation of the wiring layer of the buildup layer will be described. The wiring layer can be formed by a subtractive method in which a wiring pattern is formed by etching and an additive method in which a wiring pattern is formed by plating. Further, the additive method is divided into a full additive method in which a wiring pattern is formed by electroless plating and a semi-additive method in which a wiring pattern is formed by electrolytic plating. Since the semi-additive method is generally applied to high-density substrates, the semi-additive method will be described.

  Next, as shown in FIG. 6E, the surface of the insulating layer 28 and the inside of the via hole 29 are roughened with a permanganate bath, subjected to desmear treatment, and then subjected to electroless copper plating to form a copper film 30. Form. The formation of the copper film 30 is performed in order to impart conductivity to the surface of the insulating layer 28 and enable electrolytic copper plating. Next, a photosensitive photoresist is applied to the entire surface of the substrate. As the photosensitive photoresist, a dry film type having excellent thickness uniformity is often used. Then, a resist pattern 31 is formed by photolithography. Then, by electrolytic plating, a copper film 32 is formed in a portion not covered with the resist pattern 31 to form a wiring pattern, and plating is also performed on the via hole 29 that is opened to make an electrical connection between the upper and lower layers. As a result, the via 33 is formed. The via includes a conformal via in which the hole wall is coated with plating and a filled via in which the entire hole is filled with plating. The type of via can be properly selected by selecting the composition of the plating solution and the additive. In recent years, filled bi is often used to obtain a stacked via structure that is advantageous for high density. The filled via may be filled with a conductive paste in addition to filling the hole with plating as described above. In this example, a filled via structure embedded by plating is shown.

  Next, as shown in FIG. 6F, after the resist pattern 31 is peeled off with an alkaline aqueous solution such as NaOH, the exposed electroless plating film 30 is dissolved and removed with an aqueous solution of hydrogen peroxide / sulfuric acid. Thus, the second wiring layer 34 is formed.

Japanese Patent Publication No. 7-105600

  Patent Document 1 discloses a technique similar to the manufacturing method of the multilayer build-up wiring board described above. The following problems are cited as problems of the prior art in Patent Document 1. That is, a plurality of wiring layers are formed on an insulating substrate via an insulating layer, and a multilayer printed wiring board in which the wiring layers are electrically connected by filled vias or a core substrate on which through holes are formed. In a multilayer build-up wiring board in which a plurality of wiring layers are formed on both surfaces via an insulating layer and the wiring layers are electrically connected by filled vias, a build-up wiring layer is formed by a semi-additive method In this case, there was a problem of side etching that the circuit (second metal film on the first metal film) was thinned when removing the first metal film on the insulating layer. This problem causes a reduction in reliability due to ionic residues of etching on the surface and side of the circuit as well as degradation of electrical properties. In order to reduce this circuit thinning, it is effective to thin the first metal film.

  That is, in Patent Document 1, the first metal film is thinned in order to solve the problem of circuit thinning of wiring due to side etching that occurs in the etching process in the printed wiring board manufacturing method. However, the thinning of the first metal film in the via portion causes a deterioration in via connection.

  This is because the thinning of the first metal film deteriorates the contact of the first metal film to the via hole. Deterioration of the contact of the first metal film to the via hole causes a crack at the connection interface between the first metal film and the via formed on the first metal film, resulting in a problem that electrical connection between the upper and lower layers cannot be secured. There is a fear.

  In view of the above problems, the present invention realizes the first metal film thinning of the wiring portion and the first metal film formation around the via hole, thereby reducing the electrical characteristics and the reliability due to the ion residue. It is an object of the present invention to provide a printed wiring board and a method of manufacturing the printed wiring board that can prevent deterioration in electrical performance and ensure electrical connection reliability between wiring layers.

  The printed wiring board and the method for manufacturing the same according to the present invention are formed by forming a first resist film 8 so as to cover the first metal film 7 formed in the via hole 4 and forming it on the insulating layer 3 other than the via hole 4. By etching the one metal film 7, the first metal film 7 formed on the insulating layer 3 other than the via hole 4 is made thinner than the first metal film 7 formed on the via hole 4, and the first thinned metal A film 9 is formed.

  According to the present invention, by reducing the thickness of the first metal film in the wiring portion and forming the first metal film on the via hole, it is possible to suppress deterioration in electrical characteristics and reliability due to ion residues. A printed wiring board capable of ensuring electrical connection reliability between wiring layers can be obtained.

Schematic sectional view showing an example of a method for manufacturing a printed wiring board according to the present invention in the order of steps Typical sectional drawing which shows an example of the manufacturing method of the printed wiring board concerning this invention in order of a process following (d) of FIG. Typical sectional drawing which shows an example of the manufacturing method of the printed wiring board which concerns on this invention in order of a process following (h) of FIG. Typical sectional drawing which shows an example of the manufacturing method of the printed wiring board which concerns on this invention in order of a process following (k) of FIG. Typical sectional drawing which shows the manufacturing method of the conventional printed wiring board in process order Typical sectional drawing which shows the manufacturing method of the conventional printed wiring board in order of a process following (c) of FIG.

  Hereinafter, the manufacturing method of the printed wiring board concerning the present invention is explained based on a drawing. FIG. 1 is a schematic cross-sectional view illustrating an example of a method for producing a printed wiring board according to the present invention in the order of steps. 2 to 4 are schematic cross-sectional views sequentially showing processes subsequent to (d) of FIG.

Here, the manufacturing method of the multilayer buildup wiring board using the semi-additive method is demonstrated as an example of the manufacturing method of the printed wiring board concerning this invention.
First, as shown in FIG. 1A, the core substrate is the insulating substrate 1, the first wiring layer 2 is formed on the insulating substrate 1, the surface of the first wiring layer 2 and the surface of the insulating substrate 1. That in which the insulating layer 3 is formed so as to cover is manufactured. The insulating substrate 1 may be a rigid substrate, a flexible substrate, or a tape substrate. The insulating layer 3 is not particularly limited as long as it has insulating properties, and examples thereof include a liquid or sheet-like insulating resin. For example, as such a material, specifically, there are thermosetting resins such as epoxy resin, phenol resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, and the like.

  In the example shown in FIGS. 1 to 4, a multilayer build-up wiring board in which a plurality of wiring layers are formed on one side of the core substrate via the insulating layer 3 is manufactured. However, a multilayer build-up wiring board in which a plurality of wiring layers are formed on both surfaces of the core substrate on which the through holes are formed via insulating layers may be manufactured.

  Next, as shown in FIG. 1B, a via hole 4 is formed in the insulating substrate 1 with a laser. Examples of the laser include a UV laser, a carbon dioxide laser, and an excimer laser. When the via hole 4 is opened, a smear 5 is generated in the via hole 4.

  Next, as shown in FIG. 1C, the smear 5 in the via hole 4 is removed. Examples of the method for removing smear 5 include a method of removing smear 5 by immersing it in a solution that can be dissolved. Specifically, for example, there is a method of bringing the potassium permanganate solution or the sodium permanganate solution into contact with the insulating layer 3 by spraying or dipping.

  Next, as shown in FIG. 1 (d), a plating catalyst 6 is applied to the entire surface of the insulating layer 3 and the via holes 4. The plating catalyst 6 is not particularly limited as long as it functions as a catalyst for electroless plating such as copper or nickel. By depositing metal around the plating catalyst 6 to connect the plating catalysts 6 to form a metal film on the insulating portion, or by depositing on the insulating portion, the surface of the insulating portion is given conductivity. Examples thereof include those having conductivity, which is used in a method generally called direct plating (direct plating), in which a metal film is formed on an insulating portion by using. Examples of the plating catalyst 6 include those containing palladium, those containing palladium and tin, those containing carbon such as carbon and graphite, those containing a complex of copper, and containing a conductive polymer. And the like.

  Next, as shown in FIG. 2E, a first metal film 7 is formed on the entire surface of the insulating layer 3 and the via hole 4. It is preferable that the first metal film 7 is sufficiently formed with respect to the entire surface of the insulating layer 3 and the via hole 4 so that the insulating layer 3 is not exposed and has a small thickness. For example, examples of the method for forming the first metal film 7 include electroless plating and sputtering. The first metal film 7 is preferably copper because it needs to be easily etched and conductive in a later step.

  Next, as shown in FIG. 2 (f), a first resist film 8 is formed so as to cover the via hole 4 in the surface of the first metal film 7. As shown in FIG. 2G, the first resist film 8 is not particularly limited as long as it can withstand a removing liquid (etching liquid) for thinning the first metal film 7, for example, And a liquid photosensitive resin or a sheet-like photosensitive film.

  Next, as shown in FIG. 2G, the exposed first metal film 7 is thinned by etching so that the insulating layer 3 is not exposed to form a first thinned metal film 9. Examples of the method of forming the first thin metal film 9 by etching the first metal film 7 include a method of immersing the first metal film 7 in a solution that can be dissolved. Specifically, for example, there is a method in which an aqueous solution such as hydrogen peroxide / sulfuric acid is brought into contact with the first metal film 7 by spraying or dipping.

  Next, as shown in FIG. 2H, the first resist film 8 is removed. Examples of the removing solution for removing the first resist film 8 include alkali or solvent-type stripping solutions.

  Next, as shown in FIG. 3 (i), the surface of the first metal film 7 and the first thinned metal film 9 except for the part where the circuit and via 11 are scheduled to be formed A resist film 10 is formed.

  As shown in FIG. 3 (j), the second resist film 10 can withstand a plating solution for forming the second metal film 12, and when this plating is performed, the second metal film 12 is hardly formed on the surface. If it is a thing, it will not specifically limit, For example, a liquid photosensitive resin or a sheet-like photosensitive film etc. are mentioned.

  Next, as shown in FIG. 3J, the second metal film 12 is formed on the surface of the portion where the first metal film 7 and the first thinned metal film 9 are exposed. Examples of the method for forming the second metal film 12 include electrolytic plating and electroless plating. The thickness of the second metal film 12 needs to be smaller than the thickness of the second resist film 10. This is because, when the second resist film 10 is removed as shown in FIG. 1 (k), if the second resist film 10 is thicker than the second metal film 12, the second resist film 10 is difficult to remove. It is.

  Next, as shown in FIG. 3K, the second resist film 10 is removed. Examples of the removing solution for removing the second resist film 10 include alkali or solvent-type stripping solutions.

  Next, as shown in FIG. 4L, unnecessary portions of the first thin metal film 9 are removed by etching. Examples of the method for removing the unnecessary portion by etching the first thinned metal film 9 include a method of immersing the first thinned metal film 9 in a solution that can be dissolved. Specifically, for example, there is a method in which an aqueous solution such as hydrogen peroxide / sulfuric acid is brought into contact with the first thin metal film 9 by spraying or dipping.

Next, as shown in FIG. 4M, the plating catalyst 2 remaining on the surface of the insulating layer 3 is removed. If the plating catalyst 6 remaining on the surface of the insulating layer 3 is removed, the insulation between the circuits is improved, so that a printed wiring board having particularly high reliability is preferable. Examples of the method for removing the plating catalyst 6 remaining on the surface of the insulating layer 3 include a method of removing the plating catalyst 6 by immersing it in a solution that can be dissolved. Specifically, for example, there is a method of bringing the potassium permanganate solution or the sodium permanganate solution into contact with the insulating layer 3 by spraying or dipping.
Through the above steps, the printed wiring board according to the present invention is obtained (see FIG. 4M).

In the printed wiring board manufacturing method according to the above embodiment, the first resist film 8 is formed so as to cover the first metal film 7 formed in the via hole 4, and is formed on the insulating layer 3 other than the via hole 4. The first metal film 7 formed on the insulating layer 3 other than the via hole 4 is made thinner than the first metal film 7 formed on the via hole 4 by etching the first metal film 7 to be formed. Although the film 9 is formed, it may be as follows in other embodiments.
For example, the first resist film 8 is formed so as to cover the first metal film 7 formed in the via hole 4 and the first metal film 7 formed around (in the vicinity of) the via hole 4, and the via hole 4 and the via hole 4 are formed. The first metal film 7 formed on the insulating layer 3 other than the periphery is etched to form the first metal film 7 formed on the insulating layer 3 other than the via hole 4 and the periphery of the via hole 4. The first thin metal film 9 may be formed thinner than the first metal film 7 formed on the peripheral insulating layer 3.

<Example 1>
Embodiments of the present invention will be described below with reference to the drawings.
First, as shown in FIG. 1A, a first wiring layer 2 is formed on an insulating substrate 1, and a film-like insulating resin is laminated on the formed first wiring layer 2 and the insulating substrate 1 to obtain 35 um. A thick insulating resin layer (insulating layer) 3 was formed. Next, as shown in FIG. 1B, a via hole 4 having a diameter of 40 μm was formed in the insulating resin layer 3 with a UV laser. Next, as shown in FIG. 1C, the smear 5 was removed with a potassium permanganate solution. Next, an electroless plating catalyst 6 was applied as shown in FIG. Next, as shown in FIG. 2E, an electroless copper plating layer (first metal film) 7 was formed to a thickness of 2.0 μm by electroless copper plating. Next, as shown in FIG. 2 (f), a surface of the electroless copper plating layer 7 is covered with a dry film resist having a thickness of 25 μm, and a resist pattern (φ60 μm is formed so as to cover the via hole 4 by exposure and development. First resist film 8) was formed. Next, as shown in FIG. 2G, the electroless copper plating layer 7 not covered with the formed resist pattern 8 was thinned to 0.4 μm using a hydrogen peroxide / sulfuric acid based etching solution. Next, as shown in FIG. 2H, the resist pattern 8 was peeled off. Next, as shown in FIG. 3 (i), the surface of the thinned electroless copper plating layer (first thinned metal film) 9 is covered with a dry film resist having a thickness of 25 μm, and the line is formed by exposure and development. A resist pattern (second resist film) 10 having a space of 10/10 μm was formed. Next, as shown in FIG. 1 (j), electrolytic copper plating is performed using a copper sulfate bath to form an electrolytic copper plating layer (second metal film) 12 having a thickness of 15 μm, thereby forming wiring patterns and vias. 11 was formed. Next, as shown in FIG. 3 (k), the resist pattern 10 is stripped, and as shown in FIG. 4 (l), a thinned electroless copper plating is performed using a hydrogen peroxide / sulfuric acid-based etching solution. Layer 9 was etched away. Next, as shown in FIG. 4 (m), the electroless plating catalyst 6 was removed with a potassium permanganate solution.
Through the above steps, a printed wiring board according to Example 1 was obtained (see FIG. 4M).

<Comparative Example 1>
Next, a comparative example will be described with reference to the drawings.
First, as shown in FIG. 5C, the first wiring layer 26 was formed. Next, as shown in FIG. 6D, a film-like insulating resin is laminated on the formed first wiring layer 26 and substrate 21 to form an insulating resin layer 28 having a thickness of 35 μm. A via hole 29 having a diameter of 40 μm was formed on the substrate with a UV laser. Smear was removed with a potassium permanganate solution, and an electroless plating catalyst was applied. As shown in FIG. 6E, the electroless copper plating layer 30 is formed to a thickness of 1.0 μm by electroless copper plating, and a 25 μm thick dry film resist is formed on the surface of the electroless copper plating layer 30. The resist pattern 31 having a line / space of 10/10 μm was formed by coating, exposure and development. Next, electrolytic copper plating was performed using a copper sulfate bath, an electrolytic copper plating layer 32 having a thickness of 15 μm was formed, and a wiring pattern and a via 33 were formed. Next, as shown in FIG. 6F, the resist pattern 31 was peeled off. Then, the exposed electroless copper plating layer 30 was removed by etching using a hydrogen peroxide / sulfuric acid based etching solution. Next, the electroless plating catalyst was removed with a potassium permanganate solution.
Through the above steps, a printed wiring board according to Comparative Example 1 was obtained (see FIG. 6F).

  The cross sections of the wiring patterns obtained in Example 1 and Comparative Example 1 were confirmed. While the thinning of the top diameter of the wiring pattern of Comparative Example 1 was about 1.2 μm, the thinning of the top diameter of the wiring pattern of Example 1 was about 0.5 μm. From this result, it was confirmed that the circuit thinning due to the side etching could be reduced by thinning the electroless copper plating layer 7 of the wiring pattern.

  The printed wiring boards obtained in Example 1 and Comparative Example 1 were subjected to a thermal cycle (1000 times) test to confirm the number of cracks generated at the via connection interface. The number of via cracks in Comparative Example 1 was 6 (15 observations), whereas the number of via cracks in Example 1 was 0 (15 observations). From this result, it was confirmed that the generation of cracks at the via connection interface could be reduced by forming an electrolytic copper plating layer around the via hole.

  By using the present invention, it is possible to provide a printed wiring board and a method for manufacturing the printed wiring board capable of suppressing deterioration in electrical characteristics and reliability due to ion residues and ensuring electrical connection reliability between layers.

DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 2 ... 1st wiring layer 3 ... Insulating layer 4 ... Via hole 5 ... Smear 6 ... Plating catalyst 7 ... 1st metal film 8 ... 1st 1 resist film 9 ... first thin metal film 10 ... second resist film 11 ... via 12 ... second metal film 21 ... double-sided copper-clad substrate 22 ... through hole 23 .... Electrolytic copper plating 24 ... Hole filling ink 25 ... Resist pattern 26 ... First wiring layer 27 ... Core layer 28 ... Insulating layer 29 ... Via hole 30 ... Electroless Copper plating 31 ... resist pattern 32 ... electrolytic copper plating 33 ... via 34 ... second wiring layer

Claims (4)

A method for manufacturing a multilayer printed wiring board, wherein a plurality of wiring layers are formed on an insulating substrate via an insulating layer, and the wiring layers are electrically connected by filled vias,
Forming a via hole in the insulating layer;
Forming a first metal film on the entire surface of the insulating layer and the via hole;
Forming a resist film on the first metal film;
Exposing and developing the resist film; and
Forming a second metal film on the first metal film exposed after development of the resist film;
Removing the resist film;
A step of removing the first metal film exposed after the removal of the resist film,
Furthermore, a resist film is formed so as to cover the first metal film formed in the via hole between the step of forming the first metal film and the step of forming the resist film, and insulation other than the via hole Etching the first metal film formed on the layer, whereby the first metal film formed on the insulating layer other than the via hole is made thinner than the first metal film formed on the via hole. A method for manufacturing a printed wiring board. A method for manufacturing a multilayer build-up wiring board in which a plurality of wiring layers are formed on both surfaces of a core substrate in which through holes are formed via insulating layers, and the wiring layers are electrically connected by filled vias. And
Forming a via hole in the insulating layer;
Forming a first metal film on the entire surface of the insulating layer and the via hole;
Forming a resist film on the first metal film;
Exposing and developing the resist film; and
Forming a second metal film on the first metal film exposed after development of the resist film;
Removing the resist film;
A step of removing the first metal film exposed after the removal of the resist film,
Furthermore, a resist film is formed so as to cover the first metal film formed in the via hole between the step of forming the first metal film and the step of forming the resist film, and insulation other than the via hole Etching the first metal film formed on the layer, whereby the first metal film formed on the insulating layer other than the via hole is made thinner than the first metal film formed on the via hole. A method for manufacturing a printed wiring board. A multilayer printed wiring board in which a plurality of wiring layers are formed on an insulating substrate via an insulating layer, and the wiring layers are electrically connected by filled vias,
The insulating layer in which via holes are formed;
A first metal film formed on the surface of the insulating layer and the via hole;
A second metal film formed on the first metal film;
The printed wiring board, wherein the first metal film formed on the insulating layer other than the via hole is thinner than the first metal film formed on the via hole. A multilayer build-up wiring board in which a plurality of wiring layers are formed via insulating layers on both surfaces of a core substrate in which through holes are formed, and the wiring layers are electrically connected by filled vias,
The insulating layer in which via holes are formed;
A first metal film formed on the surface of the insulating layer and the via hole;
A second metal film formed on the first metal film;
The printed wiring board, wherein the first metal film formed on the insulating layer other than the via hole is thinner than the first metal film formed on the via hole.

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