JPH11238970A - Multilayered printed board and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To flatten the upper surface, by forming the plated catalyst layer so as to cover the side surfaces and the bottom surfaces of the first and the second opening parts in the second conductor layer, and forming an electroless metal plated layer so as to cover the plated layer furthermore. SOLUTION: A first insulating layer 28 is formed on a printed substrate 26. On the first insulating layer 28, a second insulating layer 36 which has a second opening part 31 communication to a first opening part 29 and a third opening part 33, wherein the bottom part reaches only on the first insulating layer 28, is formed. Then, a second conductor layer 33 is embedded in the first to third opening parts 29, 31 and 32. In the second conductor layer 33, a plated catalyst layer 34 is formed so as to cover the side surfaces and the bottom surfaces of the first to third opening parts 29, 31 and 32. An electroless metal plated layer 35 is formed so as to cover the plated catalyst layer 34. Three layers with an electric metal plated layer 36 are formed so as to cover the layers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a connection between conductive layers, wherein insulating layers and conductive layers are formed alternately on a substrate.
The present invention relates to a multilayer printed circuit board and a method for manufacturing the multilayer printed circuit board via via holes, and more particularly to flattening and improving reliability.

[0002]

2. Description of the Related Art A BGA (Ball Grid Array) or C
Development of a small package such as SP (Chip Size Package) and a bare chip mounting technology are being advanced. In order to realize high-density mounting with a small number of layers, a multilayer printed circuit board used for these is strongly required to have a thinner wiring pattern and a smaller via hole diameter.

In order to solve such a problem, attention has been paid to a multilayer printed circuit board by a build-up method in which insulating layers and conductive layers are sequentially and alternately formed on a substrate and the respective conductive layers are connected via via holes. As prior arts, JP-A-4-148590 and JP-A-3-329.
7 and JP-A-9-116272.

According to these, it is possible to form a conductor circuit with a wiring pitch of 150 μm or less, and it is possible to form wiring with a narrower pitch than 200 μm which is the limit of a conventional multilayer printed circuit board. Further, the diameter of the via hole connecting the layers is set to 30 which is the limit of the conventional multilayer printed circuit board.
It can be formed at 150 μm or less, which is smaller than 0 μm.

Hereinafter, a general build-up multilayer printed circuit board will be described. 14 to 17 show a conventional method of manufacturing a multilayer printed circuit board. First, a first conductor layer 2 formed of a desired circuit is formed on a printed circuit board 1 (see FIG. a)), a first insulating layer 3 made of, for example, a negative photosensitive resin is applied so as to cover the first conductor layer 2 (FIG. 14B). Next, a mask 4 formed in a desired pattern is placed on the upper surface of the first insulating layer 3, and the first insulating layer 3 is exposed to light 5 (FIG. 14C).

Next, the first insulating layer 3 is developed to form a via hole 6 (FIG. 14D). Next, a roughened surface 7 is formed on the surface of the first insulating layer 3 with a chemical roughening solution (FIG. 14E), and then electrically connected to the first conductor layer by a plating method. A second conductor layer is formed. As this plating method, there are three kinds of methods generally called a subtractive method, a semi-additive method and a full-additive method.

First, in the case of the subtractive method, FIG.
After forming as shown in 4 (e), a plating catalyst layer is formed,
An electroless copper plating layer 8 and an electrolytic copper plating layer 9 are sequentially formed on the entire surface (FIG. 15A). Next, a resist is applied and desired patterning is performed to form a resist film 10 (FIG. 1).
5 (b)). Next, using this resist film 10 as a mask, the electrolytic copper plating layer 9 and the electroless copper plating layer 8 are etched with an etching solution for etching only copper, and then the resist film 10 is peeled off. A second conductor layer 11 made of the electroless copper plating layer 8 is formed (FIG. 115 (c)).

In the case of the semi-additive method, FIG.
After forming as shown in 4 (e), a plating catalyst layer is formed,
An electroless copper plating layer 12 is formed by thinning the entire surface, and a resist film 1 is formed at a desired position on the upper surface of the electroless copper plating layer 12.
3 is formed (FIG. 16A). Next, the resist film 13
The copper plating layer 14 is formed only in the opening of FIG.
(B)). Next, the resist film 13 is peeled off, the electroless copper plating layer 12 is removed with an etching solution for etching only copper, and a second conductor layer composed of the electroless copper plating layer 12 and the electric copper plating layer 14 is formed. 15 (FIG. 16)
(C)).

In the case of the full additive method, FIG.
After forming as shown in 4 (e), a plating catalyst layer is formed,
A permanent resist film 16 is formed in a desired pattern (FIG. 17A). Next, a second conductor layer 17 made of an electroless copper plating layer is formed only in the opening of the permanent resist film 16 (FIG. 17B).

According to the above-described conventional method, after the formation of the via hole 6, the second conductor layers 11, 15, and 1 having the same thickness are formed on the via hole 6 and other portions.
7 to form second conductor layer 1 above via hole 6
Concave portions having the same thickness as the first insulating layer 3 are formed in 1, 15, and 17. For this reason, it is difficult to form an upper via hole above the via hole 6 or to provide a mounting pad above the via hole 6.

Further, according to the subtractive method and the semi-additive method, the unevenness becomes even more severe.
When the circuit pattern becomes finer, the space between the patterns becomes narrower, and it becomes difficult to supply the processing liquid or the washing water between the patterns. In addition, when nickel plating and gold plating are sequentially formed on the conductor to prevent oxidation of the conductor, short circuits frequently occur between the wiring patterns, and the production yield is significantly reduced. Further, when a conductor circuit for multilayering is formed on the upper portion, there is a problem that it is difficult to automate a pattern inspection by image processing because the unevenness is severe.

Therefore, as a method of reducing the step on the upper portion of the second conductor layer, for example, there is a method of manufacturing a multilayer printed circuit board disclosed in Japanese Patent Laid-Open No. Hei 9-116272 (hereinafter referred to as Conventional Example 1). As a manufacturing method, first, a first conductor layer 19 composed of a desired circuit is formed on a printed board 18 (FIG. 18A), and the first conductor layer 19 is formed so as to cover the first conductor layer 19.
Is applied and cured by heat treatment (FIG. 18B).

Next, a second resist film 21 is applied on the first resist film 20, and a desired concave portion 22 is formed by development (FIG. 18C). Next, after forming a plating catalyst layer, an electroless copper plating layer 23 is formed on the entire surface (FIG. 1).
8 (d)). Next, the photosensitive film 24 is exposed and developed on the electroless copper plating layer 23, and the concave portions 2 corresponding to the wiring patterns are formed.
2 is opened (FIG. 19A).

Next, copper 25 is buried in the recess 22 by electrometal plating (FIG. 19B). Next, the photosensitive film 24 is peeled off (FIG. 19C), and the second resist film 2 is removed.
Etch back the entire surface until 1 is exposed (FIG. 19)
(D)). In this way, the concave portions generated by the above-described conventional methods could be reduced.

[0015]

The conventional multilayer printed circuit board has been constructed as described above. However, in the case of Conventional Example 1, when the concave portion 22 is filled with the copper 25 by using the electrometal plating method, the current distribution originally differs depending on the pattern shape and the pattern density of the concave portion 22, and the copper 25 formed in the concave portion 22 is originally formed. Has a problem that unevenness remains on the surface even when ordinary chemical etch-back is performed after the photosensitive film 24 is peeled off.

Further, in the subtractive method, the semi-additive method and the first conventional example, a step of removing a resist film and a photosensitive film for patterning wiring is required, which causes a problem that the number of steps is increased. .

In addition, in the full additive method, in order to form the electroless copper plating 17, it is necessary to immerse in a strong alkaline electroless copper plating solution for a long time (5 to 20 hours). There is a problem that water is absorbed in the layer, and the insulating layer dissolves and deteriorates, thereby lowering the insulating ability of the insulating layer. Furthermore, since the plating catalyst layer is not formed on the side surface of the permanent resist 16 (the portion indicated by C in FIG. 17B), the adhesion between the side surface of the permanent resist 16 and the second conductor layer 17 However, there is a problem that the reliability is reduced.

Further, in the case of the subtractive method, the semi-additive method, and in the case of the conventional example 1, after the plating catalyst layer is formed, electroless copper plating is performed, and copper plating is performed on the upper portion thereof. FIG. 15 (c), FIG.
It is necessary to chemically remove the plating catalyst layer remaining in (c) and the portion indicated by A in FIG. 19D). However, due to excessive etching of the plating catalyst layer, the originally required copper plating layer is etched and becomes thinner than a desired wiring width, or the adhesion between the copper plating layer and the insulating layer is reduced. Further, in addition to the conventional step of patterning the second conductor layer, a step of removing the plating catalyst layer must be newly provided, resulting in an increase in equipment cost.

Further, it is extremely difficult to completely remove the plating catalyst layer by the above-mentioned method, and there is a problem that the insulation resistance between the wirings is reduced, and the reliability is low in an accelerated test at high temperature and high humidity. Had occurred. Further, in the full additive method, since the permanent resist 16 is not removed,
The plating catalyst layer existing below (for example, a portion indicated by B in FIG. 17B) cannot be removed, which causes a serious problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a multilayer printed board and a method of manufacturing a multilayer printed board which can planarize an upper surface and improve reliability. With the goal.

[0021]

Means for Solving the Problems Claim 1 according to the present invention.
Is a printed circuit board on which a first conductive layer is formed, and a first printed circuit board reaching the first conductive layer on the printed circuit board.
A first insulating layer having an opening of, and on the first insulating layer,
The second opening and the bottom communicating with the first opening are the first opening.
A second insulating layer having a third opening reaching only on the insulating layer, and a second conductor layer embedded in the first to third openings. A plating catalyst layer formed to cover the side and bottom surfaces of the first to third openings, an electroless metal plating layer formed to cover the plating catalyst layer, and an electroless metal plating layer It consists of three layers: an electrometal plating layer formed so as to cover the top.

According to a second aspect of the present invention, there is provided a multilayer printed board including a printed board on which a first conductive layer is formed, and a first opening on the printed board reaching the first conductive layer. A second insulating layer having a first insulating layer, and a second opening on the first insulating layer, the second opening communicating with the first opening, and a third opening having a bottom only on the first insulating layer. , And a second conductor layer embedded in the first through third openings, and the first conductor in the first opening and the second opening are formed in the first opening. A first plating catalyst layer formed so as to cover the side and bottom surfaces of the first and second electroless metal plating layers formed so as to cover the first plating catalyst layer;
A first electric metal plating layer formed so as to cover the first electroless metal plating layer and a first electric metal plating layer, the first electric metal plating layer being formed so as to cover the side surface of the second opening; A second plating catalyst layer formed so as to cover the plating layer,
A third electroless metal plating layer formed so as to cover the second plating catalyst layer and a second electrometallic plating layer formed so as to cover the second electroless metal plating layer; A second plating catalyst layer formed of six layers, the second conductor layer in the third opening being formed so as to cover the side and bottom surfaces of the third opening; Three layers of a second electroless metal plating layer formed so as to cover the catalyst layer and a second electrometallic plating layer formed so as to cover the second electroless metal plating layer It consists of

According to a third aspect of the present invention, there is provided the multilayer printed board according to the first or second aspect, wherein the second opening is formed on the second opening in which the second conductor layer is embedded. An insulating layer having an opening formed in communication is formed, a conductor layer embedded in the opening is formed, and the conductor layer is electrically connected to a second conductor layer.

According to a fourth aspect of the present invention, there is provided the multilayer printed circuit board according to any one of the first to third aspects, wherein a surface of the first insulating layer and the second insulating layer in contact with the second conductor layer is provided. In this case, a roughened surface is formed.

According to a fifth aspect of the present invention, there is provided the multilayer printed circuit board according to the fourth aspect, wherein the roughened surface formed on the first insulating layer is replaced with the roughened surface formed on the second insulating layer. It is rougher than the surface.

According to a sixth aspect of the present invention, there is provided the multilayer printed circuit board according to the fifth aspect, wherein the average particle diameter of the filler contained in the resin constituting the first insulating layer is less than that of the second insulating layer. It is larger than the average particle size of the filler contained in the resin to be formed.

According to a seventh aspect of the present invention, there is provided the multilayer printed board according to the sixth aspect, wherein the average particle diameter of the filler contained in the resin constituting the first insulating layer is 1 to 20.
The average particle diameter of the filler contained in the resin constituting the second insulating layer is in the range of 0.01 to 5 μm.

Further, according to a method of manufacturing a multilayer printed circuit board according to claim 8 of the present invention, a first insulating layer is applied on a printed circuit board on which a first conductive layer is formed, and a desired first insulating layer is formed. Opening a region to the first conductor layer, forming a first opening, applying a second insulating layer on the first insulating layer,
In a desired region of the second insulating layer, openings are formed until reaching the first opening and until the bottom reaches only above the first insulating layer, and second and third openings are respectively formed. A plating catalyst layer by a plating method so as to bury the first to third openings and cover the second insulating layer;
An electroless metal plating layer and an electrometal plating layer are sequentially formed to form a second conductor layer, the second conductor layer is mechanically polished, and the second conductor on the upper surface of the second insulating layer is formed. The layer is removed and exposed.

According to a ninth aspect of the present invention, in the method for manufacturing a multilayer printed circuit board according to the ninth aspect, the first to third openings are formed and the first to third openings are formed before forming the second conductor layer. This is for roughening the first insulating layer and the second insulating layer.

According to a tenth aspect of the present invention, in the method of manufacturing a multilayer printed circuit board, a first insulating layer is applied on a printed circuit board on which a first conductive layer is formed, and a desired first insulating layer is formed. A first plating catalyst layer is formed by plating so that the region is opened to the first conductor layer, a first opening is formed, and the first opening is buried and the first insulating layer is covered. Forming a first electroless metal plating layer and a first electrometal plating layer sequentially to form a lower conductor layer, mechanically polishing the lower conductor layer, and forming a lower conductor layer on the upper surface of the first insulating layer. Removing and exposing, applying a second insulating layer on the first insulating layer, and in a desired region of the second insulating layer up to the first opening, that is, the lower conductive layer, and the bottom portion of the second insulating layer. The second and third openings are respectively formed until only the first insulating layer is formed. Then, the second plating catalyst layer, the second electroless metal plating layer, and the second electric plating layer are filled by the plating method so as to fill the second opening and the third opening and cover the second insulating layer. A metal plating layer is sequentially formed to form an upper conductor layer, the upper conductor layer is mechanically polished, the upper conductor layer on the upper surface of the second insulating layer is removed and exposed, and the lower conductor layer and the upper conductor layer are used. Forming a second conductive layer.

According to a tenth aspect of the present invention, in the method of the tenth aspect, the first opening is formed, and the first insulating layer is formed before the lower conductive layer is formed. The first and second insulating layers are roughened before the upper conductor layer is formed, with the step of roughening and forming the second and third openings.

According to a twelfth aspect of the present invention, there is provided a method of manufacturing a multilayer printed circuit board according to any one of the eighth to eleventh aspects. The plating method of the layer or the second electric metal plating layer uses a pulse plating method or a periodic inversion current plating method.

According to a thirteenth aspect of the present invention, in the method of the twelfth aspect, the electric metal plating layer, the first electric metal plating layer, or the second electric metal plating layer has a desired thickness. After chemical etching, it is polished mechanically.

[0034]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a configuration of a multilayer printed circuit board according to Embodiment 1 of the present invention. In the figure, 26 is a printed circuit board, 27 is a first conductor layer formed on the printed circuit board 26, and the surface is formed with a roughened surface. Reference numeral 28 denotes a first insulating layer having a first opening 29 extending to the first conductive layer 27 on the printed circuit board 26, and is made of, for example, a photosensitive insulating resin mainly containing epoxy acrylate.

Reference numeral 30 denotes a second opening 31 communicating with the first opening 29 on the first insulating layer 28 and a third opening 32 having a bottom only on the first insulating layer 28. The second
The insulating layer is made of, for example, a photosensitive insulating resin containing epoxy acrylate as a main component. 33 is a second conductor layer embedded in the first to third openings 29, 31, and 32;
The surfaces of the first insulating layer 28 and the second insulating layer 30 that are in contact with the second conductor layer 33 are formed as roughened surfaces.

The second conductor layer 33 includes a plating catalyst layer 34 formed so as to cover the side and bottom surfaces of the first through third openings 29, 31, and 32. Metal plating layer 3 formed so as to cover
5 and an electric metal plating layer 36 formed so as to cover the electroless metal plating layer 35.

A method for manufacturing the multilayer printed circuit board according to the first embodiment configured as described above will be described with reference to FIGS. First, a first conductor layer 27 whose surface has been roughened by etching or the like is formed on a printed board 26 after patterning (FIG. 2A). Next, a photosensitive insulating resin is applied on the first conductor layer 27 by, for example, a curtain coater. Then, the temperature is set to 80 ° C. in a clean oven that can be forcibly exhausted by nitrogen gas.
And let dry for 40 minutes. At this time, the average thickness of the photosensitive insulating resin may be in a range where an insulating relationship with the second conductive layer formed on the first conductive layer 27 in a later step is maintained. Thickness of the upper surface of the conductor layer 27 (FIG. 2B)
(Thickness indicated by t1) of about 50 μm.

Next, a patterned photomask is placed on the photosensitive insulating resin, and the exposure amount is set to 500 to 3000 by an exposing machine using, for example, a metal halide lamp as a light source.
After exposure at mJ / cm ^{2, the} unexposed portion of the photosensitive insulating resin is developed and removed with a spray developing machine for 120 seconds using a developing solution comprising a 1% aqueous solution of sodium carbonate at a temperature of 30 ° C. Then, a via hole having an opening diameter of 100 to 150 μm is formed. After washing with water, the temperature is set to 150 ° C. in a clean oven and thermally cured for 60 minutes to form a first hole having a first opening 29 as a via hole. An insulating layer 28 is formed (FIG. 2B).

Next, after the surface of the first insulating layer 28 is flattened by using, for example, a manual type biaxial polishing machine to which a baffle is attached, the surface of the first insulating layer 28 is exposed by, for example, a curtain coater. Apply a conductive insulating resin. Then, the temperature is set to 80 ° C. in a clean oven that can be forcibly exhausted by nitrogen gas, and dried for 40 minutes. At this time, the average thickness of the photosensitive insulating resin is set in consideration of the mechanically polished thickness in addition to the desired thickness of the second conductor layer formed in a later step, For example, the first insulating layer 28
The thickness of the upper surface (thickness indicated by t2 in FIG. 2C) is 30
What is necessary is just to have about μm.

Next, a patterned photomask is placed on the photosensitive insulating resin, and the exposure amount is set to 500 to 3000 using an exposing machine using, for example, a metal halide lamp as a light source.
After exposure at mJ / cm ^{2, the} unexposed portion of the photosensitive insulating resin is developed and removed by a spray developing machine for 80 seconds using a developing solution comprising a 1% aqueous solution of sodium carbonate at a temperature of 30 ° C. Then, an opening pattern is formed, and after washing with water, the temperature is set to 150 ° C. in a clean oven, and thermosetting is performed for 60 minutes, and the second opening 31 and the bottom communicating with the first opening 29 have the first insulating property. Third opening 3 only over layer 28
2 is formed (see FIG. 2).
(C)).

Next, the exposed portions of the first and second insulating layers are chemically etched, for example, with a treatment liquid containing sodium permanganate as a main component, and the surface is roughened (not shown).
(The configuration of the roughened surface will be described later in detail). Next, the first and second layers are immersed in a solution containing a plating catalyst made of, for example, palladium.
The plating catalyst layer 34 is formed on the exposed surfaces of the insulating layers 28 and 30 (FIG. 2D).

Next, the electroless copper plating layer 35 is coated, for example, with an average thickness of 0.1 so as to cover the upper surface of the plating catalyst layer 34.
After washing with water, the temperature is set to 150 ° C. in a clean oven purged with nitrogen gas, and heat treatment is performed for 60 minutes to improve the adhesion of the electroless copper plating layer 35.

Next, for example, pickling is performed in a 10% sulfuric acid aqueous solution, and after washing with water, electrolytic copper plating is performed at a current density of, for example, 1 to 3 A / dm ² to form an electrolytic copper plating layer 36. The uppermost surface of the layer 36 is formed, for example, to have a thickness of 80 μm or more so that the lowermost portion of the upper surface is higher than the upper surface of the second insulating layer 30. Then, the plating catalyst layer 34 and the electroless copper plating layer 35
Then, the second conductor layer 33 composed of three layers of the electrolytic copper plating layer 36 is formed (FIG. 3). Next, after washing with water,
In a clean oven, the temperature is raised to 150 ° C. and heat treatment is performed for 60 minutes to improve the adhesion of the electrolytic copper plating layer 36.

Next, the surface of the electrolytic copper plating layer 36 is polished by a six-axis polisher (the six-axis polisher shown here is
The first two shafts have a rough baffle, the middle two shafts have a medium bough, and the second two shafts have a fine buff. ). Then, when a part of the second insulating layer 30 is exposed, the second insulating layer 3 is formed using a biaxial polisher having a finer baffle.
The second conductive layer 33 on the upper surface of the first layer 0 is entirely removed to expose the second insulating layer 30.

By performing such a removing step, all of the second conductor layer 33 that has entered the roughened surface formed on the upper surface of the second insulating layer 30 is removed.
On the upper surface of the second insulating layer 30, not only the electrolytic copper plating layer 36 and the electroless copper plating layer 35 do not exist, but also the plating catalyst layer 34 does not exist. Also,
A mechanically roughened surface generated by the polishing is formed on the upper surface of the second insulating layer 30 (FIG. 1).

Here, the roughening omitted above will be described with reference to FIGS. The details of the insulating layers 28 and 29 will also be described. First insulating layer 28
Is formed so that the average particle diameter of the filler contained in the resin constituting the second insulating layer 29 is larger than the average particle diameter of the filler contained in the resin constituting the second insulating layer 29. The average particle size of the filler of the insulating layer 28 is 10 μm.
The second insulating layer 30 is formed of a material having an average particle diameter of 1 μm.

Then, as shown in FIGS. 2C and 4A, after the openings 29, 31, and 32 are formed, the exposed surfaces of the first and second insulating layers 28 and 30 are formed. Roughened surfaces 37 and 38 are formed, respectively. The roughness of the roughened surfaces 37 and 38 thus formed is such that the roughened surface 37 formed on the first insulating layer is rougher than the roughened surface formed on the second insulating layer 30. Formed (Fig. 4
(B)).

This can be easily performed by changing the relationship between the average particle diameters of the fillers contained in the resin constituting the first insulating layer 28 and the second insulating layer 30. It is. And the roughened surface 3
After the formation of the layers 7 and 38, the second conductor layer 33 is formed, and the second conductor layer 33 is formed so as to fit into the roughened surfaces 37 and 38 (FIG. 5).

By forming in this manner, an excellent anchoring effect can be obtained without lowering the pattern minimum resolution. Further, it can be formed to have excellent followability to the first conductor layer and excellent step absorption.

This will be described with reference to FIGS. 6 and 7. As shown in FIG. 6, what was formed in the above-described example was evaluated as evaluation example 1, and as evaluation example 2, the average particle size of the filler contained in the resin constituting the first and second insulating layers was evaluated. It is assumed that the diameter is the same as that of the second insulating layer of Evaluation Example 1 (average particle size: 1 μm).
The average particle size of the filler contained in the resin forming the first and second insulating layers is the same as that of the first insulating layer of Evaluation Example 1 (average particle size: 10 μm).

The plating adhesion results from the size of the contact area between the conductor layer and the insulating layer. As is clear from this figure, the plating adhesion is 1.2 Kg / cm in Evaluation Examples 1 and 2 where the contact area between the two is relatively large, but the plating adhesion is small in Evaluation Example 3 where the contact area is the smallest. 0.8kg / c
m.

Since the minimum resolution of the pattern (line interval and space interval) is inversely proportional to the roughness of the roughened surface, evaluation examples 1 and 2 in which a filler having a small average particle size is present at the top. Pattern resolution is 3
In the evaluation example 3, the pattern had a minimum resolution of 6 μm, which had a small average particle diameter of 0 μm and a large average particle diameter of the filler.
It becomes as large as 0 μm.

In addition, the ability to follow the first conductor layer decreases as the average particle size of the filler increases. This is because the larger the average particle size of the filler is, the larger the flowability is, and the more easily the filler becomes flat. Here, the first conductor layer is 3
FIG. 7 shows a configuration in which the first insulating layer is formed at 0 μm and the first insulating layer is formed at 60 μm.

FIG. 7A shows the case where the first insulating layer 39 is applied and formed in the evaluation examples 1 and 3, which is the first insulation layer 3 having a large average particle diameter of the filler.
Since 9 was formed and flattened, a step of 5 μm was obtained as a whole.

FIG. 7B shows a case in which the first insulating layer 41 in the evaluation example 2 is applied and formed, in which the first insulating layer 41 having a small average particle diameter of the filler is formed. Since the surface was not flattened, the overall step was 20 μm.

As described above, the evaluation examples 1 and 3 have smaller followability to the first conductor layer than the evaluation example 2,
A configuration excellent in flatness can be obtained.

As described above, the average particle diameter of the filler contained in the resin constituting the first insulating layer 28 is made larger than the average particle diameter of the filler contained in the resin constituting the second insulating layer 30. Thereby, it is possible to simultaneously have both advantageous characteristics such as plating adhesion and pattern resolution, which cannot be obtained by a single composition having the average particle size of the filler.

If the average particle size of the filler contained in the resin constituting the first insulating layer 28 is larger than the average particle size of the filler contained in the resin constituting the second insulating layer 30, , Although the same effects as above can be achieved,
The average particle size of the filler contained in the resin constituting the first insulating layer 28 is in the range of 1 to 20 μm, and the average particle size of the filler contained in the resin constituting the second insulating layer 30 is 0 μm. Preferably, the thickness is in the range of 0.01 to 5 μm.

The surface roughness is not affected by the resin containing the filler as long as the surface is roughened by removing or dissolving the filler by a physical or chemical method. And second insulating layer 2
Even if 8, 30 are made of different resins,
If the relationship between the fillers contained in each of these resins is configured as described above, it goes without saying that the same effect can be obtained.

According to the multilayer printed board of the first embodiment configured as described above, all surfaces of each of the insulating layers 28 and 30 in contact with the second conductor layer 33, ie, the first to third openings. Since the plating catalyst layer 34 is formed so as to cover the side surfaces and the bottom surfaces of the portions 29, 31, and 32, each of the insulating layers 2
8, 30 and the second conductor layer 33 have excellent adhesion,
Infiltration of moisture and the like from the interface between the second insulating layer 30 and the second conductor layer 33 can be prevented, and a highly reliable wiring can be obtained.

Since the plating catalyst layer 34 on the upper surface of the second insulating layer 30 has been completely removed by mechanical polishing,
A circuit can be formed without causing deterioration of insulation resistance between wirings caused by the remaining plating catalyst layer 34. For example, even if a gap between circuits is formed to about 20 μm, a circuit of 10 ¹² Ω or more can be formed. Since the insulation resistance between wirings can be secured, the short circuit between wiring patterns due to nickel plating and gold plating, which are formed sequentially to prevent oxidation in the next process, can be greatly reduced, and the cost of multilayer printed circuit boards can be reduced Becomes

Since the step of removing the plating catalyst layer 34 and the step of forming the second conductor layer 33 can be performed in the same step, a step of removing the plating catalyst layer 34 is added. A circuit can be formed without any problem.

Since the upper surface of the second conductor layer 33 is formed to have the same height as the upper surface of the second insulating layer 30 by mechanical polishing of the second conductor layer 33, the upper surface has irregularities. It is possible to form a multilayer printed circuit board without the need. Therefore, the yield of mounting can be remarkably improved, for example, when the flatness of the component mounting surface is strictly required, such as bare chip mounting and CSP mounting.

Further, the second conductor layer 33 embedded in the second opening 31 communicating with the first opening 29 can be used as a component mounting pad, thereby increasing the component mounting density and increasing the board Since the wiring density can be increased and the thickness of the second conductor layer 33 is large, the connection at this location is strong and the reliability is excellent.

In the formation of the second conductor layer 33,
Since there is no need to perform patterning with a resist film as shown in Conventional Example 1, the number of devices and the number of steps involved in the resist film forming step can be reduced. In addition, as in the case of the full additive method, a strong alkaline electroless copper plating solution is used for a long time (for example, in order to form a
It does not need to be immersed, and can be formed in an acidic electrolytic copper plating solution in a short time (for example, it takes 2 to 3 hours to form a film having a thickness of 80 μm). Therefore, the amount of water supplied to each of the insulating layers 28 and 30 can be minimized.
The multilayer printed circuit board can be formed without causing the occurrence of dissolution deterioration or the like of 0 and without lowering the insulation performance.

In the first embodiment, the plating method is performed by a normal method, and the upper surface shape of the electrolytic copper plating layer 36 directly reflects the shape of the lower layer in the state shown in FIG. However, the present invention is not limited to this, and as shown in FIG. 8, for example, a pulse plating method (a plating method in which a plating execution time and a plating pause time are alternately repeated) or a periodic inversion current plating method ( The electro-copper plating layer 36a may be formed using an electroplating method in which the + and-poles are periodically inverted until the upper surface becomes substantially flat (FIG. 8A).

In this case, etching is then performed by chemical etching until, for example, the thickness of the copper electroplated layer 36b on the upper surface of the second insulating layer 30 (the thickness indicated by t3 in FIG. 8B) becomes about 5 μm. Then, the second conductor layer 33 formed on the upper surface of the second insulating layer 30 is removed by mechanical polishing in the same manner as in the first embodiment described above, and the upper surface of the second insulating layer 30 is removed. Is exposed (FIG. 1).

By forming in this manner, the amount of the copper electroplated layer 36 to be removed can be reduced and the removal time can be reduced as compared with the case where the entire copper electroplated layer 36 is mechanically polished. The dimensional stability (registration) of the substrate can be improved by reducing the amount, and the manufacturing cost can be reduced. This means that when mechanical polishing is performed, the force naturally acts on the substrate, causing the substrate to expand and contract, causing deformation of the substrate. Therefore, it can be said that the dimensional stability of the substrate depends on the amount of mechanical polishing.

In the first embodiment, the first
An example in which only the second conductor layer 33 is formed on the conductor layer 27 of the first embodiment is not limited to this. For example, as shown in FIG. A third insulating layer 46 having a fourth opening 47 to be formed, and a fifth insulating layer 46 provided on the third insulating layer 46 and communicating with the fourth opening 47.
A fourth insulating layer 48 having an opening 49 and a sixth opening 50 whose bottom extends only above the third insulating layer 46;
In addition, a third conductor layer 51 that is embedded in the sixth openings 47, 49, and 50 and that is electrically connected to the second conductor layer 33 can be formed to have a multilayer structure.

As described above, the first opening 29, the second opening 31, the fourth opening 47, and the fifth opening 49 are formed on a straight line in the thickness direction of the printed circuit board 26. Therefore, the signal transmission line can be shortened, and high-frequency signal delay can be suppressed. Further, heat from the components installed on the upper portion of the printed board 26 is transferred to the first opening 29, the second opening 31, and the fourth opening 4.
7, and the second conductor layer 33 and the third conductor layer 51 embedded in the fifth opening 49 can radiate heat to the printed circuit board 26 at the shortest distance.

In the case of multi-layering as described above, the upper surface of each layer, for example, the second insulating layer 30 and the second conductor layer 33,
Also, the upper surfaces of the fourth insulating layer 48 and the third conductor layer 51 are flattened, and in a general reflection type automatic pattern inspection apparatus, the conductor layers of each layer can be distinguished, and each layer can be inspected unattended. Therefore, the inspection cost can be reduced, and the production yield can be improved.

Embodiment 2 FIG. 10 is a sectional view showing a configuration of a multilayer printed circuit board according to Embodiment 2 of the present invention. In the figure, the same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted. 56 is the first insulating layer 2
8, a second opening 57 communicating with the first opening 29.
And a second insulating layer having a third opening 58 whose bottom reaches only above the first insulating layer 28.

Reference numeral 59 denotes the first to third openings 29, 5
In the second conductor layer embedded in the first and second openings 7, 58, the second conductor layer 59 in the first opening 29 and the second opening 58 is formed.
A first plating catalyst layer 60 formed so as to cover the side surface and the bottom surface of the first opening 29;
A first electroless metal plating layer 61 formed so as to cover the first electroless metal plating layer 61 and a first electrometallic plating layer 62 formed so as to cover the first electroless metal plating layer 61. The lower conductive layer 63 is formed so as to cover the side surface of the second opening 57, and the first electric metal plating layer 62
A second plating catalyst layer 64 formed so as to cover the top,
The second plating catalyst layer 64 is formed so as to cover the second plating catalyst layer 64.
And a second electrometallic plating layer 66 formed so as to cover the second electroless metal plating layer 65 and an upper conductor layer 67 composed of three layers. Become.

Then, the second conductor layer 59 in the third opening 58 is provided with a second plating catalyst layer 64 formed so as to cover the side and bottom surfaces of the third opening 58, A second electroless metal plating layer 65 formed so as to cover the plating catalyst layer 64 and a second electrometallic plating layer 66 formed so as to cover the second electroless metal plating layer 65; And an upper conductor layer 67 composed of three layers.

A method for manufacturing a multilayer printed circuit board according to the second embodiment having the above-described structure will be described with reference to FIGS. First, similarly to the first embodiment,
A first conductor layer 27 having a surface roughened by etching or the like after patterning on a printed board 26.
Is formed (FIG. 11A). Next, the first conductor layer 27
A photosensitive insulating resin is applied on the top using, for example, a curtain coater. Then, the temperature is set to 80 ° C. in a clean oven that can be forcibly exhausted by nitrogen gas, and dried for 40 minutes. At this time, the average thickness of the photosensitive insulating resin is set to a thickness that is polished by mechanical polishing when forming the lower conductive layer in a later step, and the upper conductive layer formed on the first conductive layer 27. What is necessary is just to set in consideration of the thickness which maintains an insulating relationship with the layer.

Next, a patterned photomask is placed on the photosensitive insulating resin, and the exposure amount is set to 500 to 3000 using an exposing machine using, for example, a metal halide lamp as a light source.
After exposure at mJ / cm ^{2, the} unexposed portion of the photosensitive insulating resin is developed and removed with a spray developing machine for 120 seconds using a developing solution comprising a 1% aqueous solution of sodium carbonate at a temperature of 30 ° C. Then, a via hole having an opening diameter of 100 to 150 μm is formed. After washing with water, the temperature is set to 150 ° C. in a clean oven and thermally cured for 60 minutes to form a first hole having a first opening 29 as a via hole. An insulating layer 28 is formed (FIG. 11B).

Next, after the surface of the first insulating layer 28 is flattened by using, for example, a manual type biaxial polishing machine to which a baffle is attached, the surface of the first insulating layer 28 is subjected to, for example, a processing liquid mainly containing sodium permanganate. The surface of the first insulating layer 28 is chemically etched to form a roughened surface (not shown). Next, the first plating catalyst layer 60 is formed on the exposed surface of the first insulating layer 28 by dipping in a solution containing a plating catalyst made of, for example, palladium (FIG. 11C).

Next, a first electroless copper plating layer 61 is formed so as to cover the upper surface of the first plating catalyst layer 60, for example, with an average thickness of 0.1 to 0.5 μm. In a clean oven purged with nitrogen gas, the temperature is set to 150 ° C., and a heat treatment is performed for 60 minutes to improve the adhesion of the first electroless copper plating layer 61.

Next, for example, pickling is performed in a 10% sulfuric acid aqueous solution, and after washing with water, electrolytic copper plating is performed at a current density of, for example, 1 to 3 A / dm ² to form the first electrolytic copper plating layer 62. The lowermost portion of the upper surface of the first electrolytic copper plating layer 62 is formed to be higher than the upper surface of the first insulating layer 28, and the first plating catalyst layer 60, the first electroless copper plating layer 61, and the first The lower conductor layer 63 composed of the three electroplated copper layers 62 is formed (FIG. 11D).

Next, the surface of the first electrolytic copper plating layer 62 is polished by a six-axis polisher. Then, when a part of the first insulating layer 28 is exposed, the lower conductive layer 63 on the upper surface of the first insulating layer 28 is entirely removed using a biaxial polishing machine having a finer baffle, The one insulating layer 28 is exposed.

By performing such a removing step, all of the lower conductor layer 63 that has entered the roughened surface formed on the upper surface of the first insulating layer 28 is removed, and the first insulating layer 28 The first electrolytic copper plating layer 62
In addition, the first electroless copper plating layer 61 does not exist, and the first plating catalyst layer 60 does not exist. Further, a mechanically roughened surface generated by this polishing is formed on the upper surface of the first insulating layer 28 (FIG. 12A).

Next, a photosensitive insulating resin is applied on the first insulating layer 28 by, for example, a curtain coater. And
The temperature is set to 80 ° C. in a clean oven that can be forcibly evacuated with nitrogen gas and dried for 40 minutes. At this time, the average thickness of the photosensitive insulating resin may be set in consideration of a desired thickness of the upper conductor layer formed in a later step and a thickness to be mechanically polished.

Next, a patterned photomask is placed on the photosensitive insulating resin, and the exposure amount is set to 500 to 3000 by an exposing machine using, for example, a metal halide lamp as a light source.
After exposure at mJ / cm ^{2, the} unexposed portion of the photosensitive insulating resin is developed and removed by a spray developing machine for 80 seconds using a developing solution comprising a 1% aqueous solution of sodium carbonate at a temperature of 30 ° C. Then, an opening pattern is formed, and after washing with water, the temperature is set to 150 ° C. in a clean oven, and thermosetting is performed for 60 minutes, and the second opening 57 and the bottom communicating with the first opening 29 are formed of the first insulating material. Third opening 5 only over layer 28
8 is formed (FIG. 12)
(B)).

Next, the first and second insulating layers 2 are treated with a treating solution containing, for example, sodium permanganate as a main component.
The exposed portions 8 and 56 are chemically etched to form a roughened surface (not shown). Next, the first substrate is immersed in a solution containing a plating catalyst made of, for example, palladium.
Then, a second plating catalyst layer 64 is formed on the exposed surfaces of the second insulating layers 28 and 56 (FIG. 12C).

Next, a second electroless copper plating layer 65 is formed so as to cover the upper surface of the second plating catalyst layer 64, for example, with an average film thickness of 0.1 to 0.5 μm. The temperature is set to 150 ° C. in a clean oven purged with nitrogen gas, and heat treatment is performed for 60 minutes to improve the adhesion of the second electroless copper plating layer 65.

Next, pickling is performed in, for example, a 10% sulfuric acid aqueous solution, and after washing with water, electrolytic copper plating is performed at a current density of, for example, 1 to 3 A / dm ^{2 to form} a second electrolytic copper plating layer 65. The second plating catalyst layer 64 and the second electroless copper plating are formed so that the lowermost portion of the upper surface of the second electrolytic copper plating layer 65 is higher than the upper surface of the second insulating layer 56, for example, at least 40 μm. An upper conductor layer 67 composed of three layers of the layer 65 and the second electrolytic copper plating layer 66 is formed, and a second conductor layer 59 composed of the lower conductor layer 63 and the upper conductor layer 67 is formed (FIG. 13). . Next, after washing with water, a heat treatment is performed at a temperature of 150 ° C. for 60 minutes in a clean oven to improve the adhesion of the second electrolytic copper plating layer 66.

Next, the surface of the second electrolytic copper plating layer 66 is polished by a six-axis polishing machine. Then, when a part of the second insulating layer 56 is exposed, the entire second conductive layer 59 on the upper surface of the second insulating layer 56 is removed using a biaxial polisher having a finer baffle. Then, the second insulating layer 56 is exposed.

By performing such a removing step, all of the second conductor layer 59 that has entered the roughened surface formed on the upper surface of the second insulating layer 56 is removed.
On the upper surface of the second insulating layer 56, a second electrolytic copper plating layer 6
6 and the second electroless copper plating layer 65 do not exist, and the second plating catalyst layer 64 also does not exist. Further, a mechanically roughened surface generated by the polishing is formed on the upper surface of the second insulating layer 56 (FIG. 10).

Here, the roughening omitted above will be described. The details of the insulating layers 28 and 56 will also be described. The first insulating layer 28 determines the average particle diameter of the filler contained in the resin constituting the first insulating layer 28 by the second insulating layer 56.
The first insulating layer 28 is formed of a material having an average particle diameter of 10 μm, and the second insulating layer 28 is formed of a material having an average particle diameter of 10 μm.
The insulating layer 56 is formed of a material having an average particle diameter of 1 μm.

With this structure, as shown in FIGS. 11B and 12B, each of the openings 29, 57, 5
After the formation of the first and second insulating layers 8, roughened surfaces are formed on the exposed surfaces of the first and second insulating layers 28 and 56, respectively.
The roughness of the roughened surface formed as described above is such that the roughened surface formed on the first insulating layer 28 is formed more coarsely than the roughened surface formed on the second insulating layer 56. It will be.

This can be easily performed by changing the relationship between the average particle diameters of the fillers contained in the resin constituting the first insulating layer 28 and the second insulating layer 56. It is. Then, after each of the roughened surfaces is formed, the lower conductor layer 63 and the upper conductor layer 67 are formed.
Are formed, and the second conductor layer 63 is formed so as to be hardly inserted into each of the roughened surfaces.

As described above, the average particle diameter of the filler contained in the resin constituting the first insulating layer 28 is made larger than the average particle diameter of the filler contained in the resin constituting the second insulating layer 56. Thereby, similarly to the first embodiment,
Without lowering the pattern minimum resolution, an excellent anchoring effect that cannot be obtained with each composition having the average particle size of the filler can be obtained. In addition, the first conductor layer can be formed to have low followability and excellent flatness.

If the average particle size of the filler contained in the resin constituting the first insulating layer 28 is larger than the average particle size of the filler contained in the resin constituting the second insulating layer 56, , Although the same effects as above can be achieved,
The average particle size of the filler contained in the resin constituting the first insulating layer 28 is in the range of 1 to 20 μm, and the average particle size of the filler contained in the resin constituting the second insulating layer 56 is 0.1 μm. It is preferable that the thickness be in the range of 01 to 5 μm.

[0094] The surface roughness is not affected by the resin containing the filler as long as the surface is roughened by removing or dissolving the filler by a physical or chemical method. And second insulating layer 2
It is needless to say that the same effects can be obtained even if the resins 8 and 56 are made of different resins as long as the relationship between the fillers contained in these resins is configured as described above.

According to the multilayer printed circuit board of the second embodiment configured as described above, all surfaces of the insulating layers 28 and 56 in contact with the second conductor layer 59, that is, the first to third openings Since the first and second plating catalyst layers 60 and 64 are formed so as to cover the side surfaces and the bottom surfaces of the portions 29, 57 and 58, the adhesion between the insulating layers 28 and 56 and the second conductor layer 59 is improved. It is excellent and can prevent penetration of moisture or the like from the interface between the second insulating layer 56 and the second conductor layer 59, and can provide a highly reliable wiring.

Further, the first and second insulating layers 28 and 56
Since the first and second plating catalyst layers 60 and 64 on the upper surface have been completely removed by mechanical polishing, the insulation resistance between the wirings caused by the remaining first and second plating catalyst layers 60 and 64 has been reduced. A circuit can be formed without deterioration. For example, a gap between circuits is 20 μm.
Even if formed to the extent, it is possible to secure an insulation resistance between wirings of 10 ¹² Ω or more, so that a short circuit between wiring patterns due to nickel plating and gold plating, which are sequentially formed to prevent oxidation in the next process, is greatly reduced. And the cost of the multilayer printed circuit board can be reduced.

Although the number of steps is increased as compared with the first embodiment, the steps of the lower layer are reduced when forming the first and second electrolytic copper plating layers 62 and 64, so that The amount of plating of each of the electrolytic copper plating layers 62 and 64 can be reduced, and the amount of polishing can be reduced.

The upper surface of the second conductor layer 59 is formed to have the same height as the upper surface of the second insulating layer 56 by mechanical polishing of the second conductor layer 59, so that the upper surface has irregularities. It is possible to form a multilayer printed circuit board without the need. Therefore, the yield of mounting can be remarkably improved, for example, when the flatness of the component mounting surface is strictly required, such as bare chip mounting and CSP mounting.

Further, the second conductor layer 59 embedded in the second opening 57 communicating with the first opening 29 can be used as a component mounting pad, thereby increasing the component mounting density and increasing the board Since the wiring density can be increased and the thickness of the second conductor layer 59 is large, the connection at this location is strong and the reliability is excellent.

In the formation of the second conductor layer 59,
Since there is no need to perform patterning with a resist film as shown in Conventional Example 1, the number of devices and the number of steps involved in the resist film forming step can be reduced. Further, a strong alkaline electroless copper plating solution is used for a long time (for example, in order to form a
It does not need to be immersed for 15 hours, and can be formed in a short time (for example, it takes 2 to 3 hours to form a film having a thickness of 80 μm) in an acidic electrolytic copper plating solution. Therefore, the amount of water supplied to each of the insulating layers 28 and 56 can be minimized, and each of the insulating layers 28 and 56
A multilayer printed circuit board can be formed without causing dissolution degradation of the resin or the like and without lowering the insulation performance.

Further, in the second embodiment, the plating method is performed by a normal method, and the plating method shown in FIGS.
In the state shown in (1), the upper surface shape of each of the copper electroplated layers 62 and 66 reflects the shape of the lower layer as it is. However, the present invention is not limited to this, and as shown in the first embodiment, For example, the respective copper electroplated layers are formed by using, for example, a pulse plating method or a periodic inversion current plating method until the upper surface becomes substantially flat, and then, for example, the first and second insulating layers 28 and 56 are formed by chemical etching. Is etched until the thickness of each of the electroplated copper layers 62, 66 on the upper surface of the substrate becomes about 5 μm, and thereafter, as in the case of the first embodiment described above, the upper surface of each of the insulating layers 28, 56 is mechanically polished. The formed lower conductor layer and upper conductor layer may be respectively removed to expose the upper surfaces of the insulating layers 28 and 56 (FIG. 10).

By forming in this manner, the amount of each of the electroplated copper layers 62 and 66 can be reduced and the removal time can be reduced as compared with the case where all of the electroplated copper layers 62 and 66 are mechanically polished. , The dimensional stability (registration) of the substrate can be improved by reducing the amount of mechanical polishing, and the manufacturing cost can be reduced.

In the second embodiment, the first
An example in which only the second conductor layer 59 is formed on the conductor layer 27 of the first embodiment is not limited to this. For example, as in the first embodiment, the second opening 5
A third insulating layer having a fourth opening communicating with the first opening, and a fifth opening and a bottom communicating with the fourth opening on the third insulating layer only on the third insulating layer. And a third conductive layer embedded in the fourth to sixth openings and electrically connected to the second conductive layer 59. In addition, it is possible to further increase the number of layers.

As described above, the first opening 29, the second opening 57, the fourth opening, and the fifth opening are formed on a straight line in the thickness direction of the printed circuit board 26. Therefore, as in the first embodiment, the signal transmission line can be shortened, and high-frequency signal delay can be suppressed. Further, heat from the components installed on the upper portion of the printed circuit board 26 is transferred to the first opening 29 and the second opening 5.
7, the second conductor layer 59 and the third conductor layer embedded in the fourth opening and the fifth opening can radiate heat to the printed circuit board 26 at the shortest distance.

In the case of multi-layering as described above, the upper surface of each layer, for example, the second insulating layer 56 and the second conductor layer 57,
Further, the upper surfaces of the fourth insulating layer and the third conductor layer are flattened, and in a general reflection type automatic pattern inspection apparatus, the conductor layers of each layer can be distinguished, and unattended inspection of each layer can be performed. Therefore, the inspection cost can be reduced and the production yield can be improved.

In each of the above embodiments, a double-sided copper-clad glass epoxy substrate is used as a printed circuit board. However, the present invention is not limited to this. For example, a bismaleimide / treazine resin substrate, a phenol resin substrate, a silicon resin A substrate or the like can be used.

Further, as each insulating resin, a photosensitive insulating resin containing epoxy acrylate as a main component has been described as an example.
Without being limited to this, as a photosensitive insulating resin,
Epoxy acrylate resins such as bisphenol A type, bisphenol F type, and phenol novolak type, or resins obtained by adding acrylic acid to these epoxy groups and then carboxylating the hydroxyl groups can be used. It is also possible to use a photosensitive dry film resist. Further, a non-photosensitive resin can be used. In this case, the first opening may be formed by a physical method such as laser ablation or sand blast.

Further, although an example has been shown in which a treatment solution containing sodium permanganate as a main component is used to roughen each insulating layer, the present invention is not limited to this. It is also possible to use an aqueous solution of potassium manganate, ozone, or the like. In addition, as an application method of each insulating resin, an example using a curtain coater has been described. However, the present invention is not limited to this. For example, screen printing, a spin coater, a roller coater, or the like may be used. Needless to say, it is preferable to use a method excellent in performance.

When a photosensitive dry film resist is used, a thermocompression roller or a vacuum laminator may be used. For exposing the photosensitive insulating resin, a high-pressure mercury lamp may be used as a light source in addition to the metal halide light source.
In addition to the buffing, mechanical polishing may be performed using a polishing machine equipped with a roller such as a brush or ceramic, or a scrub polishing machine or a honing polishing machine using abrasive grains.

[0110]

As described above, according to the first aspect of the present invention, the printed circuit board on which the first conductive layer is formed and the first opening reaching the first conductive layer are formed on the printed circuit board. A first insulating layer provided; a second opening communicating with the first opening on the first insulating layer; and a third opening having a bottom reaching only on the first insulating layer. A second insulating layer, a second conductor layer embedded in the first to third openings,
A plating catalyst layer formed so that the second conductor layer covers the side and bottom surfaces of the first to third openings;
Since it is composed of three layers, an electroless metal plating layer formed so as to cover the plating catalyst layer and an electrometallic plating layer formed so as to cover the electroless metal plating layer, the second conductive layer Since the plating catalyst layer is formed on all surfaces of each insulating layer in contact with each other, the adhesion between each insulating layer and the second conductor layer is excellent, and a highly reliable multilayer printed board can be obtained. This has the effect.

According to a second aspect of the present invention, the first
Printed circuit board on which a first conductive layer is formed, a first insulating layer having a first opening reaching the first conductive layer on the printed board, and a first opening formed on the first insulating layer. Second communicating with
A second insulating layer provided with a third opening whose opening and bottom reach only above the first insulating layer, and a second conductor layer embedded in the first to third openings. A first plating catalyst layer formed so that a second conductor layer in the first opening and the second opening covers a side surface and a bottom surface of the first opening; and a first plating catalyst layer. A first electroless metal plating layer formed so as to cover the first electroless metal plating layer, a first electrometallic plating layer formed so as to cover the first electroless metal plating layer, and a second electroless metal plating layer. A second plating catalyst layer formed to cover the side surface of the opening and to cover the first electrometal plating layer, and a second plating catalyst layer formed to cover the second plating catalyst layer. A second electroless metal plating layer and a second electric metal member formed to cover the second electroless metal plating layer. Made at the six layers of the three layers of the gas layer,
A second conductor layer in the third opening is formed so as to cover a side surface and a bottom surface of the third opening, and to cover the second plating catalyst layer. The second
And a second electrometallic plating layer formed so as to cover the second electroless metal plating layer.
Since each plating catalyst layer is formed on all side surfaces of each insulating layer in contact with the second conductor layer, the adhesion between each insulating layer and the second conductor layer is excellent. Therefore, there is an effect that a highly reliable multilayer printed board can be obtained.

According to a third aspect of the present invention, in the first or second aspect, the second conductive layer is buried in the second opening in communication with the second opening. An insulating layer having an opening is formed, a conductor layer embedded in the opening is formed, and the conductor layer is electrically connected to the second conductor layer. With the conductor layer and the conductor layer, there is an effect that it is possible to obtain a multilayer printed board capable of efficiently dissipating heat from other components to the printed board.

According to a fourth aspect of the present invention, in any one of the first to third aspects, the surface of the first insulating layer and the second insulating layer in contact with the second conductor layer is provided with a rough surface. Since the planarized surface is formed, there is an effect that a multilayer printed board that can further improve the adhesion between the second conductor layer and each insulating layer can be obtained.

According to claim 5 of the present invention, in claim 4, the roughened surface formed on the second insulating layer is
Since it is finer than the roughened surface formed on the first insulating layer, the contact area between the conductor layer and the insulating layer is increased, and there is an effect that a multilayer printed board having excellent adhesion between the two can be obtained.

According to claim 6 of the present invention, in claim 5, the average particle diameter of the filler contained in the resin constituting the first insulating layer is less than that of the resin constituting the second insulating layer. Since the average particle diameter of the contained filler is larger than
In comparison with the case where the same property as that of the first insulating layer is used for both the first and second insulating layers, the followability to the first conductor layer can be reduced, and the flatness can be easily improved. There is an effect that a certain multilayer printed board can be obtained.

According to a seventh aspect of the present invention, in the sixth aspect, the average particle diameter of the filler contained in the resin constituting the first insulating layer is in the range of 1 to 20 μm, Since the average particle diameter of the filler contained in the resin constituting the insulating layer is in the range of 0.01 to 5 μm, it is possible to surely obtain a multilayer printed board excellent in adhesion, board flatness and pattern resolution. There is an effect that can be.

According to claim 8 of the present invention, the first
Applying a first insulating layer on the printed circuit board on which the conductive layer of the first is formed, opening a desired region of the first insulating layer to the first conductive layer, forming a first opening; Applying a second insulating layer on the first insulating layer, in a desired region of the second insulating layer, until reaching the first opening, and until the bottom reaches only on the first insulating layer. A plating catalyst layer and an electroless metal plating are formed by a plating method so as to form openings, respectively, to form second and third openings, and to fill the first to third openings and cover the second insulating layer. Forming a second conductor layer by sequentially forming a layer and an electrometal plating layer, mechanically polishing the second conductor layer, and removing the second conductor layer on the upper surface of the second insulating layer. Because it is exposed, the plating catalyst layer is formed on all surfaces of each insulating layer in contact with the second conductor layer, Has excellent adhesion between the insulating layer and the second conductive layer, and the upper surface of the second conductive layer is flat, there is an effect that it is possible to obtain a method of manufacturing a highly reliable multilayer printed circuit board.

According to a ninth aspect of the present invention, in the ninth aspect, the first to third openings are formed, and the first insulating layer and the second insulating layer are formed before forming the second conductor layer. Since the second insulating layer is roughened, the adhesion between each insulating layer and the second conductor layer is further improved, and an effect of obtaining a more reliable method for manufacturing a multilayer printed circuit board can be obtained.

According to a tenth aspect of the present invention, a first insulating layer is applied on a printed circuit board on which a first conductive layer is formed, and a desired region of the first insulating layer is formed by the first conductive layer. The first plating catalyst layer and the first electroless layer are formed by plating so as to form a first opening, fill the first opening, and cover the first insulating layer. Forming a metal plating layer and a first electrometal plating layer sequentially to form a lower conductor layer, mechanically polishing the lower conductor layer, removing and exposing the lower conductor layer on the upper surface of the first insulating layer, A second insulating layer is applied on the first insulating layer, and a desired portion of the second insulating layer is extended to the first opening, that is, the lower conductive layer, and the bottom is formed only in the first insulating layer. And a second and a third opening are formed respectively.
The second plating catalyst layer, the second electroless metal plating layer and the second electrometal plating layer are plated by a plating method so as to bury the opening and the third opening and cover the second insulating layer. Forming an upper conductor layer sequentially, mechanically polishing the upper conductor layer, removing and exposing the upper conductor layer on the upper surface of the second insulating layer, and forming a second conductor composed of the lower conductor layer and the upper conductor layer. Since the conductor layers are formed, the plating catalyst layers are formed on all side surfaces of the respective insulating layers in contact with the second conductor layers, so that the adhesion between the respective insulating layers and the second conductor layers is excellent. In addition, the upper surface of the second conductor layer is flattened, so that a highly reliable method for manufacturing a multilayer printed circuit board can be obtained.

According to an eleventh aspect of the present invention, in the tenth aspect, a step of forming a first opening and roughening the first insulating layer before forming the lower conductor layer is performed. ,
Since the second and third openings are formed and the first insulating layer and the second insulating layer are roughened before forming the upper conductive layer, each of the insulating layers and the second conductive layer is There is an effect that a method for manufacturing a multilayer printed circuit board with higher adhesion and higher reliability can be obtained.

According to a twelfth aspect of the present invention, in the method for manufacturing a multilayer printed circuit board according to any one of the eighth to eleventh aspects, the electric metal plating layer, the first electric metal plating layer, or the second electric metal plating layer is used. The plating method of the plating layer,
Since the pulse plating method or the periodic reversal current plating method is used, a method of manufacturing a multilayer printed circuit board capable of minimizing the amount of plating of the electric metal plating layer, the first electric metal plating layer, or the second electric metal plating layer. Is obtained.

According to a thirteenth aspect of the present invention, in the twelfth aspect, after the electric metal plating layer, the first electric metal plating layer, or the second electric metal plating layer is chemically etched by a desired thickness. Because it is mechanically polished,
Since the polishing amount of the electrometal plating layer or the first electrometal plating layer or the second electrometal plating layer can be minimized, the dimensional stability (registration) of the substrate is improved by reducing the mechanical polishing amount. There is an effect that a method for manufacturing a multilayer printed circuit board can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of a multilayer printed circuit board according to Embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing the multilayer printed circuit board illustrated in FIG.

FIG. 3 is a cross-sectional view illustrating a method of manufacturing the multilayer printed circuit board illustrated in FIG.

FIG. 4 is a cross-sectional view illustrating a method for manufacturing the multilayer printed circuit board illustrated in FIG.

FIG. 5 is a cross-sectional view illustrating a method for manufacturing the multilayer printed circuit board illustrated in FIG.

6 is a diagram showing a comparison between the multilayer printed circuit board shown in FIG. 1 and another evaluation example.

FIG. 7 is a cross-sectional view showing a configuration for comparison between the multilayer printed board shown in FIG. 1 and another evaluation example.

FIG. 8 is a cross-sectional view illustrating a method of manufacturing the multilayer printed circuit board illustrated in FIG.

FIG. 9 is a sectional view showing a configuration of a multilayer printed circuit board according to Embodiment 1 of the present invention.

FIG. 10 is a cross-sectional view showing a configuration of a multilayer printed circuit board according to Embodiment 2 of the present invention.

11 is a cross-sectional view illustrating a method for manufacturing the multilayer printed circuit board illustrated in FIG.

FIG. 12 is a cross-sectional view illustrating a method of manufacturing the multilayer printed circuit board illustrated in FIG.

13 is a cross-sectional view illustrating a method for manufacturing the multilayer printed circuit board illustrated in FIG.

FIG. 14 is a cross-sectional view illustrating a method for manufacturing a conventional multilayer printed circuit board.

FIG. 15 is a cross-sectional view illustrating a method for manufacturing a conventional multilayer printed circuit board.

FIG. 16 is a cross-sectional view illustrating a method for manufacturing a conventional multilayer printed circuit board.

FIG. 17 is a cross-sectional view illustrating a method for manufacturing a conventional multilayer printed circuit board.

FIG. 18 is a cross-sectional view illustrating a method for manufacturing the multilayer printed circuit board of Conventional Example 1.

FIG. 19 is a cross-sectional view illustrating a method for manufacturing the multilayer printed circuit board of Conventional Example 1.

[Explanation of symbols]

26 printed circuit board, 27 first conductor layer, 28, 3
9, 41 first insulating layer, 29 first opening, 30,
56 second insulating layer, 31, 57 second opening, 3
2,58 third opening, 33,59 second conductor layer,
34 plating catalyst layer, 35 electroless copper plating layer, 36,
36a, 36b electroplated copper layer, 37, 38 roughened surface, 46 third insulating layer, 47 fourth opening, 48
Fourth insulating layer, 49 fifth opening, 50 sixth opening, 51 third conductor layer, 60 first plating catalyst layer,
61 first electroless copper plating layer, 62 first electrolytic copper plating layer, 63 lower conductor layer, 64 second plating catalyst layer, 65 second electroless copper plating layer, 66 third electrolytic copper plating layer , 67 Upper conductor layer.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yasuo Kawashima 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Atsushi Tanaka 2-3-2 Marunouchi, Chiyoda-ku, Tokyo 3 (72) Inventor Yoichi Kitamura 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation

Claims (13)

[Claims] 1. A printed circuit board on which a first conductor layer is formed, a first insulating layer provided on the printed circuit board with a first opening reaching the first conductor layer, and a first insulating layer. On the layer,
A second insulating layer having a second opening communicating with the first opening and a third opening having a bottom extending only above the first insulating layer; and the first to third openings. A plating catalyst layer comprising a second conductor layer embedded in the portion, wherein the second conductor layer is formed so as to cover the side and bottom surfaces of the first to third openings; A multilayer comprising: an electroless metal plating layer formed to cover the plating catalyst layer; and an electrometal plating layer formed to cover the electroless metal plating layer. Printed board. 2. A printed circuit board on which a first conductor layer is formed; a first insulating layer provided on the printed board with a first opening reaching the first conductor layer; On the layer,
A second insulating layer having a second opening communicating with the first opening and a third opening having a bottom extending only above the first insulating layer; and the first to third openings. A second conductor layer embedded in the portion, wherein the first opening and the second conductor layer in the second opening are formed so as to cover side surfaces and a bottom surface of the first opening. Formed first plating catalyst layer, a first electroless metal plating layer formed so as to cover the first plating catalyst layer, and a first electroless metal plating layer formed so as to cover the first electroless metal plating layer. And a second layer formed so as to cover the side surfaces of the second opening and the first electric metal plating layer and to cover the first electric metal plating layer. Plating catalyst layer, and second electroless metal plating formed so as to cover the second plating catalyst layer When made in six layers of the three layers of the second electric metal plating layer formed to cover the second electroless metal plating layer above the second of the inner third opening
The second plating catalyst layer formed so as to cover the side and bottom surfaces of the third opening;
The second electroless metal plating layer formed so as to cover the plating catalyst layer, and the second electrometallic plating layer formed so as to cover the second electroless metal plating layer. A multilayer printed circuit board comprising three layers. 3. An insulating layer having an opening communicating with the second opening is formed on the second opening in which the second conductor layer is embedded, and the conductor embedded in the opening is formed. 3. The method according to claim 1, wherein a layer is formed, and the conductive layer is electrically connected to the second conductive layer.
2. The multilayer printed circuit board according to item 1. 4. The surface of the first insulating layer and the surface of the second insulating layer which are in contact with the second conductor layer, wherein a roughened surface is formed. A multilayer printed circuit board according to any one of the above. 5. The roughened surface formed on the first insulating layer,
The multilayer printed board according to claim 4, wherein the multilayer printed board is rougher than a roughened surface formed on the second insulating layer. 6. An average particle diameter of a filler contained in a resin constituting a first insulating layer is larger than an average particle diameter of a filler contained in a resin constituting a second insulating layer. A multilayer printed circuit board according to claim 5. 7. The average particle diameter of the filler contained in the resin constituting the first insulating layer is in the range of 1 to 20 μm, and the average particle diameter of the filler contained in the resin constituting the second insulating layer is 7. The multilayer printed circuit board according to claim 6, wherein the diameter is in a range of 0.01 to 5 µm. 8. A first insulating layer is applied on a printed circuit board on which a first conductive layer is formed, and a desired region of the first insulating layer is opened to reach the first conductive layer, Forming a first opening, applying a second insulating layer on the first insulating layer, and in a desired region of the second insulating layer until reaching the first opening; Forming a second opening and a third opening, respectively, until the bottom portion reaches only above the first insulating layer; and filling the first through third openings with the second opening. Forming a second conductor layer by sequentially forming a plating catalyst layer, an electroless metal plating layer, and an electrometal plating layer by a plating method so as to cover the upper surface of the second conductor layer; Is mechanically polished to remove and expose the second conductor layer on the upper surface of the second insulating layer. A method of manufacturing a multilayer printed circuit board. 9. The method according to claim 1, further comprising the step of forming the first to third openings and roughening the first insulating layer and the second insulating layer before forming the second conductor layer. The method for manufacturing a multilayer printed circuit board according to claim 8, wherein: 10. A first insulating layer is applied on a printed circuit board on which a first conductive layer is formed, and a desired region of the first insulating layer is opened to reach the first conductive layer, A step of forming a first opening, and a first plating catalyst layer and a first electroless metal plating layer formed by a plating method so as to fill the first opening and cover the first insulating layer. Forming a lower conductor layer by sequentially forming a first electrometal plating layer and mechanically polishing the lower conductor layer to remove and expose the lower conductor layer on the upper surface of the first insulating layer. And a step of applying a second insulating layer on the first insulating layer, and in a desired area of the second insulating layer, the first opening, that is, the lower conductive layer, and a bottom portion. Are respectively opened to reach only the first insulating layer, and the second and third openings are formed. Forming a second portion and a second electroless plating layer by a plating method so as to fill the second opening and the third opening and cover the second insulating layer. Forming a metal plating layer and a second electrometal plating layer sequentially to form an upper conductor layer; mechanically polishing the upper conductor layer to remove the upper conductor layer on the upper surface of the second insulating layer; Forming a second conductor layer composed of the lower conductor layer and the upper conductor layer. 11. A step of forming a first opening and roughening a first insulating layer before forming a lower conductive layer, forming a second and third opening, and forming an upper conductive layer. The method of manufacturing a multilayer printed circuit board according to claim 10, further comprising a step of roughening the first insulating layer and the second insulating layer before forming the layer. 12. The method for manufacturing a multilayer printed circuit board according to claim 8, wherein the plating method of the electric metal plating layer, the first electric metal plating layer, or the second electric metal plating layer is performed by a pulse plating method. Alternatively, a method for manufacturing a multilayer printed circuit board, wherein a periodic inversion current plating method is used. 13. The method according to claim 12, wherein the electrometal plating layer, the first electrometal plating layer, or the second electrometal plating layer is chemically etched to a desired thickness and then mechanically polished. A method for manufacturing a multilayer printed circuit board according to the above.