JP2006032462A - Wiring formation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming a wiring layer by embedding a conductive layer in the groove of a resin layer by a damascene method using mechanical polishing without causing any failures. <P>SOLUTION: After forming the resin layer 18 on a substrate 10, a structure is formed for which the groove 18x is formed in the resin layer 18, and a protective metal layer 20 (Ni or TiW) is formed on the resin layer 18. Then, after forming the conductive layer 22 (Cu) for filling the groove 18x inside the groove 18x and on the protective metal layer 20, by utilizing the protective metal layer 20 as a polishing protective layer and mechanically polishing the conductive layer 22, the conductive layer 22 is embedded inside the groove 18x, and a wiring layer 24 is obtained. Then, the protective metal layer 20 is removed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a wiring forming method, and more particularly to a wiring forming method applicable to damascene wiring formation or via post formation in the manufacture of circuit boards and the like.

  Conventionally, there is a method of forming a wiring layer used for a circuit board or the like by a process similar to a damascene method. In such a conventional process for forming a wiring, first, after a groove is formed in the interlayer resin layer on the substrate, a conductive layer (Cu layer) filling the groove is formed on the interlayer resin layer. Thereafter, the conductive layer is polished by mechanical polishing such as buffing until the interlayer resin layer is exposed, and the conductive layer is buried in the groove to form a wiring layer.

In addition, in a conventional circuit board or the like, via posts standing in the interlayer resin layer are provided in order to interconnect multilayer wirings or connect external connection terminals. As an example of a method for forming such a via post, first, a via post (Cu) is erected on a connection portion of a wiring layer formed on a substrate, and then the via post is embedded to cover the via post. An interlayer resin layer is formed. Thereafter, the interlayer resin layer is polished by mechanical polishing such as buffing, leaving the interlayer resin layer in the lateral direction of the via post and exposing the upper surface of the via post.
JP 2000-216111 A

  However, in the mechanical polishing such as buffing used in the step of polishing the conductive layer (Cu layer) as described above, the polishing rate depends on the hardness of the material to be polished, and the material with lower hardness (soft) Tends to be easily polished. For this reason, as shown in FIG. 1A, the interlayer resin layer 102 having a lower hardness than the Cu layer 100 is polished more than the Cu layer 100, and the interlayer resin layer 102 sinks from the upper surface of the Cu layer 100. Often formed.

  Further, in mechanical polishing such as buff polishing, due to variations in the polishing rate within the substrate, over polishing occurs depending on the location of the substrate, and not only the interlayer resin layer 102 but also the Cu layer 100 sinks, and the required film A thick wiring layer may not be obtained.

  In addition, as shown in FIG. 2, in the step of polishing the interlayer resin layer 202 on the via post 200 when forming the via post 200, excessive polishing is performed in the substrate due to variations in the polishing rate in the mechanical polishing substrate. There is a problem that the height of the via post 200 varies in the substrate.

  The present invention was created in view of the above problems, and a wiring forming method capable of forming a wiring layer by embedding a conductive layer in a groove of a resin layer by a damascene method using mechanical polishing without causing any problems The purpose is to provide. Also provided is a wiring forming method for forming a via post that is embedded in a resin layer and mechanically polishing a resin layer that covers the via post to expose the upper surface, and the wiring forming method can suppress variation in the height of the via post in the substrate. The purpose is to do.

  In order to solve the above problems, the present invention relates to a wiring forming method, a step of forming a resin layer on a substrate, a groove is formed in the resin layer, and a protective metal layer is formed on the resin layer. Forming a structured structure, forming a metal layer for embedding the groove in the groove and on the protective metal layer, and mechanically polishing the metal layer using the protective metal layer as a polishing protective layer. And polishing to form a wiring layer by embedding the metal layer in the groove, and removing the protective metal layer on the resin layer.

  In the present invention, first, a structure in which a resin layer is formed on a substrate, a groove for forming a wiring layer is formed in the resin layer, and a protective metal layer serving as a polishing protection layer is formed on the resin layer. Form. In a preferred embodiment of this step, after forming the protective metal layer on the resin layer, the protective metal layer and the resin layer may be processed to form a groove, or the groove may be formed after forming the groove in the resin layer. A protective metal layer may be formed on the inside and on the resin layer.

  Next, a conductive layer (such as a Cu layer) having a thickness for embedding the groove of the resin layer is formed in the groove and on the protective metal layer. Thereafter, the conductive layer is polished by mechanical polishing such as buff polishing until the upper surface of the protective metal layer is exposed, and the conductive layer is buried in the groove to obtain a wiring layer.

  At this time, since a protective metal layer that functions as a polishing protective layer is formed on the resin layer having a relatively high polishing rate, the resin layer is protected from polishing by the protective metal layer. However, there is no possibility that the resin layer is polished.

  Therefore, the pattern loss of the wiring layer accompanying the sinking of the resin layer is prevented, and a wiring layer having a required film thickness can be formed. Furthermore, since variations in the film thickness of the wiring layer and the resin layer are suppressed over the entire substrate, a highly reliable circuit board and the like can be manufactured.

  Further, in order to solve the above-mentioned problems, the present invention relates to a wiring forming method, a step of forming a wiring layer on a substrate, a standing metal layer on a required portion of the wiring layer, and a protective metal layer on the upper surface side. Forming a via post provided; embedding a step of the via post; forming a resin layer covering the via post; and utilizing the protective metal layer as a polishing protective layer, mechanically polishing the resin layer And a step of exposing the protective metal layer on the via post by polishing.

  In the present invention, first, a via post having a protective metal layer provided on the upper surface side is erected and formed on the wiring layer on the substrate, and then a resin layer that fills the step of the via post and covers the via post is formed. The Then, using the protective metal layer as a polishing protective layer, the resin layer is polished by mechanical polishing until the protective metal layer on the via post is exposed, forming a via post embedded in the resin layer with the upper surface exposed Is done.

  By doing so, even if overpolishing is performed when the resin layer is polished, there is no possibility that the via post is unnecessarily scraped, and the problem that the height of the via post varies in the substrate is solved.

  In the above-described invention, the protective metal layer is made of a conductive layer (Cu layer) to be polished and a metal whose hardness is higher than that of the resin layer. Examples of such a metal include cobalt (Co), nickel (Ni ), Titanium tungsten (TiW), titanium (Ti) or tungsten (W) is preferably used.

  Patent Document 1 describes that the wettability between the via post and the solder ball is improved by sequentially plating nickel, palladium, and gold on the copper plating portion standing on the wiring pattern. . However, there is no description of forming a resin layer covering the via post and using the plated layer of the via post as a protective metal layer when polishing the resin layer, and does not suggest the configuration of the present invention.

  As described above, according to the present invention, a wiring layer can be accurately and stably formed in a wiring forming method using a process similar to a damascene method using mechanical polishing. Further, in the wiring formation method in which the via post is formed by scraping the resin layer covering the via post by mechanical polishing, variation in the height of the via post in the substrate can be prevented. As described above, various substrates including wiring layers and via posts can be manufactured with high yield and high reliability.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

(First embodiment)
3 to 6 are sectional views showing the wiring forming method according to the first embodiment of the present invention.

  In the present embodiment, an example in which build-up wiring is formed on a core substrate will be described. First, a core substrate 10 having a structure as shown in FIG. The core substrate 10 is provided with a through hole 10x penetrating therethrough, and the through hole 10x is filled with a conductor 11. A first wiring layer 12 is formed on the upper surface of the core substrate 10, and the first wiring layer 12 is connected to a wiring layer (not shown) on the back side of the core substrate 10 through the conductor 11 in the through hole 10 x. Has been.

  Furthermore, a conductive via post 16 connected to the first wiring layer 12 is provided upright. A first interlayer resin layer 14 is formed in the lateral direction of the via post 16 to fill the step, and the upper surface of the via post 16 is exposed.

  Next, a method for forming the second wiring layer electrically connected to the first wiring layer 12 and the via post 16 will be described.

  As shown in FIG. 3B, a second interlayer resin layer 18 is formed on the first interlayer resin layer 14 and the via posts 16. The second interlayer resin layer 18 is formed by attaching a resin film such as an epoxy resin, a polyimide resin, or a polyphenylene ether resin. Alternatively, the resin layer may be formed by spin coating or printing.

  Subsequently, as shown in FIG. 3B, a protective metal layer 20 is formed on the second interlayer resin layer 18. As the protective metal layer 20, a metal layer made of cobalt (Co), nickel (Ni), titanium tungsten (TiW), titanium (Ti), tungsten (W), or the like is used. The protective metal layer 20 formed of such a metal has a hardness higher than the hardness of the second interlayer resin layer 18 and the Cu layer that becomes the wiring layer, and when the wiring layer is formed by polishing the Cu layer later. Furthermore, it functions as a polishing protective layer that protects the second interlayer insulating layer 18 from polishing.

  As a method for forming the protective metal layer 20, a sputtering method or a plating method is employed. The film thickness of the protective metal layer 20 is appropriately adjusted according to the metal material and polishing conditions. For example, when Ni is used, the film thickness is set to about 2 μm.

  Next, as shown in the upper diagram of FIG. 3C, a resist film (not shown) provided with an opening in a portion corresponding to the second wiring layer to be formed next is formed by photolithography on the protective metal layer 20. After the above patterning, the protective metal layer 20 and the second interlayer resin layer 18 are etched using this resist film as a mask. Thereby, a groove 18x having a depth reaching the upper surface of the via post 16 and a shape corresponding to the second wiring layer is formed.

  In this way, the protective metal layer 20 is selectively left on the second interlayer resin layer 18 in a region where the second wiring layer is not formed (portion excluding the groove 18x).

  Alternatively, as shown in the lower diagram of FIG. 3C, the protective metal layer 20 may be formed not only on the second interlayer resin layer 18 but also on the inner surface of the groove 18x. In this case, without forming the protective metal layer 20 in the step of FIG. 3B, only the second interlayer resin layer 18 is processed to form the groove 18x, and then the inner surface of the groove 18x and the second interlayer are formed. The protective metal layer 20 may be formed on the insulating layer 18 by sputtering or electroless plating.

  Then. As shown in FIG. 4A, a seed layer (not shown) is formed by sputtering or electroless plating on the inner surface of the groove 18x and the protective metal layer 20 in the upper diagram of FIG. A conductive layer 22 having a film thickness for embedding the groove 18x is formed on the seed layer by electrolytic plating using the layer as a plating power feeding layer. A copper (Cu) layer is preferably used as the seed layer (not shown) and the conductive layer 22. As a result, a conductive layer (Cu layer) 22 is formed on the second interlayer insulating layer 18 via the protective metal layer 20.

  Next, as shown in FIGS. 4A and 4B, the conductive layer 22 is polished by buffing, tape polishing, or mechanical polishing such as a grinder until the upper surface of the protective metal layer 20 is exposed. A conductive layer 22 is embedded in 18x to obtain a second wiring layer 24. FIG. 4A shows an example in which the conductive layer 22 is polished by buff polishing in which a buff 19 having abrasive grains fixed on its outer peripheral surface is rotated at a high speed to polish a workpiece. At this time, as shown in FIG. 4B, since the protective metal layer 20 having a hardness higher than that of the conductive layer (Cu layer) 22 to be polished is formed on the second interlayer resin layer 18, the overpolishing is performed. Even if it performs, grinding | polishing stops substantially with the protective metal layer 20a. Thus, since the second interlayer resin layer 18 having a relatively high polishing rate is protected from polishing by the protective metal layer 20a, the second interlayer resin layer 18 is formed by sinking from the upper surface of the second wiring layer 24. No fear.

  As a result, the sinking of the conductive layer 22 is also suppressed, so that the conductive layer 22 having a required film thickness can be left in the groove 18x, and the pattern loss of the second wiring layer 24 is prevented. The In addition, variations in the film thickness of the second wiring layer 24 in the core substrate 10 are also suppressed.

  Thereafter, as shown in FIG. 5, the protective metal layer 20 is selectively removed with respect to the second wiring layer 24 and the second interlayer resin layer 18.

  As shown in FIG. 6, when the structure in which the protective metal layer 20 is formed also in the groove 18x of the second interlayer resin layer 18 as shown in the lower diagram of FIG. The protective metal layer 20 is finally left also on the inner surface of the groove 18 x of the resin layer 18 to become a part of the second wiring layer 24.

  The inventor of the present application polished the Cu layer to be the wiring layer and the Ni layer as the protective metal layer under the same buffing conditions, and compared the polishing amounts of the Cu layer and the Ni layer. The results are shown in Table 1. The amount of each polishing is determined by the difference in weight before and after polishing the substrate on which the Cu layer and the Ni layer are plated, the amount of polishing of the Cu layer is defined as 100%, and the amount of polishing of the Ni layer is a ratio of the amount of polishing of the Cu layer Expressed in Further, a comparison was made between the case where the buffing number of the buff (rotatable polishing part with abrasive grains fixed on the outer peripheral surface) was # 600 and # 1200. The polishing current (A) corresponds to the strength with which the buff is pressed against the workpiece.

  As shown in Table 1, when the abrasive grain number was # 600 and the polishing current was 1A, the polishing amount of the Ni layer was 64% of the polishing amount of the Cu layer. When the abrasive grain number was # 600 and the polishing current was 2 A, the polishing amount of the Ni layer was 30% of the polishing amount of Cu. Furthermore, when the abrasive grain number was # 1200, the dependency of the polishing current was low, and the polishing amount of the Ni layer was about 25% of the polishing amount of Cu. When the buff's abrasive grain size increases (when the abrasive grains become finer), the polishing amount of the Ni layer tends to decrease significantly compared to the polishing amount of the Cu layer, which is confirmed to be effective as a polishing protective layer. .

  Even when the above-described metals (Co, TiW, Ti, W) other than the Ni layer are used as the protective metal layer, the amount of polishing is smaller than that of the Cu layer and functions as a similar polishing protective layer.

以上のように、本実施形態の配線形成方法では、まず、第２層間樹脂層１８に第２配線層２４を形成するための溝１８ｘが形成され、かつ第２層間樹脂層１８上に保護金属層２０が形成された構造体を形成する。このとき、溝１８ｘの内面にも保護金属層２０が形成されていてもよい。

As described above, in the wiring forming method of this embodiment, first, the groove 18x for forming the second wiring layer 24 is formed in the second interlayer resin layer 18, and the protective metal is formed on the second interlayer resin layer 18. A structure in which the layer 20 is formed is formed. At this time, the protective metal layer 20 may also be formed on the inner surface of the groove 18x.

  Next, a conductive layer (Cu layer) 22 having a thickness for embedding the groove 18 x of the second interlayer resin layer 18 is formed on the groove 18 x and the protective metal layer 20. Thereafter, the conductive layer 22 is polished by mechanical polishing such as buffing until the protective metal layer 20 is exposed, and the conductive layer 22 is embedded in the groove 18x, whereby the second wiring layer 24 is obtained.

  At this time, since the protective metal layer 20 is formed on the second interlayer resin layer 18, the protective metal layer 20 functions as a polishing protective layer for the second interlayer insulating layer 18, and even if overpolishing is performed, There is no possibility that the two-layer resin layer 18 is polished.

  Therefore, sinking of the second interlayer resin layer 18 and accompanying pattern loss of the second wiring layer 24 are prevented, and a wiring layer having a required film thickness can be formed. In this way, variations in the film thickness of the wiring layer and the interlayer resin layer can be suppressed over the entire core substrate, so that a highly reliable circuit board can be manufactured.

(Second Embodiment)
7 to 9 are sectional views showing a wiring forming method according to the second embodiment of the present invention. The second embodiment relates to a method for forming a via post that is a part of a wiring layer, taking as an example a form for forming a via post of a wafer level package in which a CSP (chip size package) manufacturing process is performed on a wafer. explain.

  In the wiring forming method according to the second embodiment of the present invention, first, a semiconductor wafer 30 having a structure as shown in FIG. 7A, a predetermined element such as a transistor and a multilayer wiring (not shown) are formed on a semiconductor wafer 30, and an insulating layer 32 related to the multilayer wiring, an electrode pad 34 provided thereon, A passivation film 36 having an opening 36x provided on the pad 34 and a wiring layer 38 connected to the electrode pad 34 and extending on the passivation film 36 are shown.

  A plurality of electrode pads 34 are arranged in a peripheral form at the periphery of each chip region of the semiconductor wafer 30, and these electrode pads 34 are re-wired by the wiring layer 38, and a via post (described later) standing on the wiring layer 38. Are arranged in an area array type in each chip region.

  Subsequently, as shown in FIG. 7B, a seed layer 40 made of Cu or the like is formed on the wiring layer 38 and the passivation film 36 by sputtering or electroless plating. Next, as shown in FIG. 7C, a resist film 44 in which an opening 44 x is provided on the connection portion where the via post on the wiring layer 38 is disposed is patterned on the seed layer 40.

  Next, as shown in FIG. 7D, the opening 46x of the resist film 44 is filled with a conductor 46 made of Cu or the like by electrolytic plating using the seed layer 40 as a plating power feeding layer. Further, as shown in FIG. 8A, a protective metal layer 50 is selectively formed on the conductor 46 by electrolytic plating or electroless plating. The protective metal layer 50 functions as a polishing protective layer that prevents polishing of the conductor (Cu) 46 of the via post 52 when the interlayer resin layer that covers the via post 52 is mechanically polished later. As the protective metal layer 50, a metal such as nickel (Ni), titanium tungsten (TiW), titanium (Ti), tungsten (W) is used as in the first embodiment.

  Next, as shown in FIG. 8B, after removing the resist film 44, the seed layer 40 is etched using the conductor 46 and the protective metal layer 50 as a mask, so that the seed layer 40, the conductor 46 and the protection are protected. A via post 52 composed of the metal layer 50 is obtained. In this way, via posts 52 are formed standing on the wiring layer 38 and connected thereto. As described above, the via posts 52 are arranged in an area array type in each chip region.

  Thereafter, as shown in FIG. 8C, a resin layer 54 covering the via post 52 is formed on the upper surface side of the core substrate 10 while embedding the step of the via post 52. The resin layer 54 is formed by attaching a resin film such as an epoxy resin, a polyimide resin, or a polyphenylene ether resin. Alternatively, the resin layer may be formed by spin coating or printing.

  Next, as shown in FIG. 9A, the resin layer 54 is polished by mechanical polishing such as buff polishing, tape polishing, or grinder, so that the resin layer 54 is flattened and the upper surface of the protective metal layer 50 is exposed. Let At this time, since the protective metal layer 50 functioning as a polishing protection layer is provided on the via post 52, the conductor (Cu) 46 of the via post 52 is unnecessarily polished even if over-polished. Absent.

  Accordingly, there is no portion where the via post 52 is excessively polished over the entire semiconductor wafer 30, and the problem that the height of the via post 52 varies in the semiconductor wafer 30 is solved. At this time, since the resin layer 54 is not protected by the protective metal layer 50, it is important to set the horizontal movement speed of the buff rotating when performing the buffing to a high speed. This eliminates the problem that the resin layer 54 sinks unnecessarily.

  Subsequently, as shown in FIG. 9B, the protective metal layer 50 on the via post 52 is selectively removed with respect to the conductor 46 and the resin layer 54. As described above, the via post 52 erected on the wiring layer 38 is formed so as to be embedded in the resin layer 54 with its upper surface exposed. Thereafter, as shown in FIG. 9C, solder balls or the like are mounted on the via posts 52 to form the external connection terminals 56. When this process is completed, a semiconductor wafer 30 having a CSP structure in which film formation or processing related to the CSP structure is performed in a wafer state is obtained. Thereafter, the semiconductor wafer 30 is diced into individual semiconductor chips having a wafer level CSP structure.

  In addition, when there is a possibility that a problem occurs in the electrical connection with the external connection terminal 56, it is preferable to remove the protective metal layer 50, but it is not always necessary to remove the protective metal layer 50.

  As described above, when the via post 52 embedded in the resin layer 54 is formed with the upper surface exposed by mechanical polishing of the resin layer 54 formed on the via post 52, a protective metal is formed on the uppermost portion of the via post 52. By providing the layer 50, there is no possibility that the via post 52 is unnecessarily polished even if overpolishing is performed, and the problem that the height of the via post 52 varies in the semiconductor wafer 30 is solved.

  In the first embodiment described above, the via post 16 in FIG. 3 may be formed by a method similar to the method for forming the via post 52 in the second embodiment described above. In this way, by combining the wiring formation method of the first embodiment and the second embodiment, n layers (n is an integer of 1 or more) on one side or both sides of the core substrate 10 of the first embodiment. The build-up wiring may be formed.

(Third embodiment)
FIG. 10 is a cross-sectional view showing a state of a connection portion of a circuit board according to related technology, and FIGS.

  As shown in FIG. 10, in the related art circuit board, a wiring layer 302 including a connection portion 302a is formed on the uppermost resin layer 300 of a core substrate (not shown), and on the connection portion 302a. A solder resist film 304 provided with an opening 304x is formed. A bump of a semiconductor chip (not shown) is formed on the connection portion 302a of the wiring layer 302 by a printing method, a plating method, a ball mounting method, or the like.

  In semiconductor chips such as CPUs, the pitch of bumps has been reduced with an increase in the number of I / Os. As the pitch becomes narrower (200 μm or less), the bump height is increased to avoid electrical shorts between the bumps. It is necessary to reduce the height. When the bump height of the semiconductor chip is lowered, in the method of providing the solder resist film 304 protruding upward from the connection portion 302a of the wiring layer 302 as described above, the bump of the semiconductor chip is caused to be affected by the step of the solder resist film 304. There is a possibility that the connection part 302a of the board cannot be connected with high reliability.

  By using the wiring forming method of the third embodiment of the present invention, such a problem is solved.

  In the wiring forming method according to the third embodiment of the present invention, first, as shown in FIG. 11A, a required build-up wiring (not shown) is formed on a core substrate (not shown), and the uppermost insulating layer is formed. A structure having a wiring layer 62 formed on 60 is prepared.

  Thereafter, as shown in FIG. 11B, a seed layer 64 is formed on the wiring layer 62 and the insulating layer 60 by the same method as in the second embodiment, and then an opening is formed on the connection portion of the wiring layer 62. A resist film 66 provided with 66 x is formed on the seed layer 64. Subsequently, a conductor 68 made of Cu or the like is formed in the opening 66x of the resist film 66 by electrolytic plating. Further, the protective metal layer 70 is selectively formed on the conductor 68 by the same method as in the second embodiment.

  Next, as shown in FIG. 11C, after removing the resist film 66 by the same method as in the second embodiment, the seed layer 64 is etched using the conductor 68 and the protective metal layer 70 as a mask. As a result, a via post 72 composed of the seed layer 64, the conductor 68 and the protective metal layer 70 is obtained.

  Subsequently, as shown in FIG. 11 (d), a solder resist film 74 (resin layer) that fills the step of the via post 72 and covers the via post 72 is formed. As a method for forming the solder resist film 74, a resin film may be attached, or a resin layer may be formed by a spin coating method, printing, or the like.

  Next, as shown in FIG. 12A, the solder resist film 74 is polished by mechanical polishing such as buff polishing, so that the solder resist film 74 is flattened and the upper surface of the protective metal layer 70 is exposed. At this time, as in the second embodiment, since the protective metal layer 70 that functions as a polishing protection layer is formed on the uppermost portion of the via post 72, the conductor 68 of the via post 72 is unnecessarily polished. In addition, the height of the via post 72 can be prevented from varying over the entire circuit board.

  Thereafter, as shown in FIG. 12B, the exposed protective metal layer 70 is selectively removed with respect to the solder resist film 74 and the conductor 68. Note that the protective metal layer 70 is not necessarily removed.

  As described above, the via post 72 which is erected on the wiring layer 62 and electrically connected thereto is buried in the solder resist film 74 with its upper surface exposed. The upper surface of the via post 72 becomes a connection portion 72a to which a bump of an electronic component such as a semiconductor chip is connected.

  In the circuit board formed by the wiring forming method of the present embodiment, the solder resist film 74 does not protrude upward from the connection portion 72a of the via post 72, but the upper surface of the solder resist film 74 is connected to the connection portion 72a of the via post 72. It is flattened with substantially the same surface. Therefore, even if the bump height is reduced by narrowing the bump pitch of the semiconductor chip, unlike the related technology described above, the bump of the electronic component is connected to the circuit board without being affected by the step of the solder resist film. It becomes possible to connect to the portion 72a with high reliability, whereby the reliability of the circuit board on which the electronic component is mounted can be improved.

FIGS. 1A and 1B are cross-sectional views (part 1) showing problems of the wiring forming method according to the prior art. FIG. 2 is a cross-sectional view (part 2) showing a problem of the wiring forming method according to the prior art. 3A to 3C are cross-sectional views (part 1) showing the wiring forming method according to the first embodiment of the present invention. 4A and 4B are sectional views (No. 2) showing the wiring forming method according to the first embodiment of the present invention. FIG. 5 is a sectional view (No. 3) showing the wiring forming method according to the first embodiment of the present invention. FIG. 6 is a sectional view (No. 4) showing the wiring forming method according to the first embodiment of the present invention. 7A to 7D are cross-sectional views (part 1) showing the wiring forming method according to the second embodiment of the present invention. 8A to 8C are cross-sectional views (part 2) showing the wiring forming method according to the second embodiment of the present invention. 9A to 9C are cross-sectional views (part 3) showing the wiring forming method according to the second embodiment of the present invention. FIG. 10 is a cross-sectional view showing a state of a connection portion of a circuit board according to related technology. 11A to 11D are cross-sectional views (part 1) showing the wiring forming method according to the third embodiment of the present invention. 12A and 12B are cross-sectional views (part 2) showing the wiring forming method of the third embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Core substrate, 10x ... Through hole, 11, 46, 68 ... Conductor, 12 ... 1st wiring layer, 14 ... 1st interlayer resin layer, 16, 52, 72 ... Via post, 18 ... 2nd interlayer resin layer, DESCRIPTION OF SYMBOLS 19 ... Buff, 18x, 36x, 44x ... Opening, 20, 50, 70 ... Protective metal layer, 24 ... Second wiring layer, 30 ... Semiconductor wafer, 32, 60 ... Insulating layer, 34 ... Connection pad, 36 ... Passivation Film, 38, 62 ... wiring layer, 40, 64 ... seed layer, 44 ... resist film, 56 ... external connection terminal, 72a ... connection part, 74 ... solder resist film.

Claims (12)

Forming a resin layer on the substrate;
Forming a structure in which grooves are formed in the resin layer and a protective metal layer is formed on the resin layer;
Forming a conductive layer filling the groove in the groove and on the protective metal layer;
Using the protective metal layer as a polishing protective layer, mechanically polishing the conductive layer, thereby embedding the conductive layer in the groove to obtain a wiring layer;
And a step of removing the protective metal layer on the resin layer. The step of forming a structure in which grooves are formed in the resin layer and the protective metal layer is formed on the resin layer,
Forming the protective metal layer on the resin layer;
The wiring forming method according to claim 1, further comprising a step of forming the groove in a required portion of the protective metal layer and the resin layer. The step of forming a structure in which grooves are formed in the resin layer and the protective metal layer is formed on the resin layer,
Forming the groove in the resin layer;
The method for forming a wiring according to claim 1, further comprising: forming the protective metal layer on the inner surface of the groove and the resin layer. Forming a wiring layer on the substrate;
Forming a via post erected on the wiring layer and provided with a protective metal layer on the upper surface side;
A step of embedding a step of the via post and forming a resin layer covering the via post; and
And a step of exposing the protective metal layer on the via post by mechanically polishing the resin layer using the protective metal layer as a polishing protective layer. The step of forming the via post includes
Forming a seed layer covering the wiring layer;
Forming a resist film having an opening on a required portion of the wiring layer on the seed layer;
Forming a conductor in the opening of the resist film by electroplating using the seed layer as a plating power supply layer;
Selectively forming the protective metal layer on the conductor;
Removing the resist film;
The wiring formation method according to claim 4, further comprising: etching the seed layer using the conductor and the protective metal layer as a mask.   6. The wiring forming method according to claim 4, further comprising a step of removing the protective metal layer after the step of exposing the protective metal layer on the via post.   The wiring forming method according to claim 1, wherein a metal having a higher hardness than that of the conductive layer is used as the protective metal layer.   The wiring forming method according to claim 7, wherein the protective metal layer is made of any one of cobalt (Co), nickel (Ni), titanium tungsten (TiW), titanium (Ti), and tungsten (W). .   6. The wiring forming method according to claim 1, wherein the mechanical polishing is any one of buff polishing, tape polishing, and polishing by a grinder.   The wiring forming method according to claim 1, wherein the conductive layer is a copper layer, and the resin layer is an epoxy resin or a polyimide resin.   The wiring formation method according to claim 4, wherein the via post is made of copper, and the resin layer is an epoxy resin or a polyimide resin.   The wiring forming method according to claim 4, wherein the resin layer is a solder resist film, and an electronic component is electrically connected to an upper surface of the via post.

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