JPH11354931A - Electronic components integral-type multilayer substrate and its manufacture method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing an electronic component integral-type multilayer wiring board, where the misalignment between a pad at a substrate side and the electrode in such electronic components as a semiconductor element may not occur and the need for forming a solder bumps at the electrode of the electronic components are eliminated. SOLUTION: A manufacturing method successively includes an installation process A (step S.1), a first resin layer forming process B (S.2-S.7) for covering the surface of elements and tools with a first insulation resin layer, a first circuit layer forming process C (S.8-S.12), for forming a first circuit layer on the first resin layer, a second resin layer forming process D (S.13-S.20) for covering an area on the first circuit layer with a second insulation resin layer, a second circuit layer forming process E (S.1-S.25) for forming a second circuit layer on the second resin layer, and a stage F (S.28) for stripping the tools.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component-integrated multi-layer substrate in which a plurality of substrate layers are connected by interlayer connecting portions such as posts (metal columns) and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional method of manufacturing a build-up type wiring board will be described with reference to FIGS. Each figure is
For the sake of explanation, the magnification in the thickness direction, which is the vertical direction in the figure, is set to be larger than that in the width direction, which is the horizontal direction, and the film pressure of the conductor layer, the metal film, etc. is shown enlarged from the actual scale. FIG.

As shown in FIG. 23A, a copper foil 2 is formed on the surface of an insulating substrate 1 such as glass epoxy by plating or the like, and the surface is chemically or buffed with a chemical such as sulfuric acid containing hydrogen peroxide. Clean by mechanical polishing using, for example. Next, the dry film resist is thermocompression-bonded onto the copper foil 2, a mask for forming a circuit pattern is overlaid, exposed, and developed to leave the resist layer 3 only in a portion required as a circuit pattern (FIG. 23 (b) )). Subsequently, an unnecessary portion of the copper foil 2 is removed with an etching solution such as a copper chloride solution, an iron chloride solution, and a sulfuric acid solution containing hydrogen peroxide to form a circuit pattern (FIG. 2).
3 (c)), the resist layer 3 is removed (FIG. 23 (d)). Up to this point, it is the same as a normal single-layer wiring board.

[0004] Next, a post for connection to an upper layer substrate is formed by plating. First, as shown in FIG. 23E, a power supply film 4 for plating is formed by electroless plating over the entire surface of the substrate 1 on which a circuit pattern is formed, and a resist layer 5 for post plating is laminated thereon. FIG. 23 (f)). And
The resist layer 5 is exposed and developed to expose a conductor portion on the insulating substrate 1, that is, a part of the portion where the copper foil 2 is left, to form an opening 5a (FIG. 24 (g)). In this state, electricity is supplied to the power supply film 4 to electroplate the metal for the post, thereby forming the post 6 connected to the copper foil 2 in the opening 5a (FIG. 24 (h)).

Subsequently, the resist layer 5 is removed (FIG. 24).
(i)), using the post 6 as a mask, the power supply film 4 is removed by etching with an etching solution such as copper chloride or sulfuric acid containing hydrogen peroxide (FIG. 24 (j)). Then, a thermosetting insulating resin layer 7 filling the space between the lower substrate 1 and the upper substrate is applied onto the substrate 1 by printing or curtain coating, and is thermoset (FIG. 24 (k)). ).

The surface of the insulating resin layer 7 is polished by a buff to expose the post 6 to the end face (FIG. 25 (l)), and the entire surface of the exposed post 6 and the insulating resin layer 7 is covered with an upper layer circuit. The copper foil 8 is formed by using both electroless plating and electrolytic plating (FIG. 25 (m)). Subsequently, a resist layer 9 serving as a mask when etching the copper foil 8 is formed by applying, exposing, and developing a resist (FIG. 25 (n)), and the copper foil 8 is etched using the resist layer 9 as a mask. Form a circuit pattern
(FIG. 25 (o)).

After forming the circuit pattern, the resist layer 9 is removed (FIG. 26 (p)), and a nickel (Ni) layer 10 and a gold (Au) layer 11 are plated on the copper foil 8 left as a conductor. To form a pad (FIG. 26 (q)). Through the above steps, a build-up type wiring board including the lower circuit pattern and the upper circuit pattern is completed. FIG.
(r) shows a state in which the semiconductor element 20 is connected as an electronic component to the conductive portion of the upper circuit pattern. The solder bump 22 fixed to the electrode 21 of the element 20 is brought into contact with the pad,
After melting the solder bumps 22 by heat and pressure, the solder bumps 22 are cooled and solidified to fix the element to the build-up type substrate.

[0008]

However, in the above-described conventional manufacturing method, the space between the upper and lower circuit patterns is filled with the insulating resin layer 7, so that it is affected by environmental changes such as temperature and humidity. The position of the pad on the build-up type substrate side is easily
There is a problem that it is difficult to match the position of the zero electrode 21.

In this regard, it is conceivable to design the substrate in consideration of the influence of expansion and contraction as a margin. In this case, a margin must be secured with a considerable margin in consideration of a difference in expansion and contraction ratio due to a difference in kind and lot of a used material. However, with the miniaturization and high integration of devices, the electrode pitch of semiconductor devices tends to be finer, and there is a problem that the design with the above-mentioned margin cannot cope with miniaturization.

In the above-described manufacturing method, the semiconductor element 2
Since the step of forming the solder bumps 22 on the 0 electrodes 21 is required, the manufacturing cost is higher than an element that does not require solder bumps, and the cost of the entire electronic circuit configured by combining the substrate and the element is reduced. There is a problem of becoming high.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and does not cause a displacement between the position of a pad on a substrate and an electrode of an electronic component such as a semiconductor element. It is an object of the present invention to provide a multi-layer wiring board integrated with an electronic component which does not need to form a solder bump on the electrode and a method of manufacturing the same.

[0012]

According to the method of manufacturing an electronic component-integrated multilayer substrate according to the present invention, when an electronic component having an electrode formed on one surface serving as a substrate connection surface is used, the electronic component is fitted. An installation step of fitting an electronic component so that a board connection surface is exposed in the holding hole by using a jig having a holding hole formed therein, and a state in which the first interlayer connection portion is connected and formed to the electrode. A first resin layer forming step of covering a portion of the connection surface other than the interlayer connection portion and the surface of the jig with an insulating first resin layer; and forming a first resin layer connected to the first interlayer connection portion on the first resin layer. 1
A first circuit layer forming step of forming a circuit layer; and a second circuit connection step in which a second interlayer connection portion is connected and formed to a part of the first circuit layer.
A second resin layer forming step of covering a portion other than the interlayer connection portion with an insulating second resin layer, and a second circuit for forming a second circuit layer connected to the second interlayer connection portion on the second resin layer It is characterized in that it includes a layer forming step and a step of peeling the jig in order.

According to the above procedure, the interlayer connection portion, the resin layer, and the circuit layer are sequentially laminated from the element side on the basis of the electronic component in reverse to the conventional case, so that the positional relationship between the electronic component and the substrate side is reversed. Can be kept accurate. Further, since the interlayer connection portion can be formed by means such as plating, the connection reliability can be kept higher than when the electronic component and the circuit layer are connected by soldering.

As the first resin layer forming step, the following two methods can be considered. The first is a method in which a first layer post is first formed as a first interlayer connection portion on an electrode, and then a first resin layer is formed around the post. Second, a first resin layer is first formed on the entire surface of the substrate connection surface and the surface of the jig, an opening reaching the electrode is formed in the resin layer, and a first interlayer connection portion is formed in the formed opening. It is a method of forming. In the second method, the first interlayer connection portion can be formed as a solid post (metal column) that fills the opening, or can be formed as a film attached to the surface of the opening.

In the case of using the above-described second method, in the first circuit layer forming step, it is possible to use a conductor layer formed continuously and collectively at the time of forming the first interlayer connection portion.
That is, when the first interlayer connection is formed by plating, plating can be performed even on the first resin layer so that the conductor layer can be formed so as to be continuous with the first interlayer connection.

In the method of manufacturing an electronic component-integrated multilayer substrate according to the present invention, when an electronic component having leads or bumps formed on one surface serving as a substrate connection surface is used, the electronic component is fitted. Using a jig having a holding hole formed therein, an installation step of fitting an electronic component such that leads or bumps protrude from the holding hole, and covering the substrate connection surface and the surface of the jig with an insulating first resin layer. A first resin layer forming step, a first circuit layer forming step of forming a first circuit layer connected to a first interlayer connecting portion made of a lead or a bump on the first resin layer, and a first circuit layer forming step. A second resin layer forming step of covering a portion other than the second interlayer connection portion with an insulating second resin layer in a state where the second interlayer connection portion is connected and formed to the portion;
A second circuit layer forming step of forming a second circuit layer connected to the second interlayer connection portion on the second resin layer, and a step of peeling the jig are sequentially included.

In the second resin layer forming step, as in the description of the first resin layer forming step, a first method of forming a post as a second interlayer connecting portion first and thereafter forming a resin layer, And a second method of forming an opening after forming a second resin layer on the entire surface. Also,
In the case where the second method is used, the second circuit layer can be formed by using the conductor layer formed continuously and collectively at the time of forming the second interlayer connection portion.

Further, the electronic component-integrated multi-layer substrate according to the present invention is connected to a multi-layer build-up substrate in which a plurality of circuit layers are laminated via an insulating resin layer, and a surface circuit layer of the build-up substrate. In the structure provided with at least one electronic component, an interlayer connecting portion for electrically connecting both is formed between the electronic component and the surface circuit layer,
The surface circuit layer is covered with an insulating resin layer having a thickness substantially equal to the distance between the electronic component and the surface circuit layer in a portion other than the interlayer connection portion, and the electronic component is mounted on the substrate by the resin layer. It is characterized by being fixed.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a method for manufacturing an electronic component integrated type multi-layer substrate according to the present invention will be described. FIG.
Is a flowchart showing each process and step of the first embodiment, and FIGS. 2 to 7 are sectional views showing the structure of the multilayer substrate at each step.

The first embodiment is a method suitable for a case where a semiconductor element having an electrode pad formed on one surface serving as a substrate connection surface is used as an electronic component. First, an outline of the steps will be described with reference to FIG. 1, and then each step will be described in more detail with reference to cross-sectional views.

The manufacturing method according to the first embodiment includes an installation step A (S.1) of installing a semiconductor element in a holding hole of a jig;
A first resin layer forming step B (S.2 to S.7) for covering the surface of the element and the jig with an insulating first resin layer, and a first circuit for forming a first circuit layer on the first resin layer Layer forming step C (S.8 to S.12)
A second resin layer forming step D (S.13 to S.20) of covering the first circuit layer with an insulating second resin layer; and forming a second circuit layer on the second resin layer. Two-circuit layer forming step E (S.21 to S.25)
And a step F (S.28) of stripping the jig. When the circuit layer of the multi-layer substrate has two layers, the entire process is completed once through each of the steps A to F. However, in order to form three or more circuit layers, the second resin layer forming step D, only the second circuit layer forming step E is repeatedly executed.

In the installation step A, as shown in FIG. 2 (a), a flat jig 40 having a holding hole 41 into which the semiconductor element 30 is fitted is used, and a substrate connection on which an electrode pad 32 is formed is used. The semiconductor element 30 is fitted into the holding hole 41 so that the surface 31 is exposed (S.1). Since the jig 40 is peeled off from the semiconductor element 30 after completion, its surface, especially the holding hole 4
The inner surface 1 and the surface 42 are surface-processed with a highly releasable fluororesin or the like. In this example, only a single semiconductor element 30 is shown as an electronic component for simplicity.
The holding hole 41 is also single, but when mounting a plurality of electronic components, a jig having a holding hole formed for each component may be prepared.

In the first resin layer forming step B, the electrode pads 3
In a state where the first interlayer connection portion is connected and formed in 2, a portion other than the interlayer connection portion of the substrate connection surface and the surface of the jig are covered with the insulating first resin layer. In this example, the first resin layer forming step B is performed on the electrode pad 32 as a first interlayer connection portion.
Forming a layer post; and, after forming the post, forming a first resin layer around the post.

In the step of forming the first layer post, a photosensitive resist layer (plating resist) 50 covering the substrate connecting surface 31 and the surface 42 of the jig 40 is formed (S.2, FIG. 2).
(b)), exposure and post-forming positions of the resist layer 50 are formed.
An opening 50a reaching the electrode through the development process is formed (S.3, FIG. 2C). Subsequently, a first layer post 51 is formed in the opening 50a by plating (S.4, FIG. 3).
(d)). After the formation of the first layer post 51, the resist layer 50 is removed (S.5, FIG. 3E). As the metal for plating, metals such as copper, nickel, gold, silver, platinum and rhodium, or alloys of tin and gold, nickel and phosphorus, and the like can be used. Plating may be performed by electroplating if the electrode pad 32 can be energized, or electroless plating if it cannot be performed.

After forming the first layer post 51, a first resin layer 52 is formed on the entire surface of the jig 40 so as to cover the first layer post 51.
(S.6, FIG. 3 (f)). As the resin material, epoxy resin,
BT resin or the like can be used, and as a forming method, any means such as screen printing or application by a curtain coat method can be used. In step S.7, in order to expose the head of the first layer post 51 buried in the first resin layer 52, the surface of the first resin layer 52 is mechanically polished using a polishing device such as a buff or a belt sander. Grind. FIG. 4G shows a state after polishing.

In the first circuit layer forming step C, a first circuit layer is formed while being connected to the first layer post 51. First, a conductor layer 53 is formed on the first layer post 51 and the first resin layer 52 by plating (S.8, FIG. 4H). The conductor layer 53 is formed first by electroless copper plating, and subsequently by electrolytic copper plating using a formed copper foil. Subsequently, a photosensitive resist layer (etching resist) is formed on the conductor layer 53 (S.9), and the resist layer is exposed and developed in a predetermined pattern to form a resist layer on a conductive portion of the first circuit layer. Leave (S.10). Then, the conductor layer 53 in a region not covered with the resist layer is removed by etching (S.11), and only the necessary portion of the conductor layer 53 is left by removing the resist layer, thereby forming the first circuit layer. (S.12, Fig. 4
(i)).

The second resin layer forming step D includes the first circuit layer 53
Is a step of covering a portion other than the second interlayer connection portion with an insulating second resin layer in a state where the second interlayer connection portion is connected and formed on a part of the second interlayer connection portion. The method includes a step of forming a second layer post as a connecting portion, and a step of forming a second resin layer around the post after the formation of the post. In the step of forming the second layer post, a power supply film 54 is formed on the first circuit layer 53 and the first resin layer 52 (S.13, FIG. 5).
(j)), a photosensitive resist layer (plating resist) 55 is formed on the power supply film 54 (S.14), and the resist layer 5
An opening 55a that reaches the first circuit layer 53 through an exposure / development process is formed at the post formation position of No. 5 (S.15, FIG. 5 (k)).

Subsequently, a current is supplied to the power supply film 54 to perform electrolytic plating, thereby forming a second layer post 56 in the opening 55a (S.16, FIG. 5 (l)), and removing the resist layer 55.
(S.17), and the power supply film 54 is etched using the second layer posts 56 as a mask (S.18, FIG. 6 (m)). Next, a second resin layer 57 is formed on the first resin layer 52 so as to cover the formed second layer posts 56 and the first circuit layer 53 (S.19,
6 (n)), the second layer post 5 is polished by polishing the surface.
6 is searched (S.20, FIG. 6 (o)).

The second circuit layer forming step E includes the second resin layer 57
The step of forming a second circuit layer connected to the second layer post 56 thereon includes a step of forming a conductor layer and a step of etching by a lithographic technique. First, a conductor layer 58 connected to the second layer post 56 is formed on the second resin layer 57 by electroless copper plating and electrolytic copper plating.
(S.21, FIG. 7 (p)). A photosensitive resist layer (etching resist) is formed on the conductor layer 58 (S.22), and the resist layer is exposed and developed in a predetermined pattern to leave a resist layer in a conductive portion of the second circuit layer (S.22). S.23), the conductor layer 58 in a region not covered with the resist layer is removed by etching.
(S.24). After the etching, the resist layer is removed to leave only a necessary portion of the conductor layer 58, thereby forming a second circuit layer (S.25, FIG. 7 (q)).

The second resin layer forming step D and the second circuit layer forming step E are completed only once when the number of layers of the multilayer circuit board is two, but when three or more layers are required. Is incremented by n in step S.27 from the branch of step S.26, and is repeatedly executed as many times as necessary. When the required number of resin layers and circuit layers have been formed, the jig 4
Step F (S.28, FIG. 7 (r)) of stripping 0 is performed, and a multi-layer substrate on which a multi-layer circuit is formed is formed integrally with the semiconductor element 30 to complete an electronic component integrated substrate. .
The completed electronic component integrated substrate is composed of a semiconductor element 20 and a surface layer.
A first layer post 51 is formed between the first circuit layer 53 and the (first circuit layer 53) as an interlayer connection part for electrically connecting the two. 2
0 and the first circuit layer 53 are covered with an insulating resin layer 52 having a thickness substantially equal to that of the resin layer 52.
Thus, the electronic component 20 is fixed to the substrate.

According to the first embodiment, the semiconductor device 30
Because we decided to laminate multilayer circuit boards based on
Compared to a case where a semiconductor element is attached to a multilayer substrate formed as in the related art, the element and the circuit on the substrate side can be accurately connected without being affected by expansion and contraction of the resin constituting the substrate. Therefore, it is not necessary to secure a large margin in consideration of the expansion and contraction of the resin in joining the element and the circuit, and it is possible to easily cope with the miniaturization of the electrode pitch.
Further, by using the post formed by plating for the connection between the electrode pad 32 and each circuit layer, a stronger and more reliable electrical connection can be obtained as compared with the conventional connection using solder.

Next, a second embodiment will be described.
The second embodiment is a modified example in which a part of the steps of the first embodiment described above is modified. FIG. 8 is a flowchart of each step and step, and FIG. 9 is a step in a step unique to the second embodiment. A cross-sectional view of the structure of the multilayer substrate is shown. Other processes,
The structure at the stage is the same as in the first embodiment.

The manufacturing method according to the second embodiment includes an installation step A (S.51) of installing a semiconductor element in a holding hole of a jig;
A first resin layer forming step B (S.52 to S.57) for covering the surfaces of the element and the jig with an insulating first resin layer, and a first circuit for forming a first circuit layer on the first resin layer Layer forming step C (S.58 to S.6)
2), a second resin layer forming step D (S. 63 to S. 69) of covering the first circuit layer with an insulating second resin layer, and forming a second circuit layer on the second resin layer The second circuit layer forming step E (S.70 to S.7)
4) and a step F (S.78) of stripping the jig.

Installation step A and first resin layer forming step B
Is the same as in the first embodiment. When these steps are completed, the substrate is in the state shown in FIG.

In the first circuit layer forming step C, a first circuit layer is formed while being connected to the first layer post 51. In this example, as shown in FIG. 9A, a power supply film 60 for plating is formed on the first resin layer 52 (S.58), and a photosensitive resist layer (plating resist) is formed on the power supply film 60. ) 61 is formed
(S.59). Then, the resist layer 61 is exposed and developed in a predetermined pattern to leave a resist layer corresponding to the insulating portion of the first circuit layer (S.60).
To form a conductor layer 53 by electrolytic plating (S.6).
1, FIG. 9 (b)). After forming the conductor layer 53, the resist layer 6
1 is removed (S.62). At this stage, the power supply film 60 may be removed using the conductor layer 53 as a mask.
In the resin layer forming step D, the power supply film 60 is used for forming the second layer post.
And is to be removed after forming the post.

The second resin layer forming step D includes a step of forming a second layer post and a step of forming a second resin layer around the post after the formation of the post. First, as shown in FIG. 9C, a photosensitive resist layer (plating resist) 55 is formed on the first circuit layer 53 and the power supply film 60 (S.63), and is exposed and developed in a predetermined pattern. Thus, an opening 55a reaching the first circuit layer 53 is formed at the post formation position of the resist layer 55 (S.64). Subsequently, a current is supplied to the power supply film 60 to perform electrolytic plating, so that the second layer post 56 is formed in the opening 55a.
Is formed (S.65), the resist layer 55 is removed (S.66), and then the power supply film 60 is etched with a hydrogen peroxide-containing sulfuric acid aqueous solution or the like using the first circuit layer 53 as a mask (S.67, S.67). FIG. 9D). At this stage, the power supply film 60 used to form the first circuit layer 53 is removed. Next, similarly to the first embodiment shown in FIGS. 6 (n) and 6 (o), the formed second layer post 5 is formed.
A second resin layer 57 is formed on the first resin layer 52 so as to cover the first circuit layer 53 and the first circuit layer 53 (S.68), and the second layer post 56 is caught by polishing the surface (S.68). .69).

The second circuit layer forming step E is the same as the first circuit layer forming step C. First, a power supply film is formed (S.70), and a resist layer (plating resist) is formed thereon. Exposure and development are performed (S.71, 72), and a conductor layer is formed by electrolytic plating in a portion of the opening formed in the resist layer (S.73). After the formation of the conductor layer, the resist layer is removed (S.74). When three or more circuit layers are formed, n is incremented at step S.76 from the branch of step S.75 while the power supply film is left to be used for post formation of the next layer. The resin layer forming step D and the second circuit layer forming step E are performed. When the formation of the required number of resin layers and circuit layers is completed, the power supply film formed in step S.70 of the final second circuit layer forming step E is removed by etching (S.77), and the jig 40 is formed. A step F (S.78) of peeling off is performed, and a multi-layer substrate on which a multi-layer circuit is formed is integrally formed with the semiconductor element 30, thereby completing an electronic component integrated substrate.

In the second embodiment, since the power supply film is formed before the formation of the conductor layer of the circuit, the conductor layer can be formed by electrolytic plating. Since the layer can be formed, there is no need for etching after the formation, and the time required for forming the conductor layer can be reduced as compared with the first embodiment.

FIG. 10 is a flowchart showing the steps and steps of the third embodiment, and FIGS. 11 to 14 are sectional views showing the structure of the multilayer substrate at each step. As shown in FIG. 10, the manufacturing method according to the third embodiment also includes an installation step A (S.101) of installing a semiconductor element in a holding hole of a jig, and a step of insulating the surface of the element and the jig. A first resin layer forming step B (S.102 to S.104) for covering with the first resin layer,
First circuit layer forming step C for forming a circuit layer (S.105 to S.109)
A second resin layer forming step D (S.110 to S.112) of covering the first circuit layer with an insulating second resin layer; and forming a second circuit layer on the second resin layer. Two circuit layer forming step E (S.113 to S.113)
117) and a step F (S.120) of separating the jig.

In the installation step A, as shown in FIG. 11A, the semiconductor element 30 is exposed so that the substrate connection surface 31 is exposed.
Is fitted into the holding hole 41 of the jig 40 (S.1). Jig 40
Is the same as that of the first embodiment.

In the first resin layer forming step B, the electrode pads 3
In a state where the first interlayer connection portion is connected and formed in 2, a portion other than the interlayer connection portion of the substrate connection surface and the surface of the jig are covered with the insulating first resin layer. In this example, the first resin layer forming step B is a step of forming the first resin layer 52 on the entire surface of the substrate connection surface 31 and the surface of the jig 40 (S.102, FIG. 11B),
Forming an opening 52a reaching the electrode pad 32 of the semiconductor element 30 in the first resin layer 52 (S.103, FIG. 11C).
And forming a first layer post 51 as a first interlayer connection portion in the opening 52a (S.103, FIG. 12D).

The first resin layer 52 is made of a photosensitive epoxy resin having an insulating property. In this case, the opening 52a can be formed by a chemical process such as exposure and development. However, the opening 52a may be formed by a physical process using a laser cutter or the like, without using a photosensitive resin. After the formation of the openings, the first resin layer 52 is thermally cured.

The first layer post 51 is formed by electroless plating or by using electrolytic plating in the middle. At this time, the metal deposited by filling the opening 52a becomes the first layer post 51, and the first resin layer 52 around the opening 52a.
The portion deposited on the surface becomes a conductor layer 53 for forming the first circuit layer. That is, in this example, in the first resin layer forming step B, the first layer post forming step S.
Step S.105 of forming the conductor layer in the circuit layer forming step C is continuously performed in the process.

In the first circuit layer forming step C, a first circuit layer is formed while being connected to the first layer post 51. As described above, the conductor layer 53 is formed continuously with the formation of the first layer post 51.
Is formed (S.105, FIG. 12D), a photosensitive resist layer (etching resist) is formed thereon (S.106), and the resist layer is exposed and developed in a predetermined pattern to form a first resist. The resist layer is left in the conductive portion of the circuit layer (S.107), and the conductor layer 53 in a region not covered by the resist layer is removed by etching (S.108). After the etching, the resist layer is removed to leave only the necessary portions of the conductor layer 53, thereby forming the first circuit layer 53 (S.109, FIG. 12E).

As the first interlayer connection portion, not only the post 51 filling the opening 52a as described above, but also the first interlayer connection portion shown in FIG.
The film 5 formed on the surface of the opening 52a as shown in (d-2)
Via hole type connection form using 1a can also be used.

The second resin layer forming step D includes the first circuit layer 53
Is a step in which a portion other than the second interlayer connection portion is covered with an insulating second resin layer in a state where the second interlayer connection portion is connected and formed to a part of the first circuit layer 53. The step of forming the layer 57 (S.110, FIG. 13 (f)) and the step of forming the opening 57a reaching a part of the first circuit layer 53 in the second resin layer 57 (S.111, FIG. )) And forming a second layer post 56 as a second interlayer connection portion in the opening 57a (S.112, FIG. 13H).

The second resin layer 57 is also made of a photosensitive epoxy resin like the first resin layer 52, and the opening 5 is formed by exposure and development.
7a is formed. The second layer posts 56 are formed by electroless plating or by using electrolytic plating in the middle. At this time, the metal deposited by filling the opening 57a becomes the second layer post 56, and the portion deposited on the surface of the second resin layer 57 around the opening 57a becomes the conductor layer 58 for forming the second circuit layer. . That is, in this example, the second
Step S.112 for forming second layer post in resin layer forming step D
And step S.11 of forming a conductor layer in the second circuit layer forming step E
3 is continuously performed on the process.

In the second circuit layer forming step E, a second circuit layer is formed while being connected to the second layer post 56. As described above, the conductive layer 58 is formed continuously with the formation of the second layer post 56.
Is formed (S.113, FIG. 13 (h)), a photosensitive resist layer (etching resist) is formed thereon (S.114), and the resist layer is exposed and developed in a predetermined pattern to form a first resist. The resist layer is left in the conductive portion of the circuit layer (S.115), and the conductor layer 58 in a region not covered by the resist layer is removed by etching (S.116). After the etching, the resist layer is removed to leave only the necessary portions of the conductor layer 58, thereby forming the second circuit layer 58 (S.117, FIG. 14 (i)). As the second interlayer connection, similarly to the first interlayer connection shown in FIG. 12D-2, a via-hole connection mode can be used.

When three or more circuit layers are formed, n is incremented in step S.119 from the branch of step S.118, and the second resin layer forming step D and the second circuit layer forming step E are executed. I do. When the formation of the necessary number of resin layers and circuit layers is completed, a step F (S.120) of peeling the jig 40 is performed, and the multilayer substrate on which the multilayer circuit is formed is integrated with the semiconductor element 30. And the electronic component integrated substrate is completed.

According to the third embodiment, an insulating resin layer is formed first, and an opening is formed in the insulating resin layer to form an interlayer connection portion. Therefore, the number of steps can be reduced as compared with the first and second embodiments, and the efficiency of the operation can be improved. In addition, since the posts, which are the interlayer connection portions, and the conductors of the circuit layer can be formed in a continuous process, the operation is easier than performing these processes as separate processes.

Next, a fourth embodiment will be described.
The fourth embodiment is a modified example in which a part of the steps of the above-described third embodiment is modified. FIG. 15 is a flowchart of each step and step, and FIG. 16 is a step in a step unique to the fourth embodiment. A cross-sectional view of the structure of the multilayer substrate is shown. The structure in other steps and stages is the same as that of the third embodiment.

The manufacturing method according to the fourth embodiment includes an installation step A (S.151) of installing a semiconductor element in a holding hole of a jig.
A first resin layer forming step B (S.152 to S.157) of covering the surfaces of the element and the jig with an insulating first resin layer; and a first step of forming a first circuit layer on the first resin layer. One circuit layer forming process C (S.1
58 to S.160), a second resin layer forming step D (S.161 to S.166) of covering the first circuit layer with an insulating second resin layer,
Second circuit layer forming step E of forming a second circuit layer on the resin layer
(S.167 to S.1694) and a step F (S.172) of peeling the jig are sequentially included.

The first two steps of the setting step A and the first resin layer forming step B are the same as in the third embodiment. When these steps are completed, the substrate is in the state shown in FIG.

Next, in the fourth embodiment, as shown in FIG. 16A, a power supply film 60 is formed inside the opening formed in the first resin layer 52 and on the surface of the first resin layer 52 ( S.15
4) Then, a photosensitive resist layer (plating resist) is formed thereon (S.155). Then, by exposing and developing the resist layer according to a predetermined pattern, the resist layer 61 is left according to the insulating portion of the first circuit layer (S.156). . At this time, FIG.
As shown in FIG. 6B, the metal deposited to fill the opening is the first metal.
A layer post 51 is formed on the surface of the power supply film 60 outside the opening.
Becomes That is, in this example, the first resin layer forming step B
The step S.157 of forming the first layer post and the step S.158 of forming the conductor layer in the first circuit layer forming step C are continuously performed in the process.

In the first circuit layer forming step C, a first circuit layer is formed while being connected to the first layer post 51. As described above, the conductor layer 53 is formed continuously with the formation of the first layer post 51.
Is formed (S.158), the resist layer 61 is removed (S.159), and the power supply film 60 is removed by etching using the conductor layer 53 as a mask (S.160).

The second resin layer forming step D is the same as the first resin layer forming step B. First, a second resin layer is formed so as to cover the first circuit layer 53 (S.161). Form an opening
(S.162). Subsequently, a power supply film is formed on the entire surface including the inside of the opening (S.163), a resist layer (plating resist) is formed, and exposure and development are performed (S.164, S.165). Then, the power supply film is energized to perform electrolytic plating, thereby forming the second layer post (S.166) and continuously forming the conductor layer used for the second circuit layer (S.167).

The second circuit layer forming step E is the same as the first circuit layer forming step C. After the conductor layer is continuously formed on the second layer post, the resist layer is removed (S.168). The power supply film is removed by etching using the conductor layer as a mask (S.16
9). When forming three or more circuit layers, step S.
From step 170, n is incremented in step S.171,
The second resin layer forming step D and the second circuit layer forming step E are performed. When the formation of the required number of resin layers and circuit layers is completed, a step F (S.172) of peeling the jig 40 is performed, and the multilayer substrate on which the multilayer circuit is formed is integrated with the semiconductor element 30. And the electronic component integrated substrate is completed.

In the fourth embodiment, the post and the conductor layer can be formed by electroplating using the power supply film, and the conductor layer can be formed only in a finally required portion. Therefore, there is no need to etch the conductor layer later, and the time required for forming the conductor layer can be reduced as compared with the third embodiment.

FIG. 17 is a flowchart showing the steps and steps of the fifth embodiment, and FIGS. 18 to 22 are sectional views showing the structure of the multilayer substrate at each step. Although the above-described four embodiments show the case where the substrate is stacked on the single semiconductor element 30, a large number of components are practically mounted on the substrate. Further, among components to be mounted, a semiconductor device having solder bumps or leads formed on electrode pads, or a component with leads such as a capacitor is often used. When such a component is used, it is not necessary to form the first layer post as the first interlayer connection as in the above embodiment. The fifth embodiment is a method suitable for using an electronic component in which leads or bumps are formed on one surface serving as the substrate connection surface.

The manufacturing method according to the fifth embodiment includes an installation step A (S.201) for fitting an electronic component such that leads or bumps protrude from a holding hole of the jig, and a process for mounting the component and the surface of the jig. A first resin layer forming step B (S. 202, 203) covering with an insulating first resin layer, and a first circuit layer forming step C (S. 204 to S. 204) forming a first circuit layer on the first resin layer. 209) and a second resin layer forming step D (S.2) of covering the first circuit layer with the second resin layer.
10 to S.217), a second circuit layer forming step E of forming a second circuit layer on the second resin layer (S.218 to S.222), and a step F of removing the jig (S.225). ). When the circuit layer of the multi-layer substrate has two layers, the entire process is completed once through each of the steps A to F. However, in order to form three or more circuit layers, the second step is performed.
Only the resin layer forming step D and the second circuit layer forming step E are repeatedly executed.

In the installation step A, as shown in FIG. 18A, a semiconductor element 33 having a solder bump 33a formed on an electrode pad, a capacitor 34 having leads 34a,
The semiconductor element 35 on which the lead 35a is formed is fitted into the holding hole of the jig 45 so that the bump and the lead protrude, respectively (S.201).

In the first resin layer forming step B, each component and the surface of the jig are covered with an insulating first resin layer 52 (S.202,
Thereafter, the leads and the resin layer are polished until all the bumps and the leads appear on the surface of the first resin layer 52 (FIG. 18B).
(S.203, FIG. 18 (c)). Since the bumps and leads of each component have different lengths, when the first resin layer 52 is formed, the solder bumps 33a of the semiconductor element 33 and the semiconductor elements 3
The lead 35a of the capacitor 5 is buried in the first resin layer 52, and the lead 34a of the capacitor 34 protrudes from the first resin layer 52. This is mechanically polished by a device such as a buff or a belt sander to make the height uniform, and all leads and bumps are exposed on the surface.

In the above case, the first resin layer 52 is desirably applied by a non-contact method such as a curtain coating method.
However, if the heights of the leads and bumps are all the same,
Alternatively, when the heights of the leads are trimmed before the first resin layer 52 is formed, a simple application method such as screen printing can be used.

In the first circuit layer forming step C, the conductor layer 53 for forming the first circuit layer is formed on the polished surface by electroless plating or by using electrolytic plating in the middle (S.204). FIG. 19 (d)), and a photosensitive resist layer thereon.
(Etching resist) is formed (S.205), and this is exposed and developed in a predetermined pattern to leave a resist layer in a conductive portion of the first circuit layer (S.207). Then, the conductor layer 53 in a region not covered with the resist layer is removed by etching (S.2
08), by removing the resist layer, only the necessary portion of the conductor layer 53 is left, thereby forming the first circuit layer.
(S.209, FIG. 19 (e)). In the first circuit layer forming step C, as described in the second embodiment, a power supply film is first formed on one surface, a resist layer (plating resist) is formed thereon, and this is exposed. A method of removing the resist layer at the portion where the conductor layer is to be formed by development, forming the conductor layer at a necessary portion by electrolytic plating, and then removing the resist layer and the power supply film can also be used.

The second resin layer forming step D includes the first circuit layer 53
Is a step of covering a portion other than the second interlayer connection portion with an insulating second resin layer in a state where the second interlayer connection portion is connected and formed on a part of the second interlayer connection portion. The method includes a step of forming a second layer post as a connecting portion, and a step of forming a second resin layer around the post after the formation of the post. In the step of forming the second layer post, a power supply film 54 is formed on the first circuit layer 53 and the first resin layer 52 (S.210, FIG.
0 (f)), a photosensitive resist layer (plating resist) 55 is formed on the power supply film 54 (S.211), and the first formation position of the resist layer 55 is exposed to light via a process of exposure and development. An opening 55a reaching the circuit layer 53 is formed (S.212,
FIG. 20 (g)).

Subsequently, a current is applied to the power supply film 54 to perform electrolytic plating, thereby forming a second layer post 56 in the opening 55a (S.213, FIG. 20H), and removing the resist layer 55. (S.214), and the power supply film 54 is etched using the second layer posts 56 as a mask (S.215, FIG. 21 (i)). Next, the formed second layer post 56 and first circuit layer 53 are formed.
The second resin layer 57 is formed on the first resin layer 52 so as to cover the second layer post (S.216, FIG. 21 (j)), and the surface of the second layer post 56 is located by polishing the surface (S.216). 217, FIG. 21 (k)).

In the second circuit layer forming step E, a second circuit layer is formed while being connected to the second layer post 56. As described above, with the second layer posts 56 exposed on the surface of the second resin layer 57, the conductor layer 58 to be the second circuit layer is formed on the second resin layer 57 (S.218, FIG. 22 (l)). And
A photosensitive resist layer (etching resist) is formed on the conductor layer 58 (S.219), and the resist layer is exposed and developed in a predetermined pattern to leave a resist layer in a conductive portion of the second circuit layer (S.219). .220), the conductor layer 58 in a region not covered by the resist layer is removed by etching (S.221). After the etching, the resist layer is removed to leave only the necessary portions of the conductor layer 58, thereby forming the second circuit layer 58 (S.222, FIG. 22 (m)).

When three or more circuit layers are formed, n is incremented in step S.224 from the branch of step S.223, and the second resin layer forming step D and the second circuit layer forming step E are executed. I do. When the formation of the required number of resin layers and circuit layers is completed, a step F (S.225, FIG. 22 (n)) of peeling the jig 45 is performed, and the electronic components 33, 34, 35 are multilayered. Is formed integrally, and an electronic component integrated substrate is completed.

According to the fifth embodiment, when an electronic component having leads and bumps is used, a circuit layer can be formed on the basis of these leads and bumps, and the electronic component is fixed to a completed substrate. As compared with the case where the circuit is formed, the element and the circuit on the substrate side can be accurately connected without being affected by expansion and contraction of the resin constituting the substrate.

[0070]

As described above, according to the manufacturing method of the present invention, since the interlayer connection portion, the resin layer, and the circuit layer are sequentially laminated from the element side based on the electronic component, the electronic component and the substrate The positional relationship with the side can be accurately maintained. Therefore, it is not necessary to secure a large margin in consideration of the expansion and contraction of the resin in joining the element and the circuit, and it is possible to easily cope with the miniaturization of the electrode pitch. Further, since the interlayer connection portion can be formed by means such as plating, the connection reliability can be kept higher than when the electronic component and the circuit layer are connected by soldering.

According to a second aspect of the present invention, when the first layer post is first formed as the first interlayer connection portion on the electrode and then the first resin layer is formed around the post, Although the number of steps is increased, there is no need to form an opening in the resin layer later, and thus there is an advantage that the type of resin is not limited. On the other hand, as in claim 3, a first resin layer is first formed on the entire surface of the substrate connection surface and on the surface of the jig, an opening reaching the electrode is formed in the resin layer, and the first resin layer is formed in the formed opening. 1
When the method of forming the interlayer connection is adopted, for example, it is necessary to use a photosensitive resin or to form an opening with a laser cutter or the like, but the number of steps can be reduced as compared with the case of claim 2. In addition, it is possible to shorten the time of the manufacturing process.

It should be noted that, in the method of claim 3,
If the conductor layer is formed continuously at the time of forming the first interlayer connection portion as described above, the actual number of steps is further reduced, and the steps are easier than performing these steps as separate steps.

When a semiconductor element having solder bumps or leads formed on the electrode pads or a component with leads such as a capacitor is used, the method of claim 5 is used to refer to these leads and bumps. A circuit layer can be formed on the board, and compared to the case where electronic components are fixed to a completed board, the element and the circuit on the board side are accurately connected without being affected by expansion and contraction of the resin constituting the board. Can be.

In the second resin layer forming step, the sixth resin layer may be formed.
A method in which a post is first formed as a second interlayer connecting portion and a resin layer is formed later, and an opening is formed after first forming a second resin layer on the entire surface. Method and you can choose. According to the method of claim 7, it is possible to form the conductor layer continuously at the time of forming the second interlayer connection portion. The method of claim 6 has the advantage that the type of resin is not limited, the method of claim 7 can reduce the number of steps, and the method of claim 8 can further reduce the number of steps compared to the method of claim 7. There is an advantage that you can.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a method for manufacturing an electronic component-integrated multilayer substrate according to a first embodiment.

FIG. 2 is a cross-sectional view of the substrate showing each step (No. 1) of the method according to the first embodiment.

FIG. 3 is a cross-sectional view of the substrate, illustrating each step (No. 2) of the method according to the first embodiment.

FIG. 4 is a sectional view of the substrate, showing each step (No. 3) of the method according to the first embodiment.

FIG. 5 is a cross-sectional view of the substrate, illustrating each step (No. 4) of the method according to the first embodiment.

FIG. 6 is a sectional view of the substrate, illustrating each step (No. 5) of the method according to the first embodiment.

FIG. 7 is a cross-sectional view of the substrate, illustrating each step (No. 6) of the method according to the first embodiment.

FIG. 8 is a flowchart illustrating a method for manufacturing an electronic component-integrated multilayer substrate according to a second embodiment.

FIG. 9 is a cross-sectional view of a substrate showing characteristic steps of the method of the second embodiment.

FIG. 10 is a flowchart showing a method for manufacturing an electronic component-integrated multilayer substrate according to a third embodiment.

FIG. 11 is a cross-sectional view of a substrate showing each step (No. 1) of the method according to the third embodiment.

FIG. 12 is a cross-sectional view of the substrate, showing each step (No. 2) of the method according to the third embodiment.

FIG. 13 is a cross-sectional view of the substrate, illustrating each step (No. 3) of the method according to the third embodiment.

FIG. 14 is a cross-sectional view of the substrate, illustrating each step (No. 4) of the method according to the third embodiment.

FIG. 15 is a flowchart illustrating a method of manufacturing an electronic component-integrated multilayer substrate according to a fourth embodiment.

FIG. 16 is a cross-sectional view of a substrate showing characteristic steps of the method of the fourth embodiment.

FIG. 17 is a flowchart illustrating a method of manufacturing an electronic component-integrated multilayer substrate according to a fifth embodiment.

FIG. 18 is a cross-sectional view of the substrate, illustrating each step (No. 1) of the method according to the fifth embodiment.

FIG. 19 is a sectional view of the substrate, showing each step (No. 2) of the method according to the fifth embodiment;

FIG. 20 is a sectional view of the substrate, illustrating each step (No. 3) of the method according to the fifth embodiment;

FIG. 21 is a sectional view of the substrate, showing each step (No. 4) of the method according to the fifth embodiment;

FIG. 22 is a sectional view of the substrate, showing each step (No. 5) of the method according to the fifth embodiment;

FIG. 23 is a cross-sectional view of a substrate showing each step (No. 1) of a conventional method for manufacturing an electronic component-integrated multilayer substrate.

FIG. 24 is a cross-sectional view of the substrate showing each step (No. 2) of the conventional method for manufacturing an electronic component-integrated multilayer substrate.

FIG. 25 is a cross-sectional view of the substrate showing each step (No. 3) of the conventional method of manufacturing an electronic component-integrated multilayer substrate.

FIG. 26 is a cross-sectional view of the substrate showing each step (part 4) of the conventional method of manufacturing an electronic component-integrated multilayer substrate.

[Explanation of symbols]

 Reference Signs List 30 semiconductor element 40 jig 51 first layer post 52 first resin layer 53 first circuit layer 56 second layer post 57 second resin layer 58 second circuit layer

Claims (9)

[Claims] An electronic component-integrated multilayer substrate comprising at least one electronic component having electrodes formed on one surface serving as a substrate connection surface and a multilayer build-up substrate to which the electronic component is attached. In the method, using a jig provided with a holding hole into which the electronic component fits, an installation step of fitting the electronic component so that the board connection surface is exposed in the holding hole, and a first interlayer on the electrode. With the connection part connected and formed,
A first resin layer forming step of covering a portion other than the interlayer connection portion of the substrate connection surface and a surface of the jig with an insulating first resin layer; and forming the first interlayer connection on the first resin layer. A first circuit layer forming step of forming a first circuit layer connected to a portion, and a state in which a second interlayer connection portion is connected and formed to a part of the first circuit layer, except for the second interlayer connection portion. Forming a second circuit layer on the second resin layer, the second circuit layer being connected to the second interlayer connecting portion, on the second resin layer. A method for manufacturing an electronic component integrated substrate, comprising: a step; and a step of peeling off the jig. 2. The first resin layer forming step includes forming a first layer post as a first interlayer connection portion on the electrode, and forming the first resin layer around the post after the post is formed. 2. The method according to claim 1, further comprising the step of: 3. The first resin layer forming step includes: forming the first resin layer on the entire surface of the substrate connection surface and the surface of the jig; and forming an opening reaching the electrode in the first resin layer. The method of manufacturing an electronic component-integrated multi-layer substrate according to claim 1, further comprising the steps of: forming a first interlayer connection portion in the opening; 4. The method according to claim 1, wherein in the first circuit layer forming step, the first circuit layer is formed.
4. The method according to claim 3, wherein the first circuit layer is formed using a conductor layer formed continuously and collectively at the time of forming the interlayer connection portion. 5. At least one electronic component having leads or bumps formed on one surface serving as a substrate connection surface,
A method for manufacturing an electronic component-integrated multi-layer substrate comprising a multilayer build-up substrate to which the electronic component is attached, wherein the lead or the bump is formed using a jig having a holding hole into which the electronic component is fitted. An installation step of fitting the electronic component into the holding hole so as to protrude from the holding hole; a first resin layer forming step of covering the substrate connection surface and the surface of the jig with an insulating first resin layer; Forming a first circuit layer on the first resin layer, the first circuit layer being connected to a first interlayer connection portion made of the lead or the bump; and forming a second circuit layer on a part of the first circuit layer. A second resin layer forming step of covering a portion other than the second interlayer connection portion with an insulating second resin layer in a state where the interlayer connection portion is connected and formed; and forming the second resin layer on the second resin layer. Second circuit layer connected to interlayer connection The second and the circuit layer forming step, electronic component integrated substrate manufacturing method which comprises a step in the order of removing the jig to be formed. 6. The second resin layer forming step includes forming a post as a second interlayer connection portion on the first circuit layer, and forming the second resin layer around the post after the post is formed. The method of manufacturing an electronic component-integrated multilayer substrate according to any one of claims 1 to 5, further comprising the steps of: 7. The second resin layer forming step includes: forming the second resin layer on the entire surface of the first resin layer so as to cover the first circuit layer; and forming the first resin layer on the second resin layer. The electronic component-integrated multilayer according to any one of claims 1 to 5, further comprising a step of forming an opening reaching a circuit layer and a step of forming the second interlayer connection portion in the opening. Substrate manufacturing method. 8. The second circuit layer forming step, wherein the second circuit layer
8. The method according to claim 7, wherein the second circuit layer is formed using a conductor layer formed continuously and collectively at the time of forming the interlayer connection portion. 9. An electronic device comprising: a multi-layer build-up board in which a plurality of circuit layers are stacked via an insulating resin layer; and at least one electronic component connected to a surface circuit layer of the build-up board. In the component-integrated multi-layer substrate, an interlayer connection portion for electrically connecting the electronic component and the surface circuit layer is formed between the electronic component and the surface circuit layer, and the surface circuit layer is formed in a portion other than the interlayer connection portion. The electronic component is covered with an insulating resin layer having a thickness substantially equal to the distance between the electronic component and the surface circuit layer, and the electronic component is fixed to the substrate by the resin layer. Multilayer board with integrated electronic components.