JP3938921B2 - Manufacturing method of semiconductor IC built-in module - Google Patents

Description

  The present invention relates to a semiconductor IC built-in module and a manufacturing method thereof, and more particularly to a semiconductor IC built-in module suitable for incorporating a semiconductor IC having a narrow electrode pitch and a manufacturing method thereof.

  In recent years, many proposals have been made to mount a semiconductor IC to be mounted on a printed circuit board in a bare chip state in order to satisfy the demand for miniaturization and thinning of a semiconductor IC mounting module. A bare chip semiconductor IC has a very narrow electrode pitch compared to a packaged semiconductor IC. Therefore, when the semiconductor IC is mounted on a printed circuit board, an electrode provided on the semiconductor IC (hereinafter referred to as a “land electrode”). It is an important problem how to connect the wiring to the wiring (hereinafter referred to as “substrate wiring pattern”) provided on the printed circuit board.

  As one method for connecting the land electrode and the substrate wiring pattern, a method for connecting them by wire bonding is known. According to this method, a semiconductor IC in a bare chip state can be mounted relatively easily, but the area for mounting the semiconductor IC and the area for connecting the bonding wires need to be provided on different planes on the printed circuit board. There is a problem that the mounting area becomes large.

  As another method of connecting the land electrode and the substrate wiring pattern, a method of flip chip connecting a bare-chip semiconductor IC to a printed circuit board is also known. Although it is possible to reduce the mounting area according to this method, in order to ensure sufficient mechanical connection strength between the land electrode and the substrate wiring pattern, a multilayer under barrier metal is formed on the surface of the land electrode. There is a problem that the process becomes complicated.

  In addition, since the two methods described above both mount a semiconductor IC on the surface of the printed board, there is a common problem that it is difficult to make the entire module thin. As a method for solving this, as described in Patent Document 1, a method is considered in which a cavity is formed in a printed circuit board and a semiconductor IC in a bare chip state is embedded therein, thereby forming a module with a built-in semiconductor IC. It is done.

However, in the method described in Patent Document 1, it is necessary to increase the thickness of the printed circuit board to some extent in order to ensure the strength of the portion where the cavity is formed, which hinders the thinning of the module. there were. Further, since the size of the cavity in the planar direction needs to be set to be somewhat larger than the size of the semiconductor IC in the planar direction, a deviation occurs in the relative positional relationship between the land electrode and the substrate wiring pattern. It has been very difficult to use a narrow semiconductor IC having an electrode pitch of 100 μm or less.
JP-A-9-321408

  As described above, in the conventional semiconductor IC built-in module, it is difficult to sufficiently reduce the thickness, and at the same time, it is very difficult to use a semiconductor IC having a narrow electrode pitch.

  Accordingly, an object of the present invention is to provide a module with a built-in semiconductor IC capable of realizing further reduction in thickness and a method for manufacturing the same.

  Another object of the present invention is to provide a semiconductor IC built-in module capable of using a semiconductor IC with a very narrow electrode pitch and a method for manufacturing the same.

A semiconductor IC built-in module according to the present invention includes a first resin layer, a second resin layer, at least a post electrode embedded in the first and second resin layers, the first resin layer, and the and a fixed semiconductor IC to be embedded between the second resin layer, said on the land electrodes of the semiconductor IC bumps provided, said bumps being positioned with respect to the post electrode It is characterized by. The module with a built-in semiconductor IC according to the present invention includes a first resin layer, a second resin layer, a post electrode provided through the first and second resin layers, and the first resin. is fixed so as to be buried between the the layer second resin layer, and a semiconductor IC that is thinned, bumps provided on the land electrodes of the semiconductor IC, the bumps in the post electrode It is characterized by being positioned with respect to.

According to the present invention, since the semiconductor IC is embedded between the first resin layer and the second resin layer, it is possible to reduce the thickness of the entire module with built-in semiconductor IC. Moreover, since the bumps provided on the semiconductor IC are positioned with respect to the post electrodes, the planar position of the bumps is substantially fixed, and therefore the electrode pitch of 100 μm or less, particularly about 60 μm is very high. A narrow semiconductor IC can be used. In addition, if a thin semiconductor IC is used, the thickness of the entire semiconductor IC built-in module can be made very thin.

  The present invention further includes a first substrate wiring pattern provided on the first resin layer side and a second substrate wiring pattern provided on the second resin layer side, wherein one end of the post electrode is Preferably, the post substrate is electrically connected to the first substrate wiring pattern, and the other end of the post electrode is electrically connected to the second substrate wiring pattern. According to this, it becomes possible to perform electrical connection from one surface of the module with a built-in semiconductor IC to the other surface. It is more preferable to further include a third substrate wiring pattern provided so as to be embedded between the first resin layer and the second resin layer. According to this, it becomes possible to give a complicated wiring pattern by the module with a built-in semiconductor IC.

A method of manufacturing a module with a built-in semiconductor IC according to the present invention includes a step of forming a post electrode on a first transfer substrate, a step of forming first and second positioning portions on a second transfer substrate, Temporarily positioning the semiconductor IC having the bumps on the second transfer substrate while positioning the bumps on one positioning portion; and the first transfer substrate by the second positioning portion and the post electrode. Pressing the resin with the first and second transfer substrates and curing the resin while positioning the substrate with respect to the second transfer substrate.

According to the present invention, since the position of the bump provided on the semiconductor IC in the planar direction is substantially fixed with respect to the position of the post electrode in the planar direction, it is connected to the bump with almost no deviation. It is possible to form a wiring pattern. This makes it possible to use a semiconductor IC having a very narrow electrode pitch of 100 μm or less, particularly about 60 μm.

In the present invention, it is preferable to further include a step of reducing the thickness of the semiconductor IC before temporarily fixing the semiconductor IC to the second transfer substrate. According to this, the thickness of the entire semiconductor IC built-in module can be made very thin.

  In the present invention, it is preferable to further include a step of forming a substrate wiring pattern on at least one of the first transfer substrate and the second transfer substrate. According to this, it is possible to simultaneously form the substrate wiring pattern in the step of pressing and curing the resin.

Further, in the present invention, after the resin is cured, the step of exposing the post electrode and the bump by peeling the second transfer substrate, the step of forming a resin layer covering the exposed post electrode and the bump , Preferably, the method further includes a step of exposing the post electrode and the bump again by removing a part of the resin layer, and a step of forming a substrate wiring pattern corresponding to the post electrode and the bump exposed again. In this case, since the position of the bump in the planar direction and the position of the post electrode in the planar direction are substantially fixed, the substrate wiring pattern can be formed with almost no deviation.

  In addition, a multilayer substrate can be used as the first transfer substrate. In this case, the first transfer substrate is not peeled off and may be used as it is as a part of the module with a built-in semiconductor IC.

  As described above, according to the present invention, it is possible to provide a thin semiconductor IC built-in module using a semiconductor IC having a very narrow electrode pitch.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic sectional view showing the structure of a semiconductor IC built-in module 100 according to a preferred embodiment of the present invention.

  As shown in FIG. 1, the semiconductor IC built-in module 100 according to the present embodiment includes a laminated resin layer 140 (first resin layer) and resin layer 150 (second resin layer), a resin layer 140, and a resin layer. 150, the semiconductor IC 130 embedded between them, the lower substrate wiring patterns 110 and 111 (first substrate wiring patterns) provided so as to be embedded in the surface of the resin layer 140, and the surface of the resin layer 150. The upper substrate wiring patterns 170 and 171 (second substrate wiring patterns), the underlying conductor layer 160 provided below the upper substrate wiring patterns 170 and 171, and the resin layer 140 and the resin layer 150 are embedded so as to be embedded therein. A post electrode 120 that electrically connects the lower substrate wiring pattern 111 and the upper substrate wiring pattern 171 and the surface of the resin layer 140 A protective layer 180 covering the lower board wiring patterns 110 and 111, and a protective layer 181 covering the surface and the upper board wiring patterns 170 and 171 of the resin layer 150 is formed. A stud bump 132 is formed on each land electrode (not shown in FIG. 1) of the semiconductor IC 130, and each land electrode is electrically connected to the upper substrate wiring pattern 170 via the corresponding stud bump 132. Connected. As shown in FIG. 1, the stud bump 132 is provided through the resin layer 150.

  Although not shown in FIG. 1, passive components such as capacitors are mounted on the surfaces of the protective layers 180 and 181, and the lower substrate wiring pattern is formed via via holes (BVH) provided in the protective layers 180 and 181. 110, 111 or upper substrate wiring patterns 170, 171 are electrically connected.

  In the semiconductor IC built-in module 100 according to the present embodiment, the built-in semiconductor IC 130 is thinned by polishing, so that the overall thickness of the semiconductor IC built-in module 100 can be reduced to 1 mm or less, for example, about 200 μm. Is possible. As will be described later, in this embodiment, the position of each stud bump 132 provided in the semiconductor IC 130 in the planar direction is substantially fixed with respect to the position of the post electrode 120 in the planar direction. In addition, there is almost no deviation in the relative positional relationship between the stud bump 132 and the upper substrate wiring pattern 170.

  FIG. 2 is a schematic perspective view showing the structure of the semiconductor IC 130.

  As shown in FIG. 2, the semiconductor IC 130 is a bare-chip semiconductor IC, and a large number of land electrodes 131 are provided on the surface 130a thereof. The pitch of the land electrodes 131 (electrode pitch) is not particularly limited, but in the semiconductor IC built-in module 100 according to the present embodiment, there is almost no deviation in the relative positional relationship between the land electrodes 131 and the upper substrate wiring pattern 170. Therefore, it is possible to use a very narrow semiconductor IC having an electrode pitch of 100 μm or less, for example, 60 μm.

  In addition, the back surface 130b of the semiconductor IC 130 is polished, so that the thickness t (distance from the front surface 130a to the back surface 130b) of the semiconductor IC 130 is very thin compared to a normal semiconductor IC. The thickness t of the semiconductor IC 130 is not particularly limited, but is preferably set to 200 μm or less, for example, about 20 to 50 μm. The polishing of the back surface 130b is preferably performed on a large number of semiconductor ICs in a wafer state and then separated into individual semiconductor ICs 130 by dicing. When the semiconductor ICs 130 are separated by dicing before being thinned by polishing, the work efficiency can be improved by polishing the back surface 130b with the surface 130a of the semiconductor IC 130 covered with a thermosetting resin or the like.

  Each land electrode 131 is formed with a stud bump 132. The size of the stud bump 132 may be appropriately set according to the electrode pitch. For example, when the electrode pitch is about 100 μm, the diameter is set to about 30 to 50 μm and the height is set to about 40 to 80 μm. That's fine. The stud bumps 132 can be formed by separating the individual semiconductor ICs 130 by dicing and then forming them on each land electrode 131 using a wire bonder. The material of the stud bump 132 is not particularly limited, but copper (Cu) is preferably used. If copper (Cu) is used as the material of the stud bump 132, it is possible to obtain a higher bonding strength with respect to the land electrode 131 than when gold (Au) is used, and the reliability is improved.

  Next, a method for manufacturing the semiconductor IC built-in module 100 shown in FIG. 1 will be described with reference to the drawings.

  3 to 24 are process diagrams for explaining a method of manufacturing the semiconductor IC built-in module 100 shown in FIG.

  First, a transfer substrate 101 (first transfer substrate) is prepared, and photosensitive dry films 102 and 103 are attached to the front surface 101a and the back surface 101b, respectively (FIG. 3). Any material may be used as the material for the transfer substrate 101 as long as it has conductivity. However, since the material is peeled off in a later step, the adhesion to the resin layer 140 shown in FIG. Is preferably used. Examples of the material having low adhesiveness to the resin include nickel (Ni) and stainless steel. The thickness of the transfer substrate 101 is not particularly limited as long as the mechanical strength necessary for the transfer substrate is ensured, and may be set to about 50 μm, for example. On the other hand, the thickness of the dry film 102 needs to be set slightly thicker than the lower substrate wiring patterns 110 and 111. For example, when the thickness of the lower substrate wiring patterns 110 and 111 is about 20 μm, the dry film 102 is dry. The thickness of the film 102 may be set to about 25 μm. As will be described later, the dry film 103 is provided for the purpose of preventing the back surface 101b of the transfer substrate 101 from being plated, and the thickness thereof is arbitrary.

  Next, the dry film 102 is exposed using a photomask (not shown), and the dry film 102 in the regions 110a and 111a where the lower substrate wiring patterns 110 and 111 are to be formed is removed (FIG. 4). As a result, the surface 101a of the transfer substrate 101 is exposed in the region 110a and the region 111a. At this time, the dry film 103 is not removed, and thereby the back surface 101b of the transfer substrate 101 is kept substantially covered.

  After exposing a part of the surface 101a of the transfer substrate 101 in this way, electrolytic plating using the transfer substrate 101 as a base is performed. Thereby, lower substrate wiring patterns 110 and 111 are formed in the regions 110a and 111a where the surface 101a of the transfer substrate 101 is exposed (FIG. 5). As for the back surface 101b of the transfer substrate 101, since the entire surface is substantially covered with the dry film 103, no plating is formed. About the kind of plating solution, what is necessary is just to select suitably according to the material which should constitute lower substrate wiring pattern 110, 111. For example, when the material of lower substrate wiring pattern 110, 111 is copper (Cu), Copper sulfate can be used as the plating solution. Thereafter, when the dry films 102 and 103 are peeled off, the lower substrate wiring patterns 110 and 111 are formed on the surface 101a of the transfer substrate 101 (FIG. 6).

  Next, another photosensitive dry films 104 and 105 are respectively attached to the front surface 101a and the back surface 101b of the transfer substrate 101 (FIG. 7). The thickness of the dry film 104 needs to be set slightly thicker than that of the post electrode 120. For example, when the thickness of the post electrode 120 is about 90 μm, the thickness of the dry film 104 is about 100 μm. You only have to set it. On the other hand, like the dry film 103, the dry film 105 is provided for the purpose of preventing the back surface 101b of the transfer substrate 101 from being plated, and the thickness thereof is arbitrary.

  Next, the dry film 104 is exposed using a photomask (not shown), and the dry film 104 in the region 120a where the post electrode 120 is to be formed is removed (FIG. 8). As shown in FIG. 8, the region 120a in which the post electrode 120 is to be formed is a region corresponding to the substantially central portion of the lower substrate wiring pattern 111. As a result, the lower substrate wiring pattern 111 is exposed in the region 120a. It becomes a state. At this time, the dry film 105 is not removed, so that the entire back surface 101b of the transfer substrate 101 is substantially covered.

  After exposing a part of the lower substrate wiring pattern 111 in this way, electrolytic plating using the transfer substrate 101 as a base is performed. Thus, the post electrode 120 is formed in the region 120a where the lower substrate wiring pattern 111 is exposed (FIG. 9). As for the back surface 101b of the transfer substrate 101, since the entire surface is substantially covered with the dry film 105, no plating is formed. The selection of the plating solution is as described above, and for example, copper sulfate can be used. Then, if the dry films 104 and 105 are peeled, the lower substrate wiring patterns 110 and 111 and the post electrodes 120 are formed on the surface 101a of the transfer substrate 101 (FIG. 10). Thus, the processing for the transfer substrate 101 is completed.

  On the other hand, a transfer substrate 106 (second transfer substrate) is prepared separately from the transfer substrate 101, and a predetermined region is removed by etching using an etching mask (not shown), whereby a plurality of positioning holes 106a are obtained. (First positioning portion) and a plurality of positioning holes 106b (second positioning portion) are formed (FIG. 11). The transfer substrate 106 may be made of the same material and the same thickness as the transfer substrate 101, but need not have conductivity unlike the transfer substrate 101. However, it is preferable to use a material having low adhesion to the resin layer 140 because it is peeled off in a later step. When the same material as the transfer substrate 101 is used as the material of the transfer substrate 106, the positioning holes 106a and 106b can be formed by wet etching using ferric chloride.

  The positioning hole 106a is a hole for temporarily fixing the semiconductor IC 130 in a state where the semiconductor IC 130 is positioned on the transfer substrate 106 by fitting the stud bump 132 in the following process. Therefore, it is necessary to set the diameter to be substantially the same as or slightly larger than the diameter of the stud bump 132. If the diameter of the positioning hole 106a is too large compared to the diameter of the stud bump 132, the semiconductor IC 130 cannot be temporarily fixed to the transfer substrate 106. Therefore, the diameter of the positioning hole 106a should not be set too large. Further, as long as the semiconductor IC 130 can be temporarily fixed in a state where it is positioned on the transfer substrate 106, it is not necessary to form the same number of positioning holes 106a corresponding to all the stud bumps 132, as shown in FIG. The positioning holes 106a corresponding to some of the stud bumps 132 are provided, and the notch 106c that is sufficiently larger than the diameter of the stud bump 132 is provided in the region corresponding to the remaining stud bumps 132, so that the remaining studs The bump 132 and the transfer substrate 106 may be configured to avoid interference.

  On the other hand, the positioning hole 106b is a hole for positioning the transfer substrate 106 with respect to the transfer substrate 101 by fitting the post electrode 120 in the following process. Therefore, the diameter needs to be set slightly larger than the diameter of the post electrode 120. However, if the diameter of the positioning hole 106b is too large compared to the diameter of the post electrode 120, the positioning accuracy is lowered, so the diameter of the positioning hole 106b should not be set too large.

  As described above, the positioning hole 106a and the positioning hole 106b formed in the transfer substrate 106 are holes through which the stud bumps 132 and the post electrodes 120 are fitted in the following steps, respectively, and the accuracy of the relative positional relationship between them is determined. Therefore, it is required to form with high accuracy. Accordingly, the positioning holes 106a and 106b may be formed using another method, for example, a drill as long as the processing accuracy is ensured. Thus, the processing for the transfer substrate 106 is completed.

  Further, processing on the semiconductor IC 130 is performed separately from processing on the transfer substrate 101 and the transfer substrate 106. As described above, there are two processes for the semiconductor IC 130: thinning by polishing and formation of the stud bumps 132. As described above, thinning by polishing is performed by polishing the back surface 130b in the state of a wafer, reducing the thickness t to 200 μm or less, for example, about 20 to 50 μm, and then dicing into individual semiconductor ICs 130 by dicing. be able to. The stud bumps 132 can be formed by separating the individual semiconductor ICs 130 by dicing and then forming them on each land electrode 131 using a wire bonder. As a result, as shown in FIG. 2, the semiconductor IC 130 having a reduced thickness and the stud bump 132 formed on each land electrode 131 can be manufactured.

  When the processing for the transfer substrate 106 and the processing for the semiconductor IC 130 are completed in this way, the stud bumps 132 of the semiconductor IC 130 are inserted into the positioning holes 106 a provided in the transfer substrate 106, and thereby the semiconductor IC 130 is transferred to the transfer substrate 106. Is temporarily fixed (FIG. 13). As a result, the semiconductor IC 130 is positioned on the transfer substrate 106.

  Next, the transfer substrate 101 and the transfer substrate 106 are used to position the transfer substrate 106 with respect to the transfer substrate 101 so that the post electrode 120 is inserted into the positioning hole 106 b provided in the transfer substrate 106. The prepreg 140a is pressed (FIG. 14). The prepreg 140a is a sheet obtained by impregnating a fiber such as carbon fiber, glass fiber, or aramid fiber with an uncured thermosetting resin such as an epoxy resin, and heat contained in the prepreg 140a by applying heat while pressing. The curable resin is cured to form the resin layer 140 (FIG. 15). Accordingly, the lower substrate wiring pattern 110, the lower substrate wiring pattern 111, the post electrode 120, and the semiconductor IC 130 are integrated by the resin layer 140. Thereafter, the transfer substrate 101 and the transfer substrate 106 are peeled off, and the integrated laminate is taken out (FIG. 16). When the transfer substrate 101 and the transfer substrate 106 are peeled, the post electrodes 120 and the stud bumps 132 are projected as shown in FIG. Here, the planar positional relationship between the post electrode 120 and the stud bump 132 substantially matches the planar positional relationship between the positioning hole 106 a and the positioning hole 106 b provided in the transfer substrate 106. The positional relationship is substantially fixed.

  Next, the surface from which the post electrode 120 and the stud bump 132 protrude is covered with the prepreg 150a to completely cover the protruding post electrode 120 and the stud bump 132 (FIG. 17). As the prepreg 150a to be used, the same material as the prepreg 140a used for forming the resin layer 140 may be used. Then, the prepreg 150a is cured by applying heat to form the resin layer 150, and then the surface is removed by polishing or blasting to expose the post electrode 120 and the stud bump 132 (FIG. 18).

  Next, a thin underlying conductor layer 160 is formed on the entire surface on the side where the post electrode 120 and the stud bump 132 are exposed by a vapor phase growth method such as sputtering (FIG. 19). However, in forming the base conductor layer 160, a plating method may be used instead of the vapor phase growth method, or the base conductor layer 160 may be formed by attaching a metal foil. Since unnecessary portions of the underlying conductor layer 160 are removed thereafter, the thickness of the underlying conductor layer 160 needs to be set sufficiently thin, and is preferably set to about 0.3 μm, for example.

  Next, photosensitive dry films 107 and 108 are attached to both surfaces of the laminate, that is, the surface of the resin layer 140 and the surface of the base conductor layer 160, respectively (FIG. 20). The thickness of the dry film 107 needs to be set slightly thicker than the upper substrate wiring patterns 170 and 171. For example, when the thickness of the upper substrate wiring patterns 170 and 171 is about 20 μm, the dry film 107 The thickness may be set to about 25 μm. On the other hand, the dry film 108 is provided for the purpose of preventing the surface of the resin layer 140 on which the lower substrate wiring patterns 110 and 111 are formed from being plated, and the thickness thereof is arbitrary. .

  Next, the dry film 107 is exposed using a photomask (not shown), and the dry film 107 in the regions 170a and 171a where the upper substrate wiring patterns 170 and 171 are to be formed is removed (FIG. 21). As a result, the base conductor layer 160 is exposed in the region 170a and the region 171a. At this time, the dry film 108 is not removed, whereby the surface of the resin layer 140 on which the lower substrate wiring patterns 110 and 111 are formed is substantially covered.

  Here, the region 170a where the upper substrate wiring pattern 170 is to be formed includes a region corresponding to the stud bump 132 as shown in FIG. As described above, in this embodiment, since the semiconductor IC 130 having a very narrow electrode pitch is used, a large deviation is not allowed in the relative positional relationship between the stud bump 132 and the region 170a in the plane direction. As described above, the relative positional relationship between the post electrode 120 and the post electrode 120 is substantially fixed. This is because the relative positional relationship between the photomask pattern corresponding to the region 170a and the photomask pattern corresponding to the region 171a is the relative positional relationship between the stud bump 132 and the post electrode 120 in the planar direction. Since it means that they substantially coincide, it is possible to accurately expose the region corresponding to the stud bump 132 in the underlying conductor layer 160.

  After exposing a part of the underlying conductor layer 160 in this way, electrolytic plating using the underlying conductor layer 160 as a base is performed. Accordingly, upper substrate wiring patterns 170 and 171 are formed in the regions 170a and 171a where the underlying conductor layer 160 is exposed (FIG. 22). Since the entire surface of the resin layer 140 is substantially covered with the dry film 108, no plating is formed. The selection of the plating solution is as described above, and for example, copper sulfate can be used. Thereafter, when the dry films 107 and 108 are peeled off, the upper substrate wiring patterns 170 and 171 are formed on the surface of the underlying conductor layer 160 (FIG. 23).

  Then, an unnecessary base conductor layer 160 where the upper substrate wiring patterns 170 and 171 are not formed is removed (soft etching) using an etching solution such as an acid (FIG. 24), and then both sides of the laminate are photosensitive. The portions of the lower substrate wiring pattern 110 and the upper substrate wiring pattern 170 are exposed by removing the portions of the protective layers 180 and 181 corresponding to the regions where passive components such as capacitors are to be mounted. Thereafter, by mounting passive components, the semiconductor IC built-in module 100 shown in FIG. 1 is completed.

  As described above, in the manufacture of the semiconductor IC built-in module 100 according to the present embodiment, since the transfer substrate 106 having the positioning holes 106a and 106b is used, the stud bump 132 and the post electrode 120 in the planar direction are relative to each other. The positional relationship is substantially fixed. Thus, the relative positional relationship between the photomask pattern corresponding to the region 170a and the photomask pattern corresponding to the region 171a is substantially the same as the relative positional relationship between the stud bump 132 and the post electrode 120 in the planar direction. Therefore, when the upper substrate wiring patterns 170 and 171 are formed, the stud bumps 132 can be accurately aligned. Therefore, even when a very narrow semiconductor IC 130 having an electrode pitch of 100 μm or less, for example, 60 μm, is used, the relative positional relationship between the land electrode 131 and the stud bump 132 and the upper substrate wiring pattern 170 is minimized. Can be suppressed.

  Moreover, since the thickness t of the semiconductor IC 130 used in the present embodiment is set to be very thin by polishing, the entire thickness of the semiconductor IC built-in module 100 is very thin, for example, about 200 μm. Is possible.

  In the manufacturing process described above, after the resin layer 150 is formed, the surface is removed by polishing or blasting to expose the post electrode 120 and the stud bump 132 (see FIG. 18). It is also possible to expose the stud bump 132 by drilling using a laser or the like. The method will be described below with reference to the drawings.

  25 to 31 are process diagrams for explaining a manufacturing method in the case where the post electrode 120 and the stud bump 132 are exposed by punching.

  First, after the steps up to FIG. 17 are completed, a hole 151 is formed in the resin layer 150 by irradiating a region corresponding to the post electrode 120 and the stud bump 132 to expose the post electrode 120 and the stud bump 132. (FIG. 25). The hole 151 may be formed by a method other than laser irradiation.

  The subsequent process is the same as the process after FIG. 19, and after forming the thin base conductor layer 160 on the entire surface on the side where the post electrode 120 and the stud bump 132 are exposed (FIG. 26), Photosensitive dry films 107 and 108 are attached to both surfaces (FIG. 27), and the dry film 107 is exposed using a photomask (not shown) to remove the dry films 107 in the regions 170a and 171a (FIG. 28). Next, electrolytic plating using the base conductor layer 160 as a base is performed to form upper substrate wiring patterns 170 and 171 in the regions 170a and 171a, respectively (FIG. 29). Then, the dry films 107 and 108 are peeled off (FIG. 30), and the unnecessary base conductor layer 160 where the upper substrate wiring patterns 170 and 171 are not formed is removed (soft etching) (FIG. 31). Thereafter, both sides of the laminate are covered with photosensitive protective layers 180 and 181, and portions of the protective layers 180 and 181 corresponding to regions where passive components such as capacitors are to be mounted are removed to remove the lower substrate wiring pattern 110 and the upper portion. After a part of the substrate wiring pattern 170 is exposed, a passive component is mounted to complete the semiconductor IC built-in module.

  Next, a semiconductor IC built-in module according to another preferred embodiment of the present invention will be described.

  FIG. 32 is a schematic cross-sectional view showing the structure of a semiconductor IC built-in module 200 according to another preferred embodiment of the present invention.

  As shown in FIG. 32, the semiconductor IC built-in module 200 according to the present embodiment includes the laminated resin layer 240 and resin layer 250, and the semiconductor IC 230 and internal substrate wiring embedded between the resin layer 240 and resin layer 250. A pattern 290 (third substrate wiring pattern), lower substrate wiring patterns 210 and 211 provided on the surface of the resin layer 240, upper substrate wiring patterns 270 and 271 provided on the surface of the resin layer 250, and a lower substrate The base conductor layer 261 provided on the resin layer 240 side of the wiring patterns 210 and 211, the base conductor layer 260 provided on the resin layer 250 side of the upper substrate wiring patterns 270 and 271, the resin layer 240 and the resin layer 250 inside So that the lower substrate wiring pattern 211 and the upper substrate wiring pattern 271 are electrically connected to each other. A post electrode 220 that continues, a protective layer 280 that covers the surface of the resin layer 240 and the lower substrate wiring patterns 210 and 211, and a protective layer 281 that covers the surface of the resin layer 250 and the upper substrate wiring patterns 270 and 271. Has been. As described above, the semiconductor IC built-in module 200 according to the present embodiment is provided with the internal substrate wiring pattern 290 and the lower substrate wiring patterns 210 and 211 are resin layers as compared with the semiconductor IC built-in module 100 described above. It is mainly different in that it is not embedded in 240 but provided on its surface.

  Also in the semiconductor IC built-in module 200 according to the present embodiment, passive components such as capacitors are mounted on the surfaces of the protective layers 280 and 281, and the lower substrate wiring pattern 210 is formed via via holes (BVH) provided in the protective layers 280 and 281. , 211 or the upper substrate wiring patterns 270, 271. Further, the semiconductor IC 230 incorporated can be the same as the semiconductor IC 130 used in the above-described semiconductor IC built-in module 100. As shown in FIG. 32, the upper substrate wiring pattern 270 is interposed via the stud bump 232. And are electrically connected.

  Next, a method for manufacturing the semiconductor IC built-in module 200 shown in FIG. 32 will be described with reference to the drawings. In addition, since the manufacturing method of the semiconductor IC built-in module 200 according to the present embodiment is similar to the manufacturing method of the semiconductor IC built-in module 100 described above in many parts, some redundant descriptions may be omitted. .

  33 to 49 are process diagrams for explaining a method of manufacturing the semiconductor IC built-in module 200 shown in FIG.

  First, a transfer substrate 201 is prepared, and a predetermined region is removed by etching using an etching mask (not shown), thereby forming a plurality of positioning holes 201a and a plurality of positioning holes 201b (FIG. 33). The transfer substrate 201 may be made of the same material and the same thickness as the transfer substrate 101 described above. As a method of forming the positioning holes 201a and 201b, the positioning holes 106a and 106b are formed in the transfer substrate 106. A method similar to the method used may be used.

  The positioning hole 201a is a hole for temporarily fixing the semiconductor IC 230 in a state where the semiconductor IC 230 is positioned on the transfer substrate 201 by fitting the stud bump 232 in the following process. Therefore, the diameter of the positioning hole 201a is the stud bump 232. It is necessary to set it to be almost the same as or slightly larger than the diameter. As described with reference to FIG. 12, the positioning holes 201 a corresponding to some of the stud bumps 232 are provided, and the area corresponding to the remaining stud bumps 232 is sufficiently larger than the diameter of the stud bump 232. By providing the notches, interference between the remaining stud bumps 232 and the transfer substrate 201 may be avoided. On the other hand, the positioning hole 201b is a hole for positioning the transfer substrate 201 with respect to the transfer substrate 206 described later by fitting the post electrode 220 in the following process.

  Next, photosensitive dry films 202 and 203 are attached to both surfaces of the transfer substrate 206 (FIG. 34), and the dry film 203 is exposed using a photomask (not shown), whereby the internal substrate wiring pattern 290 is exposed. The dry film 203 in the region 290a to be formed is removed (FIG. 35). At this time, the dry film 202 is not removed.

  After exposing a part of the back surface of the transfer substrate 201 in this way, an internal substrate wiring pattern 290 is formed in the region 290a by performing electrolytic plating using the transfer substrate 201 as a base (FIG. 36). Thereafter, when the dry films 202 and 203 are peeled off, the internal substrate wiring pattern 290 is formed on the back surface of the transfer substrate 201 (FIG. 37).

  Next, a semiconductor IC 230 having the same structure as the semiconductor IC 130 described above is prepared, and temporarily fixed by inserting stud bumps 232 of the semiconductor IC 230 into the positioning holes 201 provided in the transfer substrate 201 (FIG. 38). As a result, the semiconductor IC 230 is positioned on the transfer substrate 201.

  On the other hand, a transfer substrate 206 is prepared separately from the transfer substrate 201, and a plurality of post electrodes 220 are formed on the surface thereof using a method similar to the method in which the internal substrate wiring pattern 290 is formed on the transfer substrate 201. . Then, the transfer substrate 201 and the transfer substrate 206 are used to position the prepreg while positioning the transfer substrate 201 with respect to the transfer substrate 206 so that the post electrode 220 is inserted into the positioning hole 201b provided in the transfer substrate 201. 240a is pressed (FIG. 39). In this state, the prepreg 240a is cured by applying heat to form the resin layer 240 (FIG. 40). Thereby, the internal substrate wiring pattern 290, the post electrode 220, and the semiconductor IC 230 are integrated by the resin layer 240. Thereafter, the transfer substrate 201 and the transfer substrate 206 are peeled off, and the integrated laminate is taken out (FIG. 41). Here, since the planar positional relationship between the post electrode 220 and the stud bump 232 substantially matches the planar positional relationship between the positioning hole 201a and the positioning hole 201b provided in the transfer substrate 201, both The positional relationship is substantially fixed.

  Next, the surface from which the post electrode 220 and the stud bump 232 protrude is covered with the prepreg 250a to completely cover the protruding post electrode 220 and the stud bump 232 (FIG. 42). Then, the prepreg 250a is cured by applying heat to form the resin layer 250, and then the surface is removed by polishing or blasting to expose the post electrode 220 and the stud bump 232 (FIG. 43).

  Next, a thin underlying conductor layer 260 is formed on the entire surface on the side where the resin layer 250 is formed, and a thin underlying conductor layer 261 is formed on the entire surface on the side where the resin layer 240 is formed ( FIG. 44). That is, the base conductor layer is formed on both surfaces of the multilayer body. Next, photosensitive dry films 207 and 208 are respectively attached to both surfaces of the laminate, that is, the surfaces of the underlying conductor layers 260 and 261 (FIG. 45), and the dry films 207 and 207 using a photomask (not shown) are used. By exposing 208, the dry film 207 in the regions 270a and 271a where the upper substrate wiring patterns 270 and 271 are to be formed and the dry film 208 in the regions 210a and 211a where the lower substrate wiring patterns 210 and 211 are to be formed are removed. (FIG. 46). As a result, the base conductor layer 260 is exposed in the regions 270a and 271a, and the base conductor layer 261 is exposed in the regions 210a and 211a.

  Here, the region 270a where the upper substrate wiring pattern 270 is to be formed includes a region corresponding to the stud bump 232 as shown in FIG. 46, but the stud bump 232 and the post electrode 220 relative to each other in the planar direction. Therefore, the region corresponding to the stud bump 232 in the base conductor layer 260 can be accurately exposed.

  Thus, after exposing a part of base conductor layers 260 and 261, electrolytic plating using base conductor layers 260 and 261 as a base is performed. As a result, upper substrate wiring patterns 270 and 271 are formed in the regions 270a and 271a where the underlying conductor layer 260 is exposed, and lower substrate wiring patterns are formed in the regions 210a and 211a where the underlying conductor layer 261 is exposed. 210 and 211 are formed (FIG. 47). Thereafter, when the dry films 207 and 208 are peeled off, the upper substrate wiring patterns 270 and 271 are formed on the surface of the underlying conductor layer 260, and the lower substrate wiring patterns 210 and 211 are formed on the surface of the underlying conductor layer 261. (FIG. 48).

  Then, an unnecessary base conductor layer 260 is removed (soft etching) in a portion where the upper substrate wiring patterns 270 and 271 are not formed using an etching solution, and a portion where the lower substrate wiring patterns 210 and 211 are not formed. After removing unnecessary base conductor layer 261 (soft etching) (FIG. 49), both sides of the laminate are covered with photosensitive protective layers 280 and 281 and portions corresponding to regions where passive components such as capacitors are to be mounted. The protective layers 280 and 281 and the resin layer 250 are removed to expose part of the lower substrate wiring pattern 210, the upper substrate wiring pattern 270, and the internal wiring pattern 290, and then passive components are mounted thereon to mount FIG. The semiconductor IC built-in module 200 shown in FIG.

  As described above, in the manufacture of the semiconductor IC built-in module 200 according to the present embodiment, since the transfer substrate 201 having the positioning holes 201a and 201b is used, the stud bump 232 and the post electrode 220 in the planar direction are relative to each other. The positional relationship is substantially fixed. As a result, as in the above embodiment, even when a very narrow semiconductor IC 230 having an electrode pitch of 100 μm or less, for example, 60 μm, is used, the relative positional relationship between the stud bump 232 and the upper substrate wiring pattern 270 is shifted. Can be minimized.

  Furthermore, in the present embodiment, since the internal substrate wiring pattern 290 is formed, a more complicated wiring pattern can be applied.

  In the manufacturing process described above, after the resin layer 250 is formed, the surface is removed by polishing or blasting to expose the post electrode 220 and the stud bump 232 (see FIG. 43). As described with reference to FIG. 31, the post electrode 220 and the stud bump 232 may be exposed by drilling using a laser or the like. At this time, if a part of the internal substrate wiring pattern 290 is also exposed by drilling, it is possible to easily connect the internal substrate wiring pattern 290 to other wirings and the like.

  The present invention is not limited to the embodiments described above, and various modifications are possible within the scope of the invention described in the claims, and these are also included in the scope of the present invention. Needless to say.

  For example, in the semiconductor IC built-in module 100 shown in FIG. 1, the lower substrate wiring patterns 110 and 111 are embedded in the resin layer 140. In the pressing process shown in FIG. The lower substrate wiring patterns 110 and 111 may be formed on the surface of the resin layer 140 by using the transfer substrate 206 shown in FIG.

  On the contrary, in the semiconductor IC built-in module 200 shown in FIG. 32, the transfer substrate 101 shown in FIGS. 10 and 14 is used in place of the transfer substrate 206 in the pressing step shown in FIG. Through the steps shown in FIG. 24, the lower substrate wiring patterns 210 and 211 may be embedded in the resin layer 240.

  Further, both the lower substrate wiring pattern 110 embedded in the resin layer 140 (240) and the lower substrate wiring patterns 210 and 211 formed on the surface of the resin layer 140 (240) may be formed. In this case, in order to insulate the buried lower substrate wiring pattern 110 from the lower substrate wiring patterns 210 and 211 formed on the surface, it is necessary to interpose a layer similar to the resin layer 150 (250) between them. There is.

  In any of the embodiments, the transfer substrate is finally peeled off. However, for example, a multi-layer substrate with a large number of internal wirings is used as one transfer substrate, and this is peeled off after pressing. Alternatively, it can be used as it is as a part of a module with a built-in semiconductor IC. For example, in the pressing step shown in FIG. 39, instead of the transfer substrate 206 on which the post electrode 220 is formed, a multilayer substrate on which the post electrode 220 is formed may be used as it is without peeling off. .

  Further, in any of the embodiments, the post electrode 120 (220) is inserted into the positioning hole 106b (201b) provided in the transfer substrate 106 (201), thereby transferring the image to the transfer substrate 101 (206). Although the substrate 106 (201) is positioned (see FIGS. 14 and 39), it is not essential to insert the post electrode into the positioning hole at the time of positioning. For example, positioning may be performed by setting the height of the post electrode to approximately the same as the thickness of the prepreg (140a, 240a) and recognizing the image of the post electrode through the positioning hole. In this case, positioning can be performed correctly even if the post electrode is not inserted into the positioning hole. Even when the post electrode is inserted into the positioning hole, if positioning by image recognition is also used, positioning can be performed correctly even if the diameter of the positioning hole is set sufficiently larger than the diameter of the post electrode. Thus, the work efficiency can be improved.

  As described above, according to the present invention, it is possible to provide a thin semiconductor IC built-in module using a semiconductor IC having a very narrow electrode pitch.

1 is a schematic cross-sectional view showing a structure of a semiconductor IC built-in module 100 according to a preferred embodiment of the present invention. 2 is a schematic perspective view showing a structure of a semiconductor IC 130. FIG. It is a figure which shows a part (formation of the dry films 102 and 103) of the manufacturing process of the module 100 with a built-in semiconductor IC. It is a figure which shows a part (patterning of the dry film 102) of the manufacturing process of the module 100 with a built-in semiconductor IC. 7 is a diagram showing a part of the manufacturing process of the semiconductor IC built-in module 100 (formation of lower substrate wiring patterns 110 and 111). FIG. It is a figure which shows a part (peeling of the dry films 102 and 103) of the manufacturing process of the module 100 with a built-in semiconductor IC. It is a figure which shows a part (formation of the dry films 104 and 105) of the manufacturing process of the module 100 with a built-in semiconductor IC. It is a figure which shows a part (patterning of the dry film 104) of the manufacturing process of the module 100 with a built-in semiconductor IC. 7 is a diagram showing a part of the manufacturing process of the semiconductor IC built-in module 100 (formation of the post electrode 120). FIG. It is a figure which shows a part (peeling of the dry films 104 and 105) of the manufacturing process of the module 100 with a built-in semiconductor IC. It is a figure which shows a part (formation of positioning hole 106a, 106b) of the manufacturing process of the module 100 with a built-in semiconductor IC. It is a figure for demonstrating the positioning method when only the positioning hole 106a corresponding to some stud bumps 132 is provided in the board | substrate 106 for transfer. 7 is a diagram showing a part of the manufacturing process of the semiconductor IC built-in module 100 (temporary fixing of the semiconductor IC 130). FIG. FIG. 5 is a diagram showing a part of the manufacturing process of the semiconductor IC built-in module 100 (pressing by the transfer substrates 101 and 106). 7 is a diagram illustrating a part of the manufacturing process of the semiconductor IC built-in module 100 (formation of a resin layer 140). FIG. 7 is a diagram showing a part of the manufacturing process of the semiconductor IC built-in module 100 (peeling of the transfer substrates 101 and 106). FIG. It is a figure which shows a part (formation of prepreg 150a) of the manufacturing process of the module 100 with a built-in semiconductor IC. 6 is a diagram illustrating a part of the manufacturing process of the semiconductor IC built-in module 100 (formation of a resin layer 150). FIG. FIG. 5 is a diagram illustrating a part of the manufacturing process of the semiconductor IC built-in module 100 (formation of the base conductor layer 160). FIG. 5 is a diagram showing a part of the manufacturing process of the semiconductor IC built-in module 100 (formation of dry films 107 and 108). It is a figure which shows a part (patterning of the dry film 107) of the manufacturing process of the module 100 with a built-in semiconductor IC. 7 is a diagram showing a part of the manufacturing process of the semiconductor IC built-in module 100 (formation of upper substrate wiring patterns 170 and 171). FIG. It is a figure which shows a part (peeling of the dry films 107 and 108) of the manufacturing process of the module 100 with a built-in semiconductor IC. FIG. 5 is a diagram showing a part of the manufacturing process of the semiconductor IC built-in module 100 (removal of the underlying conductor layer 160). It is a figure which shows a part of other manufacturing process (formation of the hole 151) of the module 100 with a built-in semiconductor IC. It is a figure which shows a part (formation of the base conductor layer 160) of the other manufacturing process of the module 100 with a built-in semiconductor IC. It is a figure which shows a part (formation of the dry films 107 and 108) of the other manufacturing process of the module 100 with a built-in semiconductor IC. It is a figure which shows a part of other manufacturing process (patterning of the dry film 107) of the module 100 with a built-in semiconductor IC. 6 is a diagram showing a part of another manufacturing process of the semiconductor IC built-in module 100 (formation of upper substrate wiring patterns 170 and 171). FIG. It is a figure which shows a part (peeling of the dry films 107 and 108) of the other manufacturing process of the module 100 with a built-in semiconductor IC. It is a figure which shows a part (removal of the base conductor layer 160) of the other manufacturing process of the module 100 with a built-in semiconductor IC. It is a schematic sectional drawing which shows the structure of the semiconductor IC built-in module 200 by other preferable embodiment of this invention. It is a figure which shows a part (formation of positioning hole 201a, 201b) of the manufacturing process of the module 200 with a built-in semiconductor IC. It is a figure which shows a part (formation of the dry films 202 and 203) of the manufacturing process of the module 200 with a built-in semiconductor IC. It is a figure which shows a part of manufacturing process of the module 200 with a built-in semiconductor IC (patterning of the dry film 203). 7 is a diagram showing a part of the manufacturing process of the semiconductor IC built-in module 200 (formation of an internal substrate wiring pattern 290). FIG. It is a figure which shows a part of manufacturing process of the module 200 with a built-in semiconductor IC (peeling of the dry films 202 and 203). It is a figure which shows a part of manufacturing process of the module 200 with a built-in semiconductor IC (temporary fixing of the semiconductor IC 230). It is a figure which shows a part (press by the transfer substrates 201 and 206) of the manufacturing process of the module 200 with a built-in semiconductor IC. It is a figure which shows a part of manufacturing process of the module 200 with a built-in semiconductor IC (formation of the resin layer 240). It is a figure which shows a part of manufacturing process of the module 200 with a built-in semiconductor IC (peeling of the transfer substrates 201 and 206). It is a figure which shows a part of manufacturing process of the semiconductor IC built-in module 200 (formation of the prepreg 250a). It is a figure which shows a part of manufacturing process of the semiconductor IC built-in module 200 (formation of the resin layer 250). 7 is a diagram showing a part of the manufacturing process of the semiconductor IC built-in module 200 (formation of the underlying conductor layers 260 and 261). FIG. It is a figure which shows a part (formation of the dry films 207 and 208) of the manufacturing process of the module 200 with a built-in semiconductor IC. It is a figure which shows a part (patterning of the dry films 207 and 208) of the manufacturing process of the semiconductor IC built-in module 200. FIG. 6 is a diagram showing a part of the manufacturing process of the semiconductor IC built-in module 200 (formation of upper substrate wiring patterns 270 and 271 and lower substrate wiring patterns 210 and 211). FIG. It is a figure which shows a part of manufacturing process of the module 200 with a built-in semiconductor IC (peeling of the dry films 207 and 208). It is a figure which shows a part of manufacturing process of the module 200 with a built-in semiconductor IC (removal of the underlying conductor layers 260 and 261).

Explanation of symbols

100, 200 Semiconductor IC built-in module 101, 106, 201, 206 Transfer substrate 101a Front surface 101b Back surface 102-105, 107, 108, 202, 203, 207, 208 Dry film 106a, 106b, 201a, 201b Positioning holes 110, 111 , 210, 211 Lower substrate wiring pattern 110a, 111a, 120a, 170a, 171a, 210a, 211a, 270a, 271a, 290a Area 120, 220 where dry film is removed Post electrode 130, 230 Semiconductor IC
130a Front surface 130b Back surface 131 Land electrodes 132, 232 Stud bumps 140, 150, 240, 250 Resin layers 140a, 150a, 240a, 250a Pre-preg 151 Holes 160, 260, 261 Base conductor layers 170, 171, 270, 271 Upper substrate wiring pattern 180,181,280,281 Protective layer 290 Internal substrate wiring pattern

Claims (5)

Forming a post electrode on the first transfer substrate;
Forming first and second positioning portions on a second transfer substrate;
Temporarily fixing the semiconductor IC having the bump on the second transfer substrate while positioning the bump on the first positioning portion;
While the first transfer substrate is positioned with respect to the second transfer substrate by the second positioning portion and the post electrode, the resin is pressed and cured by the first and second transfer substrates. A method of manufacturing a module with a built-in semiconductor IC. 2. The method of manufacturing a module with a built-in semiconductor IC according to claim 1 , further comprising a step of reducing a thickness of the semiconductor IC before temporarily fixing the semiconductor IC to the second transfer substrate. 3. The method of manufacturing a module with built-in semiconductor IC according to claim 1 , further comprising a step of forming a substrate wiring pattern on at least one of the first transfer substrate and the second transfer substrate. After curing the resin, exposing the post electrode and the bump by peeling the second transfer substrate; and forming a resin layer covering the exposed post electrode and the bump; The method further comprises exposing the post electrode and the bump again by removing a part of the resin layer, and forming a substrate wiring pattern corresponding to the post electrode and the bump exposed again. A method for manufacturing a module with a built-in semiconductor IC according to any one of claims 1 to 3 . 5. The method of manufacturing a module with a built-in semiconductor IC according to claim 1, wherein the first transfer substrate is a multilayer substrate. 6.

Images