JP4057146B2 - Manufacturing method of electronic component integrated multilayer substrate - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electronic component-integrated multilayer substrate configured by connecting a plurality of substrate layers by interlayer connection portions such as posts (metal pillars) and a method for manufacturing the same.
[0002]
[Prior art]
A conventional method for manufacturing a build-up wiring board will be described with reference to FIGS. In each figure, for the sake of explanation, the magnification in the thickness direction, which is the vertical direction in the figure, is set larger than the width direction, which is the horizontal direction, and the film pressure of the conductor layer, metal film, etc. is actually set. It is the conceptual diagram expanded and shown from the reduced scale.
[0003]
As shown in FIG. 23 (a), a copper foil 2 is formed on the surface of an insulating substrate 1 such as glass epoxy by plating or the like, and the surface is chemically treated with a chemical such as hydrogen peroxide-containing sulfuric acid, or a buff is used. Clean by mechanical polishing. Next, a dry film resist is thermocompression-bonded on the copper foil 2, and a mask for forming a circuit pattern is superimposed, exposed, and developed to leave the resist layer 3 only in a necessary portion as a circuit pattern (FIG. 23B). )). Subsequently, an unnecessary portion of the copper foil 2 is removed with an etching solution such as a copper chloride solution, an iron chloride solution, and a hydrogen peroxide-containing sulfuric acid solution to form a circuit pattern (FIG. 23 (c)), and the resist layer 3 is removed. (FIG. 23 (d)). Up to this point, it is the same as an ordinary single-layer wiring board.
[0004]
Next, a post for connection to the upper substrate is formed by plating. First, as shown in FIG. 23 (e), a plating power supply film 4 is formed on the entire surface of the substrate 1 on which a circuit pattern is formed by electroless plating, and a post plating resist layer 5 is laminated thereon (see FIG. 23E). FIG. 23 (f)). Then, the resist layer 5 is exposed and developed so as to expose a part of the conductor on the insulating substrate 1, that is, the portion where the copper foil 2 is left, thereby forming an opening 5a (FIG. 24G). In this state, the post 6 connected to the copper foil 2 is formed in the opening 5a by energizing the power supply film 4 and electrolytically plating the post metal (FIG. 24 (h)).
[0005]
Subsequently, the resist layer 5 is removed (FIG. 24 (i)), and the feed film 4 is removed by etching with an etchant such as copper chloride or hydrogen peroxide-containing sulfuric acid using the post 6 as a mask (FIG. 24 (j)). )). Then, a thermosetting insulating resin layer 7 filling the space between the lower substrate 1 and the upper substrate is applied on the substrate 1 by printing or curtain coating, and is thermally cured (FIG. 24 (k)). ).
[0006]
The surface of the insulating resin layer 7 is polished by buffing to expose the post 6 on the end face (FIG. 25 (l)), and the upper layer copper foil 8 for the circuit is formed on the entire surface of the exposed post 6 and the insulating resin layer 7. Is formed by using both electroless plating and electrolytic plating (FIG. 25 (m)). Subsequently, a resist layer 9 serving as a mask for etching the copper foil 8 is formed by resist application, exposure, and development (FIG. 25 (n)), and the copper foil 8 is etched using the resist layer 9 as a mask. A circuit pattern is formed (FIG. 25 (o)).
[0007]
After the circuit pattern is formed, the resist layer 9 is removed (FIG. 26 (p)), and a nickel (Ni) layer 10 and a gold (Au) layer 11 are formed on the copper foil 8 left as a conductor portion by plating. Thus, a pad is formed (FIG. 26 (q)). Through the above steps, a build-up type wiring board having a lower layer circuit pattern and an upper layer circuit pattern is completed. FIG. 26 (r) shows a state in which the semiconductor element 20 is connected as an electronic component to the conductive portion of the upper circuit pattern. The solder bump 22 fixed to the electrode 21 of the element 20 is brought into contact with the pad, the solder bump 22 is melted by heat and pressure, and then cooled to solidify the solder bump 22 to fix the element to the build-up type substrate. To do.
[0008]
[Problems to be solved by the invention]
However, in the above-described conventional manufacturing method, the space between the upper and lower circuit patterns is filled with the insulating resin layer 7, so that it is easily affected by environmental changes such as temperature and humidity, and the substrate expands and contracts. There is a problem that it is difficult to match the position of the pad on the mold substrate side with the position of the electrode 21 of the semiconductor element 20.
[0009]
In this regard, it is also conceivable to design the substrate in consideration of the influence of expansion and contraction as a margin. In this case, it is necessary to secure a margin with a considerable margin in consideration of the difference in expansion / contraction ratio due to the type and lot of materials used. However, due to the miniaturization and high integration of the elements, the electrode pitch of the semiconductor elements tends to be miniaturized, and there arises a problem that miniaturization cannot be dealt with in the design that secures the above margin.
[0010]
In addition, the above manufacturing method requires a step of forming the solder bump 22 on the electrode 21 of the semiconductor element 20, so that the manufacturing cost is high compared to an element that does not require the solder bump, and the substrate and the element are combined. There is a problem that the cost of the entire electronic circuit configured becomes high.
[0011]
The present invention has been made in view of the above-described problems of the prior art, and does not cause misalignment between the position of the pad on the substrate side and the electrode of an electronic component such as a semiconductor element, and the electrode of the electronic component. PROBLEM TO BE SOLVED: To provide an electronic component integrated multilayer wiring board that does not require the formation of solder bumps, and a method of manufacturing the same
(Purpose)
[0012]
[Means for Solving the Problems]
In the method of manufacturing an electronic component-integrated multilayer substrate according to the present invention, when an electronic component having an electrode formed on one surface serving as a substrate connection surface is used, a treatment hole in which a holding hole into which the electronic component is fitted is formed. The installation process of fitting the electronic component so that the board connection surface is exposed in the holding hole using the tool, and the part other than the interlayer connection part of the board connection surface in the state where the first interlayer connection part is connected and formed to the electrode A first resin layer forming step of covering the surface of the jig with an insulating first resin layer, and a first circuit for forming a first circuit layer connected to the first interlayer connection on the first resin layer And a second resin layer formation in which a portion other than the second interlayer connection portion is covered with an insulating second resin layer in a state in which the second interlayer connection portion is connected and formed on a part of the first circuit layer. And a second circuit layer for forming a second circuit layer connected to the second interlayer connection on the second resin layer And forming step, characterized in that it comprises a step in order to peel a jig.
[0013]
According to the above procedure, since the interlayer connection, resin layer, and circuit layer are sequentially laminated from the element side with reference to the electronic component, the positional relationship between the electronic component and the substrate side is accurately determined. Can keep. Further, since the interlayer connection portion can be formed by means such as plating, the connection reliability can be kept higher than when the electronic component and the circuit layer are connected by solder.
[0014]
As the first resin layer forming step, the following two methods are conceivable. The first is a method in which a first layer post is first formed as a first interlayer connection portion on an electrode, and then a first resin layer is formed around the post. Second, a first resin layer is first formed on the entire surface of the substrate connection surface and the surface of the jig, an opening reaching the electrode is formed in the resin layer, and the first interlayer connection portion is formed in the formed opening. It is a method of forming. In the second method, the first interlayer connection portion can be formed as a solid post (metal column) filling the opening, or can be formed as a film attached to the surface of the opening.
[0015]
When the second method described above is used, in the first circuit layer forming step, a conductor layer formed continuously and collectively at the time of forming the first interlayer connection portion can be used. That is, when the first interlayer connection portion is formed by plating, the conductor layer can be formed in a state where the first resin layer is also plated to be continuous with the first interlayer connection portion.
[0016]
In addition, in the method of manufacturing an electronic component integrated multilayer substrate according to the present invention, when an electronic component having a lead or bump formed on one surface serving as a substrate connection surface is used, a holding hole into which the electronic component is fitted is provided. A first resin that covers the substrate connection surface and the surface of the jig with an insulating first resin layer using the formed jig to fit the electronic component so that the lead or bump protrudes into the holding hole. A first circuit layer forming step of forming a first circuit layer connected to the first interlayer connection portion made of leads or bumps on the first resin layer; a first circuit layer forming part of the first circuit layer; A second resin layer forming step of covering a portion other than the second interlayer connection portion with an insulating second resin layer in a state where the two interlayer connection portions are connected and formed, and the second interlayer connection on the second resin layer Step of forming a second circuit layer connected to the portion , Characterized in that it comprises a step of separating the fixture in order.
[0017]
Also in the second resin layer forming step, similarly to the description in the first resin layer forming step, the first method of first forming the post as the second interlayer connection portion and then forming the resin layer later, A second method of forming the opening after forming the second resin layer can be selected. Further, when the second method is used, the second circuit layer can be formed by using a conductor layer that is continuously and collectively formed when the second interlayer connection portion is formed.
[0018]
Furthermore, the electronic component integrated multilayer substrate according to the present invention includes a multilayer buildup substrate in which a plurality of circuit layers are laminated via an insulating resin layer, and at least a circuit layer connected to the surface layer of the buildup substrate. In a structure including one electronic component, an interlayer connection portion that electrically connects the electronic component and the surface circuit layer is formed between the electronic component and the surface circuit layer. The electronic component is covered with an insulating resin layer formed with a thickness substantially equal to the distance between the component and the surface circuit layer, and the electronic component is fixed to the substrate by the resin layer.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of a method for manufacturing an electronic component integrated multilayer substrate according to the present invention will be described. FIG. 1 is a flowchart showing steps and steps of the first embodiment, and FIGS. 2 to 7 are cross-sectional views showing the structure of the multilayer substrate at each step.
[0020]
The first embodiment is a method suitable for a case where a semiconductor element having an electrode pad formed on one surface serving as a substrate connection surface is used as an electronic component. First, the outline of the process will be described based on FIG. 1, and then each process will be described in more detail with reference to cross-sectional views.
[0021]
The manufacturing method according to the first embodiment includes an installation process A (S.1) in which a semiconductor element is installed in a holding hole of a jig, and a first resin layer that covers the surface of the element and the jig with an insulating first resin layer. Resin layer forming step B (S.2 to S.7), first circuit layer forming step C (S.8 to S.12) for forming the first circuit layer on the first resin layer, and the first circuit Second resin layer forming step D (S.13 to S.20) for covering the layer with an insulating second resin layer, and a second circuit layer forming step for forming a second circuit layer on the second resin layer E (S.21 to S.25) and a step F (S.28) of peeling the jig are included in this order. When the circuit layer of the multilayer substrate has two layers, each process A to F is performed once and the entire process is completed. To form three or more circuit layers, the second resin layer forming process D, only the part of the second circuit layer forming step E is repeatedly executed.
[0022]
In the installation step A, as shown in FIG. 2A, a plate-like jig 40 having a holding hole 41 into which the semiconductor element 30 is fitted is used, and the substrate connection surface 31 on which the electrode pad 32 is formed is formed. The semiconductor element 30 is fitted into the holding hole 41 so as to be exposed (S.1). Since the jig 40 is peeled off from the semiconductor element 30 after completion, the surface thereof, in particular, the inner surface of the holding hole 41 and the surface 42 are subjected to surface processing with a highly peelable fluororesin or the like. In this example, only a single semiconductor element 30 is shown as an electronic component for simplicity, and the holding hole 41 is also single. However, when a plurality of electronic components are mounted, What is necessary is just to prepare the jig | tool with which the holding hole was formed.
[0023]
In the first resin layer forming step B, in a state where the first interlayer connection portion is connected and formed to the electrode pad 32, the portion other than the interlayer connection portion on the substrate connection surface and the surface of the jig are insulative first resin. Cover with layers. In this example, the first resin layer forming step B includes a step of forming a first layer post as a first interlayer connection on the electrode pad 32 and a step of forming a first resin layer around the post after the formation of the post. Including.
[0024]
In the stage of forming the first layer post, a photosensitive resist layer (plating resist) 50 is formed to cover the substrate connection surface 31 and the surface 42 of the jig 40 (S.2, FIG. 2B). An opening 50a reaching the electrode is formed at the post formation position of the resist layer 50 through an exposure / development process (S.3, FIG. 2 (c)). Subsequently, a first layer post 51 is formed in the opening 50a by plating (S.4, FIG. 3 (d)). After the formation of the first layer post 51, the resist layer 50 is removed (S.5, FIG. 3 (e)). As the plating metal, metals such as copper, nickel, gold, silver, platinum, and rhodium, or an alloy of tin and gold, nickel and phosphorus, or the like can be used. The plating may be electrolytic plating if the electrode pad 32 can be energized. Otherwise, electroless plating is performed.
[0025]
After the formation of the first layer post 51, the first resin layer 52 is formed on the entire surface of the jig 40 so as to cover it (S.6, FIG. 3 (f)). As the resin material, an epoxy resin, a BT resin, or the like can be used, and as a forming method, any means such as screen printing or application by a curtain coat method can be used. In step S.7, in order to expose the head of the first layer post 51 buried in the first resin layer 52, the surface of the first resin layer 52 is mechanically used with a polishing apparatus such as a buff or a belt sander. Grind. FIG. 4G shows the state after polishing.
[0026]
In the first circuit layer forming step C, the first circuit layer is formed while being connected to the first layer post 51. First, the conductor layer 53 is formed on the first layer post 51 and the first resin layer 52 by plating (S.8, FIG. 4 (h)). The conductor layer 53 is formed first by electroless copper plating and then by electrolytic copper plating using the formed copper foil. Subsequently, a photosensitive resist layer (etching resist) is formed on the conductor layer 53 (S.9), and the resist layer is exposed and developed in a predetermined pattern to form a resist layer on the conductive portion of the first circuit layer. Leave (S.10). Then, the conductor layer 53 in the region not covered with the resist layer is removed by etching (S.11), and only the necessary portion of the conductor layer 53 is left by removing the resist layer, thereby forming the first circuit layer. (S.12, FIG. 4 (i)).
[0027]
In the second resin layer forming step D, a portion other than the second interlayer connection portion is covered with an insulating second resin layer in a state where the second interlayer connection portion is connected and formed on a part of the first circuit layer 53. A step of forming a second layer post as a second interlayer connection on the first circuit layer 53 and a step of forming a second resin layer around the post after the formation of the post.
In the step of forming the second layer post, the power supply film 54 is formed on the first circuit layer 53 and the first resin layer 52 (S.13, FIG. 5 (j)), and the photosensitive film is formed on the power supply film 54. The resist layer (plating resist) 55 is formed (S.14), and an opening 55a reaching the first circuit layer 53 is formed at the post formation position of the resist layer 55 through the exposure / development process (S.15). FIG. 5 (k)).
[0028]
Subsequently, the power supply film 54 is energized to perform electrolytic plating, thereby forming the second layer post 56 in the opening 55a (S.16, FIG. 5 (l)) and removing the resist layer 55 (S. 17) and the power feeding film 54 is etched using the second layer post 56 as a mask (S.18, FIG. 6 (m)). Next, a second resin layer 57 is formed on the first resin layer 52 so as to cover the formed second layer post 56 and the first circuit layer 53 (S.19, FIG. 6 (n)), and the surface is formed. The second layer post 56 is cued by polishing (S.20, FIG. 6 (o)).
[0029]
The second circuit layer forming step E is a step of forming a second circuit layer connected to the second layer post 56 on the second resin layer 57. The step of forming a conductor layer and etching by a lithography technique are performed. Including stages. First, the conductive layer 58 connected to the second layer post 56 is formed on the second resin layer 57 by electroless copper plating and electrolytic copper plating (S.21, FIG. 7 (p)). A photosensitive resist layer (etching resist) is formed on the conductor layer 58 (S.22), and the resist layer is exposed and developed in a predetermined pattern to leave the resist layer in the conductive portion of the second circuit layer ( S.23), the conductor layer 58 in the region not covered with the resist layer is removed by etching (S.24). After the etching, the resist layer is removed to leave only a necessary portion of the conductor layer 58, thereby forming the second circuit layer (S.25, FIG. 7 (q)).
[0030]
The second resin layer forming step D and the second circuit layer forming step E are completed once when the number of layers of the multilayer circuit board is two, but when three or more layers are required, step S is performed. In step S.27, n is incremented from the branch of .26, and is repeatedly executed as many times as necessary. When the formation of the required number of resin layers and circuit layers is completed, the step F (S.28, FIG. 7 (r)) of peeling the jig 40 is performed, and a multilayer circuit is formed on the semiconductor element 30. The multilayer substrate thus formed is integrally formed, and the electronic component integrated substrate is completed.
In the completed electronic component integrated substrate, a first layer post 51 is formed between the semiconductor element 20 and the surface layer (first circuit layer 53) as an interlayer connection portion for electrically connecting the two. 53 is covered with an insulating resin layer 52 formed with a thickness substantially equal to the distance between the semiconductor element 20 and the first circuit layer 53 at a portion other than the first layer post 51, and the electronic component is formed by the resin layer 52. 20 is fixed to the substrate.
[0031]
According to the first embodiment, since the multilayer circuit board is laminated on the basis of the semiconductor element 30, the resin constituting the substrate is compared with the case where the semiconductor element is attached to the multilayer board formed as in the prior art. The element and the circuit on the substrate side can be accurately connected without being affected by the expansion and contraction of the substrate. Therefore, it is not necessary to secure a large margin considering the expansion and contraction of the resin for joining the element and the circuit, and it is possible to easily cope with the miniaturization of the electrode pitch. Further, by using a post formed by plating for the connection between the electrode pad 32 and each circuit layer, a stronger and more reliable electrical connection can be obtained as compared with the conventional solder connection.
[0032]
Next, a second embodiment will be described. The second embodiment is a modification in which a part of the process of the first embodiment described above is changed. FIG. 8 is a flowchart of each process and stage, and FIG. 9 is a stage specific to the second embodiment. A cross-sectional view of the structure of the multilayer substrate is shown. The structure in other processes and steps is the same as that of the first embodiment.
[0033]
The manufacturing method according to the second embodiment includes an installation step A (S.51) in which a semiconductor element is installed in a holding hole of a jig, and a first resin layer that covers the surface of the element and the jig with an insulating first resin layer. Resin layer forming step B (S.52 to S.57), a first circuit layer forming step C (S.58 to S.62) for forming a first circuit layer on the first resin layer, and a first circuit A second resin layer forming step D (S.63 to S.69) for covering the layer with an insulating second resin layer, and a second circuit layer forming step for forming a second circuit layer on the second resin layer E (S.70 to S.74) and step F (S.78) for peeling the jig are included in this order.
[0034]
The installation process A and the first resin layer forming process B are the same as those in the first embodiment. At the stage where these steps are completed, the substrate is in the state shown in FIG.
[0035]
In the first circuit layer forming step C, the first circuit layer is formed while being connected to the first layer post 51. In this example, as shown in FIG. 9A, a power feeding film 60 for plating is formed on the first resin layer 52 (S.58), and a photosensitive resist layer (plating resist) is formed on the power feeding film 60. ) 61 is formed (S.59). Then, the resist layer 61 is exposed and developed in a predetermined pattern to leave a resist layer corresponding to the insulating portion of the first circuit layer (S.60). 53 is formed by electrolytic plating (S.61, FIG. 9B). After the conductor layer 53 is formed, the resist layer 61 is removed (S.62). At this stage, the power supply film 60 may be removed using the conductor layer 53 as a mask. In this example, the power supply film 60 is used for forming the second layer post in the second resin layer forming step D, and the post formation is performed. It will be removed later.
[0036]
The second resin layer forming step D includes a step of forming a second layer post and a step of forming a second resin layer around the post after the formation of the post. First, as shown in FIG. 9C, a photosensitive resist layer (plating resist) 55 is formed on the first circuit layer 53 and the power feeding film 60 (S.63), and is exposed and developed in a predetermined pattern. Thus, an opening 55a reaching the first circuit layer 53 is formed at the post formation position of the resist layer 55 (S.64). Subsequently, the power supply film 60 is energized to perform electrolytic plating, thereby forming the second layer post 56 in the opening 55a (S.65), removing the resist layer 55 (S.66), and subsequently Using the one circuit layer 53 as a mask, the power feeding film 60 is etched with a hydrogen peroxide-containing sulfuric acid aqueous solution or the like (S.67, FIG. 9D). At this stage, the power supply film 60 used to form the first circuit layer 53 is removed. Next, as in the first embodiment shown in FIGS. 6 (n) and (o), the first resin layer 52 is covered with the first resin layer 52 so as to cover the formed second layer post 56 and the first circuit layer 53. The second resin layer 57 is formed (S.68), and the second layer post 56 is cued by polishing the surface (S.69).
[0037]
The second circuit layer forming step E is the same as the first circuit layer forming step C. First, a power feeding film is formed (S.70), and a resist layer (plating resist) is formed thereon, and then exposure / development is performed. Then, a conductor layer is formed by electrolytic plating in the opening formed in the resist layer (S.73). After the formation of the conductor layer, the resist layer is removed (S.74). When three or more circuit layers are formed, n is incremented from the branch of step S.75 to step S.76 while leaving the power supply film to be used for the post formation of the next layer. Resin layer forming step D and second circuit layer forming step E are executed. When the formation of the required number of resin layers and circuit layers is completed, the feeding film formed in step S.70 of the last second circuit layer forming step E is removed by etching (S.77), and the jig 40 Step F (S. 78) is performed, and a multilayer substrate on which a multilayer circuit is formed is formed integrally with the semiconductor element 30 to complete an electronic component integrated substrate.
[0038]
In the second embodiment, since the power supply film is formed before the formation of the conductor layer of the circuit, the conductor layer can be formed by electrolytic plating, and the conductor layer is formed only in the finally required portion. Therefore, there is no need for etching after the formation, and the time required for forming the conductor layer can be shortened as compared with the first embodiment.
[0039]
FIG. 10 is a flowchart showing the steps and steps of the third embodiment, and FIGS. 11 to 14 are cross-sectional views showing the structure of the multilayer substrate at each step. As shown in FIG. 10, the manufacturing method according to the third embodiment also includes an installation step A (S. 101) in which a semiconductor element is installed in a holding hole of a jig, and the surface of the element and the jig is insulated. A first resin layer forming step B (S.102 to S.104) covered with the first resin layer, and a first circuit layer forming step C (S.105 to S) for forming the first circuit layer on the first resin layer. .109), a second resin layer forming step D (S.110 to S.112) for covering the first circuit layer with an insulating second resin layer, and a second circuit layer on the second resin layer. A second circuit layer forming step E (S.113 to S.117) to be formed and a step F (S.120) for peeling the jig are sequentially included.
[0040]
In the installation step A, as shown in FIG. 11A, the semiconductor element 30 is fitted into the holding hole 41 of the jig 40 so that the substrate connection surface 31 is exposed (S.1). The configuration of the jig 40 is the same as that of the first embodiment.
[0041]
In the first resin layer forming step B, in a state where the first interlayer connection portion is connected and formed to the electrode pad 32, the portion other than the interlayer connection portion on the substrate connection surface and the surface of the jig are insulative first resin. Cover with layers. In this example, the first resin layer forming step B forms the first resin layer 52 on the entire surface of the substrate connection surface 31 and the surface of the jig 40 (S.102, FIG. 11B), A step of forming an opening 52a reaching the electrode pad 32 of the semiconductor element 30 in one resin layer 52 (S.103, FIG. 11C), and a first layer post 51 as a first interlayer connection in the opening 52a. (S.103, FIG. 12 (d)).
[0042]
The first resin layer 52 is made of an insulating photosensitive epoxy resin or the like. In this case, the opening 52a can be formed by a chemical process by exposure and development. However, the photosensitive resin is not necessarily used, and any non-photosensitive insulating resin may be used, and the opening 52a may be formed by a physical process using a laser cutter or the like. After the opening is formed, the first resin layer 52 is thermoset.
[0043]
The first layer post 51 is formed by electroless plating or by using electrolytic plating in the middle. At this time, the metal deposited by filling the opening 52a becomes the first layer post 51, and the portion deposited on the surface of the first resin layer 52 around the opening 52a becomes the conductor layer 53 for forming the first circuit layer. . That is, in this example, step S.104 for forming the first layer post in the first resin layer forming step B and step S.105 for forming the conductor layer in the first circuit layer forming step C are continuously performed in the process. Executed.
[0044]
In the first circuit layer forming step C, the first circuit layer is formed while being connected to the first layer post 51. As described above, the conductor layer 53 is formed in succession to the formation of the first layer post 51 (S.105, FIG. 12D), and a photosensitive resist layer (etching resist) is formed thereon ( S.106), the resist layer is exposed and developed in a predetermined pattern to leave the resist layer in the conductive portion of the first circuit layer (S.107), and the conductor layer 53 in the region not covered with the resist layer is etched. Remove (S.108). After the etching, the resist layer is removed to leave only a necessary portion of the conductor layer 53, whereby the first circuit layer 53 is formed (S.109, FIG. 12 (e)).
[0045]
As the first interlayer connection portion, not only the post 51 filling the opening 52a as described above but also a via hole using a film 51a formed on the surface of the opening 52a as shown in FIG. A (Via Hole) type connection form can also be used.
[0046]
In the second resin layer forming step D, a portion other than the second interlayer connection portion is covered with an insulating second resin layer in a state where the second interlayer connection portion is connected and formed on a part of the first circuit layer 53. A step of forming a second resin layer 57 on the first circuit layer 53 (S.110, FIG. 13 (f)), and an opening reaching a part of the first circuit layer 53 in the second resin layer 57. 57a is formed (S.111, FIG. 13 (g)) and a second layer post 56 is formed in the opening 57a as a second interlayer connection (S.112, FIG. 13 (h)). Including.
[0047]
The second resin layer 57 is also a photosensitive epoxy resin like the first resin layer 52, and an opening 57a is formed by exposure and development. The second layer post 56 is formed by electroless plating or by using electrolytic plating in the middle. At this time, the metal deposited to fill the opening 57a becomes the second layer post 56, and the portion deposited on the surface of the second resin layer 57 around the opening 57a becomes the conductor layer 58 for forming the second circuit layer. . That is, in this example, the step S.112 for forming the second layer post in the second resin layer forming step D and the step S.113 for forming the conductor layer in the second circuit layer forming step E are continuously performed in the process. Executed.
[0048]
In the second circuit layer forming step E, the second circuit layer is formed while being connected to the second layer post 56. As described above, the conductor layer 58 is formed in succession to the formation of the second layer post 56 (S.113, FIG. 13 (h)), and a photosensitive resist layer (etching resist) is formed thereon ( S.114), exposing and developing the resist layer in a predetermined pattern, leaving the resist layer in the conductive portion of the first circuit layer (S.115), and etching the conductor layer 58 in the region not covered by the resist layer. Remove (S.116). After the etching, the resist layer is removed to leave only a necessary portion of the conductor layer 58, thereby forming the second circuit layer 58 (S.117, FIG. 14 (i)). As the second interlayer connection portion, a via hole type connection form can be used similarly to the first interlayer connection portion shown in FIG.
[0049]
When three or more circuit layers are formed, n is incremented in step S.119 from the branch of step S.118, and the second resin layer forming step D and the second circuit layer forming step E are executed. When the formation of the required number of resin layers and circuit layers is completed, the step F (S.120) of peeling the jig 40 is performed, and the multilayer substrate on which the multilayer circuit is formed is integrated with the semiconductor element 30. As a result, the electronic component integrated substrate is completed.
[0050]
According to the third embodiment, since the insulating resin layer is formed first, and an opening is formed in the insulating resin layer to form the interlayer connection portion, the post is first formed and then the resin layer is formed. The number of processes can be reduced from the first and second embodiments, and work efficiency can be improved. In addition, since the post which is the interlayer connection portion and the conductor of the circuit layer can be formed in a continuous process, the work becomes easier than performing them as separate processes.
[0051]
Next, a fourth embodiment will be described. The fourth embodiment is a modification in which a part of the process of the third embodiment described above is changed. FIG. 15 is a flowchart of each process and stage, and FIG. 16 is a stage specific to the fourth embodiment. A cross-sectional view of the structure of the multilayer substrate is shown. The structure in other processes and steps is the same as that of the third embodiment.
[0052]
The manufacturing method according to the fourth embodiment includes an installation process A (S.151) in which a semiconductor element is installed in a holding hole of a jig, and a first resin layer that covers the surface of the element and the jig with an insulating first resin layer. Resin layer forming step B (S.152 to S.157), first circuit layer forming step C (S.158 to S.160) for forming the first circuit layer on the first resin layer, and the first circuit A second resin layer forming step D (S.161 to S.166) for covering the layer with an insulating second resin layer, and a second circuit layer forming step for forming a second circuit layer on the second resin layer E (S.167 to S.1694) and a step F (S.172) for peeling the jig are included in this order.
[0053]
The first two steps of the installation process A and the first resin layer forming process B are the same as in the third embodiment. At the stage where these steps are completed, the substrate is in the state shown in FIG.
[0054]
Next, in the fourth embodiment, as shown in FIG. 16A, a power supply film 60 is formed inside the opening formed in the first resin layer 52 and on the surface of the first resin layer 52 (S.154). ) And a photosensitive resist layer (plating resist) is formed thereon (S.155). Then, the resist layer is exposed and developed in accordance with a predetermined pattern to leave the resist layer 61 in accordance with the insulating portion of the first circuit layer (S.156). . At this time, as shown in FIG. 16B, the metal deposited by filling the opening becomes the first layer post 51, and the portion deposited on the surface of the power supply film 60 outside the opening forms the first circuit layer. The conductor layer 53 becomes. That is, in this example, step S.157 for forming the first layer post in the first resin layer forming step B and step S.158 for forming the conductor layer in the first circuit layer forming step C are continuously performed in the process. Executed.
[0055]
In the first circuit layer forming step C, the first circuit layer is formed while being connected to the first layer post 51. As described above, the conductor layer 53 is formed following the formation of the first layer post 51 (S.158), the resist layer 61 is removed (S.159), and the power supply film 60 is formed using the conductor layer 53 as a mask. Are removed by etching (S.160).
[0056]
The second resin layer forming step D is the same as the first resin layer forming step B. First, the second resin layer is formed so as to cover the first circuit layer 53 (S.161), and an opening is formed in this. (S.162). Subsequently, a power feeding film is formed on the entire surface including the inside of the opening (S.163), a resist layer (plating resist) is formed, exposed and developed (S.164, S.165). Then, the second layer post is formed by conducting electroplating by energizing the power supply film (S.166), and the conductor layer used for the second circuit layer is continuously formed (S.167).
[0057]
The second circuit layer forming step E is also the same as the first circuit layer forming step C. After forming the conductor layer continuously on the second layer post, the resist layer is removed (S.168) The power feeding film is removed by etching using the mask (S.169). When three or more circuit layers are formed, n is incremented in step S.171 from the branch of step S.170, and the second resin layer forming step D and the second circuit layer forming step E are executed. When the formation of the required number of resin layers and circuit layers is completed, the step F (S.172) for peeling the jig 40 is performed, and the multilayer substrate on which the multilayer circuit is formed is integrated with the semiconductor element 30. As a result, the electronic component integrated substrate is completed.
[0058]
In the fourth embodiment, the post and the conductor layer can be formed by electrolytic plating using the power feeding film, and the conductor layer can be formed only in a portion that is finally required, so that the conductor can be formed later. It is not necessary to etch the layer, and the time required for forming the conductor layer can be shortened as compared with the third embodiment.
[0059]
FIG. 17 is a flowchart showing the steps and steps of the fifth embodiment, and FIGS. 18 to 22 are cross-sectional views showing the structure of the multilayer substrate at each step. The four embodiments described above show the case where a substrate is stacked on a single semiconductor element 30, but practically a large number of components are mounted on the substrate. In many cases, components to be mounted are semiconductor elements having solder bumps and leads formed on electrode pads, or components with leads such as capacitors. When such a component is used, it is not necessary to form the first layer post as the first interlayer connection as in the above embodiment. The fifth embodiment is a method suitable for the case of using an electronic component in which leads or bumps are formed on one surface serving as a substrate connection surface.
[0060]
In the manufacturing method of the fifth embodiment, the installation step A (S. 201) for fitting the electronic component so that the lead or bump protrudes into the holding hole of the jig and the surface of the component and the jig are insulated. First resin layer forming step B (S.202, 203) covered with the first resin layer, and first circuit layer forming step C (S.204 to S.209) for forming the first circuit layer on the first resin layer, The second resin layer forming step D (S.210 to S.217) for covering the first circuit layer with the second resin layer, and the second circuit layer forming for forming the second circuit layer on the second resin layer Step E (S.218 to S.222) and stage F (S.225) for peeling the jig are included in this order. When the circuit layer of the multilayer substrate has two layers, each process A to F is performed once and the entire process is completed. To form three or more circuit layers, the second resin layer forming process D, only the part of the second circuit layer forming step E is repeatedly executed.
[0061]
In the installation step A, as shown in FIG. 18A, the semiconductor element 33 having the solder bump 33a formed on the electrode pad, the capacitor 34 having the lead 34a, and the semiconductor element 35 having the lead 35a formed thereon are respectively bumped. And it is made to fit in the holding hole of the jig 45 so that the lead protrudes (S.201).
[0062]
In the first resin layer forming step B, each component and the surface of the jig are covered with an insulating first resin layer 52 (S.202, FIG. 18 (b)), and then all the bumps and leads are first. The leads and the resin layer are polished until they appear on the surface of the resin layer 52 (S.203, FIG. 18 (c)). Since the bumps and leads of each component have different lengths, the solder bumps 33a of the semiconductor element 33 and the leads 35a of the semiconductor element 35 are buried in the first resin layer 52 when the first resin layer 52 is formed. The lead 34 a of the capacitor 34 protrudes from the first resin layer 52. This is mechanically polished by an apparatus such as a buff or a belt sander to adjust the height, and all leads and bumps are exposed on the surface.
[0063]
In the above case, it is desirable to apply the first resin layer 52 by a non-contact method such as a curtain coating method. However, when the leads and bumps are all the same height, or when the lead heights are trimmed before the first resin layer 52 is formed, a simple coating method such as screen printing may be used. it can.
[0064]
In the first circuit layer forming step C, a conductor layer 53 for forming the first circuit layer on the polished surface is formed by electroless plating or by using electrolytic plating in the middle (S.204, FIG. 19). (d)) A photosensitive resist layer (etching resist) is formed thereon (S.205), and this is exposed and developed in a predetermined pattern to leave a resist layer in the conductive portion of the first circuit layer ( S.207). Then, the conductor layer 53 in a region not covered with the resist layer is removed by etching (S.208), and only the necessary portion of the conductor layer 53 is left by removing the resist layer, thereby forming the first circuit layer. (S.209, FIG. 19 (e)). In the first circuit layer forming step C, as described in the second embodiment, a power feeding film is first formed on one surface, a resist layer (plating resist) is formed thereon, and this is exposed. A method of removing the resist layer and the power feeding film after removing the resist layer in the portion where the conductor layer is formed by development and forming the conductor layer in the necessary portion by electrolytic plating can also be used.
[0065]
In the second resin layer forming step D, a portion other than the second interlayer connection portion is covered with an insulating second resin layer in a state where the second interlayer connection portion is connected and formed on a part of the first circuit layer 53. A step of forming a second layer post as a second interlayer connection on the first circuit layer 53 and a step of forming a second resin layer around the post after the formation of the post. In the step of forming the second layer post, the power supply film 54 is formed on the first circuit layer 53 and the first resin layer 52 (S.210, FIG. 20 (f)), and the photosensitive film is formed on the power supply film 54. The resist layer (plating resist) 55 is formed (S.211), and an opening 55a reaching the first circuit layer 53 is formed at the post formation position of the resist layer 55 through the exposure / development process (S.212). FIG. 20 (g)).
[0066]
Subsequently, the power supply film 54 is energized and electrolytically plated to form a second layer post 56 in the opening 55a (S.213, FIG. 20 (h)), and the resist layer 55 is removed (S. 214), and the feed film 54 is etched using the second layer post 56 as a mask (S.215, FIG. 21 (i)). Next, a second resin layer 57 is formed on the first resin layer 52 so as to cover the formed second layer post 56 and the first circuit layer 53 (S.216, FIG. 21 (j)), and the surface is formed. The second layer post 56 is cued by polishing (S.217, FIG. 21 (k)).
[0067]
In the second circuit layer forming step E, the second circuit layer is formed while being connected to the second layer post 56. As described above, the conductor layer 58 to be the second circuit layer is formed on the second resin layer 57 with the second layer post 56 exposed on the surface of the second resin layer 57 (S.218, FIG. 22 (l)). Then, a photosensitive resist layer (etching resist) is formed on the conductor layer 58 (S.219), and the resist layer is exposed and developed in a predetermined pattern to leave the resist layer in the conductive portion of the second circuit layer. (S.220), the conductor layer 58 in a region not covered with the resist layer is removed by etching (S.221). After the etching, the resist layer is removed to leave only a necessary portion of the conductor layer 58, whereby the second circuit layer 58 is formed (S.222, FIG. 22 (m)).
[0068]
When three or more circuit layers are formed, n is incremented in step S.224 from the branch of step S.223, and the second resin layer forming step D and the second circuit layer forming step E are executed. When the formation of the required number of resin layers and circuit layers is completed, the step F (S.225, FIG. 22 (n)) of peeling the jig 45 is executed, and the electronic components 33, 34, and 35 are multilayered. The multilayer substrate on which the circuit is formed is integrally formed, and the electronic component integrated substrate is completed.
[0069]
According to the fifth embodiment, when an electronic component having leads and bumps is used, a circuit layer can be formed based on these leads and bumps, and the electronic component is fixed to a completed substrate. In comparison, the element and the circuit on the substrate side can be accurately connected without being influenced by the expansion and contraction of the resin constituting the substrate.
[0070]
【The invention's effect】
As described above, according to the manufacturing method of the present invention, the interlayer connection portion, the resin layer, and the circuit layer are sequentially laminated from the element side on the basis of the electronic component, and therefore the positional relationship between the electronic component and the substrate side. Can be kept accurate. Therefore, it is not necessary to secure a large margin considering the expansion and contraction of the resin for joining the element and the circuit, and it is possible to easily cope with the miniaturization of the electrode pitch. Further, since the interlayer connection portion can be formed by means such as plating, the connection reliability can be kept higher than when the electronic component and the circuit layer are connected by solder.
[0071]
When the method of forming the first layer post as the first interlayer connection on the electrode first and then forming the first resin layer around the post as in claim 2, the number of steps is However, since there is no need to form an opening in the resin layer later, there is an advantage that the type of resin is not limited. On the other hand, as in claim 3, the first resin layer is first formed on the entire surface of the substrate connection surface and the surface of the jig, an opening reaching the electrode is formed in the resin layer, and the first resin layer is formed in the formed opening. In the case of adopting a method for forming one interlayer connection portion, for example, a photosensitive resin is used or an opening needs to be formed by a laser cutter or the like, but the number of steps may be made smaller than that in the case of claim 2. It is possible to shorten the manufacturing process time.
[0072]
In the method of claim 3, if the conductor layer is formed continuously when forming the first interlayer connection portion as in claim 4, the number of actual steps can be further reduced and these can be separated. The process becomes easier than the process.
[0073]
In the case where a semiconductor element having solder bumps or leads formed on electrode pads or a component with leads such as a capacitor is used, a circuit layer is formed on the basis of these leads and bumps by using the method of claim 5. Compared with the case where the electronic component is fixed to the completed substrate, the element and the circuit on the substrate side can be accurately connected without being influenced by the expansion and contraction of the resin constituting the substrate.
[0074]
Also in the second resin layer forming step, as in claim 6, first, a post is formed as a second interlayer connection portion and a resin layer is formed later. The method of forming the opening after forming the two resin layers can be selected. In the method of claim 7, the conductor layer can be formed continuously when the second interlayer connection portion is formed as in claim 8. The method of claim 6 has the advantage that the type of resin is not limited, the method of claim 7 has the advantage that the number of steps can be reduced, and the method of claim 8 can be even less than the method of claim 7. There is an advantage that you can.
[Brief description of the drawings]
FIG. 1 is a flowchart showing a method for manufacturing an electronic component integrated multilayer substrate according to a first embodiment.
FIG. 2 is a cross-sectional view of a substrate showing each step (1) of the method of the first embodiment.
FIG. 3 is a cross-sectional view of a substrate showing each step (2) of the method of the first embodiment.
FIG. 4 is a cross-sectional view of a substrate showing each step (No. 3) of the method according to the first embodiment;
FIG. 5 is a cross-sectional view of a substrate showing each step (No. 4) of the method according to the first embodiment;
FIG. 6 is a cross-sectional view of a substrate showing each step (No. 5) of the method according to the first embodiment;
FIG. 7 is a cross-sectional view of a substrate showing each step (No. 6) of the method according to the first embodiment;
FIG. 8 is a flowchart showing a method for manufacturing an electronic component-integrated multilayer substrate according to a second embodiment.
FIG. 9 is a cross-sectional view of a substrate showing characteristic steps of the method of the second embodiment.
FIG. 10 is a flowchart showing a method for manufacturing an electronic component-integrated multilayer substrate according to a third embodiment.
FIG. 11 is a cross-sectional view of a substrate showing each step (1) of the method of the third embodiment.
FIG. 12 is a cross-sectional view of a substrate showing each step (2) of the method of the third embodiment.
FIG. 13 is a cross-sectional view of a substrate showing each step (No. 3) of the method of the third embodiment.
FIG. 14 is a cross-sectional view of a substrate showing each step (No. 4) in the method of the third embodiment.
FIG. 15 is a flowchart showing a method for manufacturing an electronic component-integrated multilayer substrate according to a fourth embodiment.
FIG. 16 is a cross-sectional view of a substrate showing the characteristic steps of the method of the fourth embodiment.
FIG. 17 is a flowchart showing a method for manufacturing an electronic component-integrated multilayer substrate according to a fifth embodiment.
FIG. 18 is a cross-sectional view of a substrate showing each step (No. 1) of the method according to the fifth embodiment.
FIG. 19 is a sectional view of a substrate showing each step (2) of the method of the fifth embodiment.
FIG. 20 is a cross-sectional view of a substrate showing each step (No. 3) in the method of the fifth embodiment.
FIG. 21 is a cross-sectional view of a substrate showing each step (No. 4) in the method of the fifth embodiment;
FIG. 22 is a cross-sectional view of the substrate showing each stage (No. 5) of the method according to the fifth embodiment.
FIG. 23 is a cross-sectional view of a substrate showing each stage (No. 1) of a conventional method for producing an electronic component-integrated multilayer substrate.
FIG. 24 is a cross-sectional view of a substrate showing each stage (No. 2) of the conventional method of manufacturing an electronic component-integrated multilayer substrate.
FIG. 25 is a cross-sectional view of a substrate showing each stage (No. 3) of the conventional method for producing an electronic component-integrated multilayer substrate;
FIG. 26 is a cross-sectional view of a substrate showing each stage (No. 4) of the conventional method of manufacturing an electronic component-integrated multilayer substrate.
[Explanation of symbols]
30 Semiconductor elements
40 Jig
51 1st layer post
52 1st resin layer
53 First circuit layer
56 2nd layer post
57 Second resin layer
58 Second circuit layer

Claims (8)

In a method for manufacturing an electronic component-integrated multilayer substrate comprising at least one electronic component having an electrode formed on one surface serving as a substrate connection surface, and a multilayer buildup substrate to which the electronic component is attached,
Using a jig in which a holding hole into which the electronic component is fitted is formed, and an installation step for fitting the electronic component so that the board connection surface is exposed in the holding hole;
A first resin layer that covers a portion of the substrate connection surface other than the interlayer connection portion and the surface of the jig with an insulating first resin layer in a state where the first interlayer connection portion is connected to and formed on the electrode. Forming process;
A first circuit layer forming step of forming a first circuit layer connected to the first interlayer connection on the first resin layer;
A second resin layer forming step of covering a portion other than the second interlayer connection portion with an insulating second resin layer in a state where the second interlayer connection portion is connected and formed on a part of the first circuit layer;
A second circuit layer forming step of forming a second circuit layer connected to the second interlayer connection portion on the second resin layer;
Method for manufacturing an electronic component-integrated multilayer substrate which comprises the steps of removing the jig in order. The first resin layer forming step includes a step of forming a first layer post as a first interlayer connection portion on the electrode, and a step of forming the first resin layer around the post after the formation of the post. The method of manufacturing an electronic component-integrated multilayer substrate according to claim 1. The first resin layer forming step includes forming the first resin layer on the entire surface of the substrate connection surface and the surface of the jig, and forming an opening reaching the electrode in the first resin layer. 2. The method for manufacturing an electronic component-integrated multilayer substrate according to claim 1, further comprising: sequentially forming the first interlayer connection portion in the opening.   The said 1st circuit layer formation process forms the said 1st circuit layer using the conductor layer formed collectively in a lump at the time of formation of the said 1st interlayer connection part. Manufacturing method for electronic component integrated multilayer substrate. In a method of manufacturing an electronic component integrated multilayer substrate comprising at least one electronic component having a lead or bump formed on one surface serving as a substrate connection surface, and a multilayer buildup substrate to which the electronic component is attached,
Using a jig in which a holding hole into which the electronic component is fitted is formed, and an installation step of fitting the electronic component into the holding hole so that the lead or bump protrudes from the holding hole;
A first resin layer forming step of covering the substrate connection surface and the surface of the jig with an insulating first resin layer;
A first circuit layer forming step of forming a first circuit layer connected to a first interlayer connecting portion made of the leads or bumps on the first resin layer;
A second resin layer forming step of covering a portion other than the second interlayer connection portion with an insulating second resin layer in a state where the second interlayer connection portion is connected and formed on a part of the first circuit layer;
A second circuit layer forming step of forming a second circuit layer connected to the second interlayer connection portion on the second resin layer;
Method for manufacturing an electronic component-integrated multilayer substrate which comprises the steps of removing the jig in order.   The second resin layer forming step includes a step of forming a post as a second interlayer connection portion on the first circuit layer, and a step of forming the second resin layer around the post after the formation of the post. A method for producing an electronic component-integrated multilayer substrate according to any one of claims 1 to 5.   The second resin layer forming step includes a step of covering the first circuit layer and forming the second resin layer on the entire surface of the first resin layer, and an opening reaching the first circuit layer in the second resin layer 6. The method of manufacturing an electronic component-integrated multilayer substrate according to claim 1, further comprising: a step of forming the second interlayer connection portion in the opening.   The said 2nd circuit layer formation process forms the said 2nd circuit layer using the conductor layer formed collectively collectively at the time of formation of the said 2nd interlayer connection part, The said 2nd circuit layer formation process is characterized by the above-mentioned. Manufacturing method for electronic component integrated multilayer board.

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