JP2018060918A - Method for manufacturing wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board with a higher flatness and capable of successfully connecting an electrode of the component to be mounted and an electrode of the wiring board.SOLUTION: A method for manufacturing a wiring board comprises the steps of: forming a base insulating layer on a substrate (base insulating layer forming step ST1); flattening a surface of the base insulating layer (front and rear surface flattening step ST2); coating the base insulating layer with a metal thin film (thin film coating step ST3); forming a groove in a photoresist layer laminated on the base insulating layer (groove forming step ST4); filling the groove with metal (metal filling step ST5); removing the photoresist layer (photoresist layer removing step ST7); removing the exposed metal thin film (metal thin film removing step ST8); forming a circuit pattern layer by filling an insulating member between the circuit patterns (circuit pattern layer forming step ST9); and flattening a surface of the insulating member of the circuit pattern layer (circuit pattern layer flattening step ST10).SELECTED DRAWING: Figure 2

Description

  The present invention relates to a method for manufacturing a wiring board.

  2. Description of the Related Art Conventionally, a technique related to a wiring board having a rewiring layer such as an interposer or a printed wiring board that mounts and mounts a semiconductor chip or various electrical components and ensures conduction between these electrodes and other components is known. For example, Patent Document 1 discloses a build-up type wiring substrate in which conductor layers and organic insulating layers are alternately stacked on the front and back surfaces of a core substrate.

  Further, in Patent Document 2, a first insulating layer formed by impregnating a reinforcing material with resin is provided on both surfaces of a core substrate provided with a reinforcing material, and after reinforcing the core substrate with the first insulating layer, the reinforcing material is applied. A wiring board in which a plurality of second insulating layers not contained is laminated is disclosed. This wiring board includes a reinforcing material in the core substrate and the first insulating layer, or when the thermal history is applied by making the thickness of the first insulating layer thicker than the thickness of each second insulating layer. Suppressing the occurrence of warping.

JP 2001-196743 A JP 2013-80823 A

  The semiconductor chips and various electrical components mounted on the wiring board described in Patent Documents 1 and 2 are becoming lighter, thinner and smaller, the electrodes connected to the electrodes of the wiring board are also smaller, and the distance between the electrodes is narrower. It has become. For this reason, if the wiring board is warped or not flat, the electrodes of the semiconductor chip and various electrical components to be mounted and the electrodes of the wiring board cannot be satisfactorily connected, resulting in a malfunction. As described above, the wiring board described in Patent Document 2 suppresses the occurrence of warping when a thermal history is applied, but the core board is originally warped only by suppressing deformation due to the thermal history. If it is not flat, it may not be formed flat.

  The present invention has been made in view of the above, and an object of the present invention is to provide a wiring board with higher flatness that can be more favorably connected to electrodes of components to be mounted.

  In order to solve the above-described problems and achieve the object, the present invention is a method of manufacturing a wiring board having a rewiring layer on the front and back surfaces, and a resin base insulating layer is formed on the front and back surfaces of the core substrate A base insulating layer forming step, a front and back flattening step for flattening the surface of the base insulating layer on the front and back surfaces with a bite tool or a grinding wheel, and a metal thin film on the surface of the base insulating layer on the flattened front and back surfaces A thin film coating step for coating, a photoresist layer is laminated on the base insulating layer through the metal thin film, a groove to be a circuit pattern is formed in the photoresist layer by photoetching, and the metal thin film is exposed at the groove bottom A groove forming step for forming the metal thin film as an electrode, a metal filling step for filling the groove to be the circuit pattern with a metal by plating, and a step of applying the metal from the upper surface of the base insulating layer. A photoresist layer removing step for removing the photoresist layer leaving a pattern; a metal thin film removing step for removing the exposed metal thin film from the base insulating layer after performing the photoresist layer removing step; After carrying out the thin film removal step, a circuit pattern layer forming step for filling a gap between the circuit patterns with a resin insulating member to form a circuit pattern layer in which the adjacent circuit patterns are insulated; and And a circuit pattern layer flattening step in which the surface of the insulating member is cut and flattened with a bite tool, and a flat wiring substrate is formed by the front and back flattening step and the circuit pattern layer flattening step.

  Further, after the metal filling step and before the photoresist layer removing step, the surface of the metal filled in the groove is shaved with a bite tool together with the photoresist layer, and the surface of the circuit pattern of the metal is flattened. It is preferable to provide a circuit pattern flattening step.

  Further, it is preferable that the circuit pattern is further laminated on the circuit pattern layer.

  Therefore, the method for manufacturing a wiring board according to the present invention produces an effect that it is possible to provide a wiring board with higher flatness, which can be more satisfactorily connected to electrodes of mounted electrical components. .

FIG. 1 is a cross-sectional view illustrating a wiring board manufactured by the wiring board manufacturing method according to the embodiment. FIG. 2 is a flowchart showing a flow of the method of manufacturing the wiring board according to the first embodiment. FIG. 3 is a diagram illustrating a base insulating layer forming step of the method for manufacturing the wiring board according to the first embodiment. FIG. 4 is a diagram illustrating front and back planarization steps of the method for manufacturing a wiring board according to the first embodiment. FIG. 5 is a diagram illustrating another example of the front / back planarization step of the method for manufacturing the wiring board according to the first embodiment. FIG. 6 is a diagram illustrating the substrate and the base insulating layer after the front / back planarization step of the method for manufacturing the wiring substrate according to the first embodiment. FIG. 7 is a view showing a thin film coating step of the method for manufacturing a wiring board according to the first embodiment. FIG. 8 is a view showing a state in which a photoresist layer is formed in the groove forming step of the manufacturing method of the wiring board according to the first embodiment. FIG. 9 is a view showing a state in which grooves are formed in the photoresist layer in the groove forming step of the method for manufacturing the wiring board according to the first embodiment. FIG. 10 is a diagram illustrating a metal filling step of the method for manufacturing the wiring board according to the first embodiment. FIG. 11 is a diagram illustrating a circuit pattern flattening step in the method for manufacturing a wiring board according to the first embodiment. FIG. 12 is a diagram illustrating a state after the circuit pattern flattening step in the method for manufacturing the wiring board according to the first embodiment. FIG. 13 is a view showing a photoresist layer removing step of the method for manufacturing the wiring board according to the first embodiment. FIG. 14 is a diagram illustrating a metal thin film removal step of the method for manufacturing a wiring board according to the first embodiment. FIG. 15 is a diagram illustrating a circuit pattern layer forming step of the method for manufacturing a wiring board according to the first embodiment. FIG. 16 is a diagram illustrating a step of planarizing a circuit pattern layer in the method for manufacturing a wiring board according to the first embodiment. FIG. 17 is a diagram illustrating the substrate and the circuit pattern layer after the circuit pattern layer planarization step of the method for manufacturing the wiring substrate according to the first embodiment. FIG. 18 is a diagram illustrating a state in which a part of the insulating member illustrated in FIG. 17 is removed and a part of the circuit pattern is exposed.

  DESCRIPTION OF EMBODIMENTS Embodiments (embodiments) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited by the contents described in the following embodiments. The constituent elements described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the structures described below can be combined as appropriate. Various omissions, substitutions, or changes in the configuration can be made without departing from the scope of the present invention.

  A method for manufacturing a wiring board according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view illustrating a wiring board manufactured by the wiring board manufacturing method according to the embodiment. A wiring board 1 shown in FIG. 1 is a wiring board having a rewiring layer such as an interposer or a printed wiring board that mounts and mounts semiconductor chips and various electrical components and ensures conduction between these electrodes and other components. is there. In the first embodiment, the wiring board 1 is an interposer that mounts a semiconductor chip and is connected to the printed wiring board and connects the electrodes of the semiconductor chip and the wiring pattern of the printed wiring board according to a predetermined pattern. .

  As shown in FIG. 1, the wiring substrate 1 is formed on at least one layer on the base substrate 10, the base insulating layer 20 formed on both the front surface 10 a and the back surface 10 b of the substrate 10, and the base insulating layer 20. And a circuit pattern layer 30 which is a rewiring layer. The wiring substrate 1 includes a circuit pattern layer 30 on the front and back surfaces 10 a and 10 b of the substrate 10.

  The substrate 10 is an insulating (non-conductive) substrate formed of glass epoxy resin, ceramics, glass, or the like. The thickness of the substrate 10 is about 50 μm, for example. In the first embodiment, as shown in FIG. 1, the substrate 10 has a curved shape so as to draw a convex shape on the back surface 10b side (lower side in FIG. 1). In addition, in the drawings described below including FIG. 1, the degree of curvature actually generated in the substrate 10 is described in order to explain that the substrate 10 is curved.

  The base insulating layer 20 is made of an insulating resin. In the first embodiment, three circuit pattern layers 30 are formed on each base insulating layer 20, but the number of circuit pattern layers 30 formed on each base insulating layer 20 is not limited to three layers. The circuit pattern layer 30 includes a plurality of circuit patterns 31 made of a conductive metal and an insulating member 32.

  A plurality of circuit patterns 31 of the circuit pattern layer 30 formed on the base insulating layer 20 are arranged on the base insulating layer 20 according to a predetermined pattern. The circuit pattern 31 of the circuit pattern layer 30 formed on the circuit pattern layer 30 is disposed on the insulating member 32 or the circuit pattern 31 of the lower circuit pattern layer 30 near the base insulating layer 20. The insulating member 32 is made of an insulating resin, is filled in the gaps between the circuit patterns 31, and electrically insulates the circuit patterns 31 adjacent to each other.

  In Embodiment 1, the insulating member 32 of the base insulating layer 20 and each circuit pattern layer 30 is composed of a dry film type interlayer insulating material containing a resin material, and an Ajinomoto build-up film (hereinafter referred to as “Ajinomoto Fine Techno Co., Ltd.”). (Referred to as “ABF”). In the first embodiment, the insulating member 32 of the base insulating layer 20 and each circuit pattern layer 30 is made of ABF. However, the base insulating layer 20 and the insulating member 32 are not limited to the ABF. The insulating base layer 20 has a thickness of about 40 μm, for example.

  Each circuit pattern 31 is formed of a metal such as copper, for example. The height of each circuit pattern 31 (height in the stacking direction of each circuit pattern layer 30) is, for example, about 15 μm to 20 μm. Each circuit pattern 31 is electrically connected at a predetermined location as shown in FIG. A part of the circuit patterns 31 of the circuit pattern 31 of the outermost circuit pattern layer 30 in the circuit pattern layer 30 is exposed to the outside of the wiring substrate 1. The circuit pattern 31 exposed to the outside of the wiring board 1 is connected to an electrode of a semiconductor chip or a wiring pattern of a printed wiring board. The circuit pattern 31 includes a base insulating layer 20, a metal thin film 31a disposed on the insulating member 32 of the circuit pattern layer 30 on the lower layer side or the circuit pattern 31, and a metal 31b on the metal thin film 31a.

  In addition, the wiring substrate 1 has a through electrode that penetrates the substrate 10 from the front surface 10 a to the back surface 10 b and is connected to the circuit pattern layer 30. Similar to the circuit pattern 31, the through electrode is composed of a metal thin film 31a and a metal 31b on the metal thin film 31a. In the wiring board 1, the circuit pattern 31 exposed to the outside of the wiring board 1 is connected to the electrode of the semiconductor chip or the wiring pattern of the printed wiring board, and the circuit patterns 31 of the plurality of circuit pattern layers 30 are electrically connected at predetermined positions. As a result, the electrodes of the semiconductor chip and the wiring pattern of the printed wiring board are electrically connected according to a predetermined pattern.

  Next, a method for manufacturing a wiring board according to the first embodiment will be described. FIG. 2 is a flowchart showing a flow of the method of manufacturing the wiring board according to the first embodiment. FIG. 3 is a diagram illustrating a base insulating layer forming step of the method for manufacturing the wiring board according to the first embodiment. FIG. 4 is a diagram illustrating front and back planarization steps of the method for manufacturing a wiring board according to the first embodiment. FIG. 5 is a diagram illustrating another example of the front / back planarization step of the method for manufacturing the wiring board according to the first embodiment. FIG. 6 is a diagram illustrating the substrate and the base insulating layer after the front / back planarization step of the method for manufacturing the wiring substrate according to the first embodiment. FIG. 7 is a view showing a thin film coating step of the method for manufacturing a wiring board according to the first embodiment. FIG. 8 is a view showing a state in which a photoresist layer is formed in the groove forming step of the manufacturing method of the wiring board according to the first embodiment. FIG. 9 is a view showing a state in which grooves are formed in the photoresist layer in the groove forming step of the method for manufacturing the wiring board according to the first embodiment. FIG. 10 is a diagram illustrating a metal filling step of the method for manufacturing the wiring board according to the first embodiment. FIG. 11 is a diagram illustrating a circuit pattern flattening step in the method for manufacturing a wiring board according to the first embodiment. FIG. 12 is a diagram illustrating a state after the circuit pattern flattening step in the method for manufacturing the wiring board according to the first embodiment. FIG. 13 is a view showing a photoresist layer removing step of the method for manufacturing the wiring board according to the first embodiment. FIG. 14 is a diagram illustrating a metal thin film removal step of the method for manufacturing a wiring board according to the first embodiment. FIG. 15 is a diagram illustrating a circuit pattern layer forming step of the method for manufacturing a wiring board according to the first embodiment. FIG. 16 is a diagram illustrating a step of planarizing a circuit pattern layer in the method for manufacturing a wiring board according to the first embodiment. FIG. 17 is a diagram illustrating the substrate and the circuit pattern layer after the circuit pattern layer planarization step of the method for manufacturing the wiring substrate according to the first embodiment. FIG. 18 is a diagram illustrating a state in which a part of the insulating member illustrated in FIG. 17 is removed and a part of the circuit pattern is exposed.

  As shown in FIG. 2, a method of manufacturing a wiring board according to the first embodiment (hereinafter simply referred to as a manufacturing method) includes a base insulating layer forming step ST1, a front / back planarization step ST2, a thin film coating step ST3, a groove, Forming step ST4, metal filling step ST5, circuit pattern flattening step ST6, photoresist layer removing step ST7, metal thin film removing step ST8, circuit pattern layer forming step ST9, circuit pattern layer flattening step ST10 Is provided. If all the circuit pattern layers 30 have not been formed after the circuit pattern layer forming step ST9 (step ST11: No), the manufacturing method returns to the thin film coating step ST3 and all the circuit pattern layers 30 have been formed. By repeating the thin film coating step ST3 to the circuit pattern layer flattening step ST10 until it becomes (step ST11: Yes), the plurality of circuit pattern layers 30 of the wiring board 1 are laminated and formed.

  The base insulating layer forming step ST1 is a step of forming a resin base insulating layer 20 on the front and back surfaces 10a and 10b of the substrate 10 serving as a core. In the base insulating layer forming step ST1, as shown in FIG. 3, ABF made by Ajinomoto Fine Techno Co. is fixed to both the front surface 10a and the back surface 10b of the substrate 10 by thermocompression bonding or the like. At this time, the substrate 10 of the present embodiment is curved so as to draw a convex shape on the back surface 10b side (the lower side in the figure), and thus is fixed to the front surface 10a and the back surface 10b of the substrate 10 as shown in FIG. The surface 20 a of the base insulating layer 20 opposite to the substrate 10 is curved according to the shape of the substrate 10.

  The front / back planarization step ST2 is a step in which the surface 20a of the base insulating layer 20 on the front and back surfaces 10a, 10b of the substrate 10 is shaved and flattened with a cutting tool 41. As shown in FIG. 4, the front / back flattening step ST <b> 2 includes one of the front surface 10 a and the rear surface 10 b of the substrate 10 on the chuck table 42 having a holding surface 42 a formed from a metal pin chuck or the like of the cutting tool 40. The base insulating layer 20 on the side is sucked and held. Then, in the front and back flattening step ST2, the tool wheel 43 is rotated, and the tool wheel 43 is moved downward in the figure by a moving means (not shown), so that the tool tool 41 is insulated on the other side as shown in FIG. The chuck table 42 and the cutting tool 41 are moved relative to each other in a direction parallel to the holding surface 42a while being cut into the layer 20, and the surface 20a of the base insulating layer 20 on the other side is cut and flattened by the cutting tool 41. In the front and back surface flattening step ST2, after flattening the surface 20a of the base insulating layer 20 on the other side, the other base insulating layer 20 flattened on the chuck table 42 of the cutting tool 40 is sucked and held. Similarly, the surface 20a of the base insulating layer 20 is cut and flattened. When cutting with the bite wheel 43, a protective member such as an adhesive tape may be attached to the base insulating layer 20 on the side sucked and held by the chuck table 42.

  In the example shown in FIG. 4, the surface 20a of the base insulating layer 20 is cut and flattened with the cutting tool 41 of the cutting tool 40, but the front and back flattening step ST2 is performed as shown in FIG. 20a may be ground and flattened by the grinding wheel 51 of the grinding device 50. When the surface 20a of the base insulating layer 20 is ground and flattened by the grinding wheel 51 of the grinding device 50, the base insulating layer 20 is sucked and held on the chuck table 52 of the grinding device 50, and the grinding wheel 51 of the grinding device 50 is used as a base. The grinding wheel 53 is rotated while the chuck table 52 is rotated in contact with the insulating layer 20, and the surface 20 a of the base insulating layer 20 is cut and planarized by the grinding wheel 51. After the front and back planarization step ST2, as shown in FIG. 6, the surface 20a of the base insulating layer 20 on both the front and back surfaces 10a and 10b of the substrate 10 can be formed flat. When grinding with the grinding wheel 53, a protective member such as an adhesive tape may be attached to the base insulating layer 20 on the side sucked and held by the chuck table 52.

  Further, in the front / back planarization step ST2, after the surface 20a of the base insulating layer 20 is formed flat, in order to form a through electrode (not shown), the surface 10a side of the substrate 10 and the side of the substrate 10 are formed by ablation processing using laser light, for example. A through hole (through hole) (not shown) that penetrates both the base insulating layer 20 on the back surface 10b side and the substrate 10 itself is formed.

  The thin film coating step ST3 is a step of coating the metal thin film 31a on the surface 20a of the base insulating layer 20 of the front and back surfaces 10a and 10b of the flattened substrate 10. In the thin film coating step ST3, as shown in FIG. 7, a conductive metal is formed on the base insulating layer 20 on both the front surface 10a side and the back surface 10b side of the substrate 10 and the inner surface of a through hole for a through electrode (not shown). The metal thin film 31a is sequentially coated by sputtering. The metal thin film 31a may be formed by screen printing of a solder material made of a metal material, or may be formed by ejecting it from an inkjet nozzle.

  In the groove forming step ST4, a photoresist layer 60 is laminated on the base insulating layer 20 through the metal thin film 31a, a groove 61 to be the circuit pattern 31 is formed in the photoresist layer 60 by photoetching, and a metal is formed at the bottom of the groove 61. In this step, the thin film 31a is exposed. In the groove forming step ST4, as shown in FIG. 8, the exposed portion is cured by being exposed to the surface 20a of each insulating base layer 20, and the unexposed portion is removed by being developed. A resist layer 60 is laminated. In the first embodiment, the photoresist layer 60 is laminated by laminating a dry film, which is a photosensitive material, on the surface 20 a of each insulating base layer 20. In the groove forming step ST4, after laminating the photoresist layer 60, exposure and development (equivalent to photoetching) are performed to form a groove 61 in a portion where the circuit pattern 31 is formed as shown in FIG. The metal thin film 31 a is exposed at the bottom of the groove 61.

  In the metal filling step ST5, the metal thin film 31a is used as an electrode to fill the groove 61 to be the circuit pattern 31 with the metal 31b by plating. In the metal filling step ST5, the metal thin film 31a is used as an electrode in a solution containing a conductive metal, and as shown in FIG. 10, the metal thin film 31a in the groove 61 and the metal thin film 31a on the inner surface of the through hole are electrically conductive. A metal is electrodeposited to fill the metal 31b in the groove 61 and the through hole. The position of the surface of the metal 31b in the groove 61 after the metal filling step ST5 is not uniform.

  In the circuit pattern flattening step ST6, after the metal filling step ST5 and before the photoresist layer removal step ST7, the surface of the metal 31b filled in the groove 61 is formed on the surface of the metal 31b together with the photoresist layer 60 in the cutting tool 41 of the cutting tool 40. This is a step of flattening the surface of the circuit pattern 31 constituted by the metal 31b. In the circuit pattern flattening step ST6, the photoresist layer 60 on one side is sucked and held on the chuck table 42 having the holding surface 42a of the cutting tool 40 as shown in FIG. In the circuit pattern flattening step ST6, the bite wheel 43 is rotated, and the bite wheel 43 is moved downward in the figure by a moving means (not shown), so that the bite tool 41 is moved to the other photoresist layer as shown in FIG. The chuck table and the bite tool are moved relative to the holding surface while being cut into 60, and the surface of the metal 31b filled in the groove 61 together with the photoresist layer 60 on the other side is cut by the bite tool 41. Flatten.

  In the circuit pattern flattening step ST6, after flattening the other photoresist layer 60 side, the other photoresist layer 60 flattened on the chuck table 42 of the cutting tool 40 is sucked and held. The surface of the metal 31b filled in the groove 61 together with the resist layer 60 is cut and flattened. Note that. In the circuit pattern flattening step ST6, similarly to the front and back flattening step ST2, the surface of the photoresist layer 60 and the metal 31b may be cut and flattened using the grinding wheel 51 of the grinding device 50. Thus, in the circuit pattern flattening step ST6, the surface of the metal 31b electrodeposited on the metal thin film 31a is formed flat, and the surface of the circuit pattern 31 composed of the metal thin film 31a and the metal 31b is flattened. .

  The photoresist layer removal step ST7 is a step of removing the photoresist layer 60 leaving the metal thin film 31a from the upper surface of the base insulating layer 20. In the photoresist layer removing step ST7, the photoresist layer 60 is removed from the metal thin film 31a on each insulating base layer 20 as shown in FIG. 13 by dipping in a chemical solution for removing the photoresist layer 60. In the photoresist layer removing step ST7, the photoresist layer 60 may be peeled off from the metal thin film 31a. After the photoresist layer removing step ST7, the metal thin film 31a located between the circuit patterns 31 that are portions where the photoresist layer 60 is laminated is exposed.

  The metal thin film removal step ST8 is a step of removing the exposed metal thin film 31a from the base insulating layer 20 after performing the photoresist layer removal step ST7. The metal thin film removal step ST8 removes the metal thin film 31a exposed between the circuit patterns 31 as shown in FIG. 14 by immersing in a chemical solution for removing the metal thin film 31a.

  In the circuit pattern layer forming step ST9, after performing the metal thin film removing step ST8, the gap between the circuit patterns 31 is filled with an insulating resin member 32 having an insulating property, and the adjacent circuit pattern 31 is insulated. Is a step of forming. In the circuit pattern layer forming step ST <b> 9, the insulating member 32 is filled between the adjacent circuit patterns 31 and the insulating member 32 is covered on the circuit pattern 31. In the first embodiment, in the circuit pattern layer forming step ST9, the ABF is fixed between the circuit patterns 31, the base insulating layer 20, and the circuit pattern 31 by thermocompression bonding or the like. At this time, since the circuit pattern 31 is formed on the base insulating layer 20, the surface of the insulating member 32 is uneven according to the circuit pattern 31.

  The circuit pattern layer flattening step ST10 is a step in which only the surface of the insulating member 32 of the outermost circuit pattern layer 30 is shaved and flattened with the cutting tool 41. In the circuit pattern layer flattening step ST10, the insulating member 32 on one side is sucked and held on the chuck table 42 having the holding surface 42a of the cutting tool 40 as shown in FIG. In the circuit pattern layer flattening step ST10, the bite wheel 43 is rotated, and the bite wheel 43 is moved downward in the figure by a moving means (not shown), so that the bite tool 41 is insulated on the other side as shown in FIG. The surface of the insulating member 32 on the other side is cut and flattened by the cutting tool 41 while the chuck table and the cutting tool are moved relative to each other in parallel with the holding surface.

  In the circuit pattern layer flattening step ST10, after the other insulating member 32 side is flattened, the flattened insulating member 32 is sucked and held on the chuck table 42 of the cutting tool 40, and the one insulating member is sucked and held. The surface of 32 is cut and flattened. Note that. In the circuit pattern layer planarization step ST10, the surface of the insulating member 32 is ground and planarized by using the grinding wheel 51 of the grinding device 50, similarly to the front and back surface planarization step ST2 and the circuit pattern planarization step ST6. good. Thus, the circuit pattern layer planarization step ST10 planarizes the surface of the insulating member 32 to form the circuit pattern layer 30 composed of the circuit pattern 31 and the insulating member 32. After the circuit pattern layer planarization step ST10, the insulating member 32 of the circuit pattern layer 30 covers the entire circuit pattern 31 as shown in FIG. As described above, the manufacturing method completes the formation of the first circuit pattern layer 30 and completes the formation of all the circuit pattern layers 30 (step ST11: Yes). The thin film coating step ST3 to the circuit pattern layer flattening step ST10 are performed.

  Further, in the manufacturing method, when all the circuit pattern layers 30 have not been formed (step ST11: No), the circuit pattern 31 of each circuit pattern layer 30 is connected to each other, so that the insulating member 32 of the circuit pattern layer 30 as a lower layer is connected. Then, by laser ablation, as shown in FIG. 18, a through hole through which the circuit pattern 31 is exposed is formed. Then, the manufacturing method repeats the circuit pattern layer flattening step ST10 from the thin film coating step ST3, thereby filling the through holes with the metal 31b to form the upper circuit pattern 31 and connecting the upper and lower circuit pattern layers 30 to each other. Form.

  As described above, in the manufacturing method according to the first embodiment, even if the substrate 10 serving as the core is warped and the front surface 10a and the back surface 10b of the substrate 10 are not flat, The surface 20a of the base insulating layer 20 laminated on 10b is planarized in the front / back planarization step ST2. In the manufacturing method according to the first embodiment, even if the surface of the insulating member 32 filled in the gap between the circuit patterns 31 is uneven, the surface of the insulating member 32 of the outermost circuit pattern layer 30 is flattened. In the conversion step ST10, flattening is performed. For this reason, the manufacturing method according to the first embodiment has an effect of forming the flat wiring substrate 1 by the front / back planarization step ST2 and the circuit pattern layer planarization step ST10. As a result, the manufacturing method according to the first embodiment has a higher degree of flatness that can better connect the electrode of the electrical component such as the semiconductor chip to be mounted and the wiring pattern of the printed wiring board to be mounted. A high wiring board 1 can be provided.

  In the manufacturing method according to the first embodiment, in the circuit pattern flattening step ST6, the surface of the metal 31b constituting the circuit pattern 31 is also flattened, so that the distance between the circuit pattern layers 30 (that is, the circuit pattern 31 (Height) can be made constant, and the communication speed of electrical components such as a semiconductor chip mounted on the wiring board 1 is also made constant.

  Moreover, the manufacturing method according to the first embodiment can manufacture the flatter wiring substrate 1 by flattening the surface of the metal 31b constituting the circuit pattern 31 in the circuit pattern flattening step ST6. It is possible to provide a wiring board 1 with higher flatness that can be satisfactorily connected to an electrical component such as a semiconductor chip or a printed wiring board.

  In the manufacturing method according to the first embodiment, the circuit pattern 31 constituting the circuit pattern layer 30 is further stacked on the circuit pattern layer 30. That is, in the manufacturing method according to the first embodiment, the circuit pattern layer planarization step ST10 is repeated from the thin film coating step ST3 until all the circuit pattern layers 30 have been formed (step ST11: Yes). In the pattern layer flattening step ST10, the surface of the insulating member 32 constituting the circuit pattern layer 30 is flattened. For this reason, the manufacturing method according to the first embodiment can better ensure the flatness of the surface of the circuit pattern layer 30 located in the outermost layer, and the electrodes of components such as a semiconductor chip to be mounted and the printed wiring to be mounted. It is possible to provide the wiring board 1 with higher flatness, which can be better connected to the wiring pattern of the board.

  The present invention is not limited to the above embodiment. That is, various modifications can be made without departing from the scope of the present invention. In the present invention, in addition to the embodiment in which the circuit pattern 31 is flattened in the circuit pattern flattening step ST6, in the circuit pattern layer flattening step ST10, the circuit pattern 31 may be cut and flattened in addition to the insulating member 32. However, in this case, the bite tool 41 is likely to be worn or chipped by the filler contained in the ABF, so that the surface of the circuit pattern 31 is likely to be rough.

DESCRIPTION OF SYMBOLS 1 Wiring board 10 Board | substrate 10a Front surface 10b Back surface 20 Base insulating layer 20a Surface 30 Circuit pattern layer (rewiring layer)
31 Circuit pattern 31a Metal thin film 31b Metal 32 Insulating member 41 Tool tool 51 Grinding wheel 60 Photoresist layer 61 Groove ST1 Base insulating layer forming step ST2 Front / back flattening step ST3 Thin film coating step ST4 Groove forming step ST5 Metal filling step ST6 Flat circuit pattern Step ST7 Photoresist layer removal step ST8 Metal thin film removal step ST9 Circuit pattern layer formation step ST10 Circuit pattern layer flattening step

Claims (3)

A method of manufacturing a wiring board comprising a rewiring layer on the front and back surfaces,
A base insulating layer forming step of forming a resin base insulating layer on the front and back surfaces of the substrate to be the core;
A front and back flattening step of cutting and flattening the surface of the base insulating layer on the front and back surfaces with a bite tool or a grinding wheel;
A thin film coating step of coating a metal thin film on the surface of the base insulating layer on the flattened front and back surfaces;
A step of forming a photoresist layer on the base insulating layer through the metal thin film, forming a groove to be a circuit pattern in the photoresist layer by photoetching, and exposing the metal thin film at the groove bottom;
Using the metal thin film as an electrode, a metal filling step of filling the groove to be the circuit pattern with a metal by plating,
A photoresist layer removing step of removing the photoresist layer leaving the circuit pattern of the metal from the upper surface of the base insulating layer;
A metal thin film removal step for removing the exposed metal thin film from the base insulating layer after performing the photoresist layer removal step;
After performing the metal thin film removal step, a circuit pattern layer forming step of filling a gap between the circuit patterns with a resin insulating member and forming a circuit pattern layer in which the adjacent circuit patterns are insulated; and
A circuit pattern layer flattening step of scraping and flattening the surface of the insulating member of the circuit pattern layer with a tool.
A method of manufacturing a wiring board, comprising forming a flat wiring board by the front and back planarization step and the circuit pattern layer planarization step.   After the metal filling step and before the photoresist layer removing step, the surface of the metal filled in the groove is shaved with a bite tool together with the photoresist layer to flatten the surface of the metal circuit pattern The method for manufacturing a wiring board according to claim 1, further comprising a pattern flattening step. The method for manufacturing a wiring board according to claim 1, wherein the circuit pattern is further laminated on the circuit pattern layer.

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