JP2006032462A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2006032462A5 JP2006032462A5 JP2004205799A JP2004205799A JP2006032462A5 JP 2006032462 A5 JP2006032462 A5 JP 2006032462A5 JP 2004205799 A JP2004205799 A JP 2004205799A JP 2004205799 A JP2004205799 A JP 2004205799A JP 2006032462 A5 JP2006032462 A5 JP 2006032462A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- forming
- wiring
- protective metal
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Claims (10)
前記樹脂層上に保護金属層を形成する工程と、
前記保護金属層及び前記樹脂層に溝を形成する工程と、
前記溝を埋め込む導電層を前記溝内及び前記保護金属層上に形成する工程と、
前記保護金属層を研磨防御層として利用して、前記導電層を機械研磨することにより、前記導電層を前記溝内に埋め込んで配線層を得る工程と、
前記樹脂層上の前記保護金属層を除去する工程とを有することを特徴とする配線形成方法。 Forming a resin layer on the substrate;
Forming a protective metal layer on the resin layer;
Forming grooves in the protective metal layer and the resin layer;
Forming a conductive layer filling the groove in the groove and on the protective metal layer;
Using the protective metal layer as a polishing protective layer, mechanically polishing the conductive layer, thereby embedding the conductive layer in the groove to obtain a wiring layer;
And a step of removing the protective metal layer on the resin layer.
前記配線層の上に立設し、かつ上面側に保護金属層が設けられたビアポストを形成する工程と、
前記ビアポストの段差を埋め込むと共に、前記ビアポストを被覆する樹脂層を形成する工程と、
前記保護金属層を研磨防御層として利用して、前記樹脂層を機械研磨することにより、前記ビアポスト上の前記保護金属層を露出させる工程とを有することを特徴とする配線形成方法。 Forming a wiring layer on the substrate;
Forming a via post erected on the wiring layer and provided with a protective metal layer on the upper surface side;
A step of embedding the step of the via post and forming a resin layer covering the via post; and
And a step of exposing the protective metal layer on the via post by mechanically polishing the resin layer using the protective metal layer as a polishing protective layer.
前記配線層を被覆するシード層を形成する工程と、
前記配線層の所要部上に開口部が設けられたレジスト膜を前記シード層上に形成する工程と、
前記シード層をめっき給電層に利用する電解めっきにより、前記レジスト膜の開口部に導電体を形成する工程と、
前記導電体上に前記保護金属層を選択的に形成する工程と、
前記レジスト膜を除去する工程と、
前記導電体及び前記保護金属層をマスクにして、前記シード層をエッチングする工程とを含むことを特徴とする請求項2に記載の配線形成方法。 The step of forming the via post includes
Forming a seed layer covering the wiring layer;
Forming a resist film having an opening on a required portion of the wiring layer on the seed layer;
Forming a conductor in the opening of the resist film by electroplating using the seed layer as a plating power supply layer;
Selectively forming the protective metal layer on the conductor;
Removing the resist film;
The method for forming a wiring according to claim 2, further comprising: etching the seed layer using the conductor and the protective metal layer as a mask.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004205799A JP4515177B2 (en) | 2004-07-13 | 2004-07-13 | Wiring formation method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004205799A JP4515177B2 (en) | 2004-07-13 | 2004-07-13 | Wiring formation method |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2006032462A JP2006032462A (en) | 2006-02-02 |
JP2006032462A5 true JP2006032462A5 (en) | 2007-07-05 |
JP4515177B2 JP4515177B2 (en) | 2010-07-28 |
Family
ID=35898474
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004205799A Expired - Fee Related JP4515177B2 (en) | 2004-07-13 | 2004-07-13 | Wiring formation method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4515177B2 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5154963B2 (en) * | 2008-02-04 | 2013-02-27 | 新光電気工業株式会社 | Wiring board manufacturing method |
JP5411829B2 (en) * | 2009-10-30 | 2014-02-12 | パナソニック株式会社 | Multilayer circuit board manufacturing method and multilayer circuit board manufactured by the manufacturing method |
TWI412308B (en) * | 2009-11-06 | 2013-10-11 | Via Tech Inc | Circuit substrate and fabricating process thereof |
JP5680589B2 (en) * | 2012-06-25 | 2015-03-04 | 新光電気工業株式会社 | Wiring board |
JP6932475B2 (en) * | 2015-03-26 | 2021-09-08 | 住友ベークライト株式会社 | Manufacturing method of organic resin substrate, organic resin substrate and semiconductor device |
JP6779088B2 (en) * | 2016-10-05 | 2020-11-04 | 株式会社ディスコ | Wiring board manufacturing method |
JP6779087B2 (en) * | 2016-10-05 | 2020-11-04 | 株式会社ディスコ | Wiring board manufacturing method |
JP6783614B2 (en) * | 2016-10-11 | 2020-11-11 | 株式会社ディスコ | Wiring board manufacturing method |
JP2019204974A (en) * | 2019-08-21 | 2019-11-28 | 住友ベークライト株式会社 | Method of manufacturing organic resin substrate, organic resin substrate, and semiconductor device |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2777020B2 (en) * | 1992-07-29 | 1998-07-16 | 沖電気工業株式会社 | Wiring layer flattening method |
JP3361556B2 (en) * | 1992-09-25 | 2003-01-07 | 日本メクトロン株式会社 | Method of forming circuit wiring pattern |
JPH06112199A (en) * | 1992-09-30 | 1994-04-22 | Hitachi Ltd | Manufacture of wiring board |
JPH06260772A (en) * | 1993-03-03 | 1994-09-16 | Hitachi Ltd | Lessening method of mechanical polish flaw |
JPH1098268A (en) * | 1996-09-24 | 1998-04-14 | Oki Electric Ind Co Ltd | Method for plating columnar conductor and multi-layered printed wiring board obtained by it |
JPH11238970A (en) * | 1998-02-19 | 1999-08-31 | Mitsubishi Electric Corp | Multilayered printed board and manufacture thereof |
JPH11298141A (en) * | 1998-04-08 | 1999-10-29 | Hitachi Ltd | Manufacture for electronic device |
JP4057146B2 (en) * | 1998-06-05 | 2008-03-05 | 沖電気工業株式会社 | Manufacturing method of electronic component integrated multilayer substrate |
JP3137186B2 (en) * | 1999-02-05 | 2001-02-19 | インターナショナル・ビジネス・マシーンズ・コーポレ−ション | Interlayer connection structure, multilayer wiring board, and method for forming them |
JP3760857B2 (en) * | 2001-12-17 | 2006-03-29 | 松下電器産業株式会社 | Method for manufacturing printed wiring board |
-
2004
- 2004-07-13 JP JP2004205799A patent/JP4515177B2/en not_active Expired - Fee Related
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI324033B (en) | Method for fabricating a flip-chip substrate | |
CN103943600B (en) | Novel termination between chip and substrate and connection | |
TW582192B (en) | Multilayer printed wiring board and method for producing multilayer printed wiring board | |
CN106328604B (en) | Chip package | |
TWI296843B (en) | A method for manufacturing a coreless package substrate | |
US9888569B2 (en) | Printed circuit board having buried circuit pattern and method for manufacturing the same | |
CN104134643B (en) | Substrate with ultra-fine spacing flipchip-bumped | |
TW200810630A (en) | Circuit wiring board incorporating heat resistant substrate | |
JP2012069761A (en) | Semiconductor element, semiconductor element mounting body, and manufacturing method of semiconductor element | |
CN107004612A (en) | The integrated device including photosensitive filler is encapsulated between substrate and tube core | |
TW201247053A (en) | Printed circuit board and method for manufacturing the same | |
JP2006032462A5 (en) | ||
TWI294760B (en) | ||
WO2011111308A1 (en) | Process for production of semiconductor device, and semiconductor device | |
KR101167464B1 (en) | A method of manufacturing printed circuit board | |
JP3855320B2 (en) | Semiconductor device substrate manufacturing method and semiconductor device manufacturing method | |
JP4515177B2 (en) | Wiring formation method | |
JP2007165776A (en) | Manufacturing method for mounting substrate | |
CN104091790A (en) | Semiconductor packaging substrate structure and manufacturing method of semiconductor packaging substrate structure | |
TW201023278A (en) | Method for forming metallic bump on semiconductor component and sealing semiconductor component | |
WO2018182658A1 (en) | A die interconnect substrate, an electrical device, and a method for forming a die interconnect substrate | |
TWI277191B (en) | Method for manufacturing leadless package substrate | |
TWI230427B (en) | Semiconductor device with electrical connection structure and method for fabricating the same | |
TWI299898B (en) | ||
JP5154963B2 (en) | Wiring board manufacturing method |