JP2006032462A5 - - Google Patents

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Publication number
JP2006032462A5
JP2006032462A5 JP2004205799A JP2004205799A JP2006032462A5 JP 2006032462 A5 JP2006032462 A5 JP 2006032462A5 JP 2004205799 A JP2004205799 A JP 2004205799A JP 2004205799 A JP2004205799 A JP 2004205799A JP 2006032462 A5 JP2006032462 A5 JP 2006032462A5
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JP
Japan
Prior art keywords
layer
forming
wiring
protective metal
metal layer
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JP2004205799A
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Japanese (ja)
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JP2006032462A (en
JP4515177B2 (en
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Priority to JP2004205799A priority Critical patent/JP4515177B2/en
Priority claimed from JP2004205799A external-priority patent/JP4515177B2/en
Publication of JP2006032462A publication Critical patent/JP2006032462A/en
Publication of JP2006032462A5 publication Critical patent/JP2006032462A5/ja
Application granted granted Critical
Publication of JP4515177B2 publication Critical patent/JP4515177B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Claims (10)

基板の上に樹脂層を形成する工程と、
前記樹脂層上に保護金属層を形成する工程と、
前記保護金属層及び前記樹脂層に溝を形成する工程と、
前記溝を埋め込む導電層を前記溝内及び前記保護金属層上に形成する工程と、
前記保護金属層を研磨防御層として利用して、前記導電層を機械研磨することにより、前記導電層を前記溝内に埋め込んで配線層を得る工程と、
前記樹脂層上の前記保護金属層を除去する工程とを有することを特徴とする配線形成方法。
Forming a resin layer on the substrate;
Forming a protective metal layer on the resin layer;
Forming grooves in the protective metal layer and the resin layer;
Forming a conductive layer filling the groove in the groove and on the protective metal layer;
Using the protective metal layer as a polishing protective layer, mechanically polishing the conductive layer, thereby embedding the conductive layer in the groove to obtain a wiring layer;
And a step of removing the protective metal layer on the resin layer.
基板の上に配線層を形成する工程と、
前記配線層の上に立設し、かつ上面側に保護金属層が設けられたビアポストを形成する工程と、
前記ビアポストの段差を埋め込むと共に、前記ビアポストを被覆する樹脂層を形成する工程と、
前記保護金属層を研磨防御層として利用して、前記樹脂層を機械研磨することにより、前記ビアポスト上の前記保護金属層を露出させる工程とを有することを特徴とする配線形成方法。
Forming a wiring layer on the substrate;
Forming a via post erected on the wiring layer and provided with a protective metal layer on the upper surface side;
A step of embedding the step of the via post and forming a resin layer covering the via post; and
And a step of exposing the protective metal layer on the via post by mechanically polishing the resin layer using the protective metal layer as a polishing protective layer.
前記ビアポストを形成する工程は、
前記配線層を被覆するシード層を形成する工程と、
前記配線層の所要部上に開口部が設けられたレジスト膜を前記シード層上に形成する工程と、
前記シード層をめっき給電層に利用する電解めっきにより、前記レジスト膜の開口部に導電体を形成する工程と、
前記導電体上に前記保護金属層を選択的に形成する工程と、
前記レジスト膜を除去する工程と、
前記導電体及び前記保護金属層をマスクにして、前記シード層をエッチングする工程とを含むことを特徴とする請求項2に記載の配線形成方法。
The step of forming the via post includes
Forming a seed layer covering the wiring layer;
Forming a resist film having an opening on a required portion of the wiring layer on the seed layer;
Forming a conductor in the opening of the resist film by electroplating using the seed layer as a plating power supply layer;
Selectively forming the protective metal layer on the conductor;
Removing the resist film;
The method for forming a wiring according to claim 2, further comprising: etching the seed layer using the conductor and the protective metal layer as a mask.
前記ビアポスト上の前記保護金属層を露出させる工程の後に、前記保護金属層を除去する工程をさらに有することを特徴とする請求項2又は3に記載の配線形成方法。   4. The wiring forming method according to claim 2, further comprising a step of removing the protective metal layer after the step of exposing the protective metal layer on the via post. 前記保護金属層として、前記導電層より高い硬度の金属が使用されることを特徴とする請求項1に記載の配線形成方法。   The wiring forming method according to claim 1, wherein a metal having a higher hardness than that of the conductive layer is used as the protective metal layer. 前記保護金属層は、コバルト(Co)、ニッケル(Ni)、チタンタングステン(TiW)、チタン(Ti)及びタングステン(W)のいずれかよりなることを特徴とする請求項5に記載の配線形成方法。   6. The wiring forming method according to claim 5, wherein the protective metal layer is made of any one of cobalt (Co), nickel (Ni), titanium tungsten (TiW), titanium (Ti), and tungsten (W). . 前記機械研磨は、バフ研磨、テープ研磨及びグラインダーによる研磨のいずれかであることを特徴とする請求項1乃至3のいずれか一項に記載の配線形成方法。   The wiring forming method according to claim 1, wherein the mechanical polishing is any one of buff polishing, tape polishing, and polishing by a grinder. 前記導電層は銅層であって、前記樹脂層はエポキシ樹脂又はポリイミド樹脂であることを特徴とする請求項1に記載の配線形成方法。   The wiring forming method according to claim 1, wherein the conductive layer is a copper layer, and the resin layer is an epoxy resin or a polyimide resin. 前記ビアポストは銅よりなり、前記樹脂層はエポキシ樹脂又はポリイミド樹脂であることを特徴とする請求項2乃至4のいずれか一項に記載の配線形成方法。   The wiring formation method according to claim 2, wherein the via post is made of copper, and the resin layer is an epoxy resin or a polyimide resin. 前記樹脂層はソルダレジスト膜であり、前記ビアポストの上面に電子部品が電気的に接続されることを特徴とする請求項2乃至4のいずれか一項に記載の配線形成方法。   The wiring forming method according to claim 2, wherein the resin layer is a solder resist film, and an electronic component is electrically connected to an upper surface of the via post.
JP2004205799A 2004-07-13 2004-07-13 Wiring formation method Expired - Fee Related JP4515177B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004205799A JP4515177B2 (en) 2004-07-13 2004-07-13 Wiring formation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004205799A JP4515177B2 (en) 2004-07-13 2004-07-13 Wiring formation method

Publications (3)

Publication Number Publication Date
JP2006032462A JP2006032462A (en) 2006-02-02
JP2006032462A5 true JP2006032462A5 (en) 2007-07-05
JP4515177B2 JP4515177B2 (en) 2010-07-28

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JP2004205799A Expired - Fee Related JP4515177B2 (en) 2004-07-13 2004-07-13 Wiring formation method

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JP (1) JP4515177B2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5154963B2 (en) * 2008-02-04 2013-02-27 新光電気工業株式会社 Wiring board manufacturing method
JP5411829B2 (en) * 2009-10-30 2014-02-12 パナソニック株式会社 Multilayer circuit board manufacturing method and multilayer circuit board manufactured by the manufacturing method
TWI412308B (en) * 2009-11-06 2013-10-11 Via Tech Inc Circuit substrate and fabricating process thereof
JP5680589B2 (en) * 2012-06-25 2015-03-04 新光電気工業株式会社 Wiring board
JP6932475B2 (en) * 2015-03-26 2021-09-08 住友ベークライト株式会社 Manufacturing method of organic resin substrate, organic resin substrate and semiconductor device
JP6779088B2 (en) * 2016-10-05 2020-11-04 株式会社ディスコ Wiring board manufacturing method
JP6779087B2 (en) * 2016-10-05 2020-11-04 株式会社ディスコ Wiring board manufacturing method
JP6783614B2 (en) * 2016-10-11 2020-11-11 株式会社ディスコ Wiring board manufacturing method
JP2019204974A (en) * 2019-08-21 2019-11-28 住友ベークライト株式会社 Method of manufacturing organic resin substrate, organic resin substrate, and semiconductor device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2777020B2 (en) * 1992-07-29 1998-07-16 沖電気工業株式会社 Wiring layer flattening method
JP3361556B2 (en) * 1992-09-25 2003-01-07 日本メクトロン株式会社 Method of forming circuit wiring pattern
JPH06112199A (en) * 1992-09-30 1994-04-22 Hitachi Ltd Manufacture of wiring board
JPH06260772A (en) * 1993-03-03 1994-09-16 Hitachi Ltd Lessening method of mechanical polish flaw
JPH1098268A (en) * 1996-09-24 1998-04-14 Oki Electric Ind Co Ltd Method for plating columnar conductor and multi-layered printed wiring board obtained by it
JPH11238970A (en) * 1998-02-19 1999-08-31 Mitsubishi Electric Corp Multilayered printed board and manufacture thereof
JPH11298141A (en) * 1998-04-08 1999-10-29 Hitachi Ltd Manufacture for electronic device
JP4057146B2 (en) * 1998-06-05 2008-03-05 沖電気工業株式会社 Manufacturing method of electronic component integrated multilayer substrate
JP3137186B2 (en) * 1999-02-05 2001-02-19 インターナショナル・ビジネス・マシーンズ・コーポレ−ション Interlayer connection structure, multilayer wiring board, and method for forming them
JP3760857B2 (en) * 2001-12-17 2006-03-29 松下電器産業株式会社 Method for manufacturing printed wiring board

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