JPH11251752A - Multilayered printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayered printed wiring board in which the reliability of connection of solder bump is excellent. SOLUTION: The opening 62 of an interlayer resin insulation layer 60 on the outermost layer is filled with plating and a via hole 70 is formed, and the surface of the via hole 70 is formed high the same as a conductor circuit 72 in which a solder bump is formed. Therefore, the same quantity of solder paste is printed on the via hole 70 and conductor circuit 72 so as to make a solder bump 88U to be formed in the via hole 70 to be high the same as a solder bump 88U to be formed in the conductor circuit 72. Thus, the reliability of connection between the solder pad of an IC chip and solder bump 88U of the multilayered printed wiring board 10 can be improved at the time of mounting the IC chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board having solder bumps on its surface.

[0002]

2. Description of the Related Art On a surface of a printed wiring board such as a package board, a spherical projection of solder called a solder bump is provided for electrically connecting to an electronic component such as an IC chip to be mounted. . The solder bump may be formed directly on the via hole for the purpose of increasing the degree of integration, in addition to being formed on the conductor circuit on the substrate surface. A technique for forming a solder bump in this via hole is disclosed in Japanese Patent Application Laid-Open No. 8-335.
No. 781.

The formation of solder bumps on a printed wiring board will be described with reference to FIG. FIG. 10 (A)
Shows a cross section of a multilayer printed wiring board 310 according to the related art. The multilayer printed wiring board includes a core substrate 130.
A plurality of interlayer resin insulation layers 140 and 160
Are formed to form conductor circuits 134, 152, and 172. An opening 162 for a via hole is formed in the outermost interlayer resin insulating layer 160, and a via hole 170 made of copper plating is formed in the opening 162. The via hole 170 connects to the conductor circuit 152 under the interlayer resin insulation layer 160. In the outermost interlayer resin insulating layer 160, a plating resist 180 having an opening 181 having a predetermined diameter is formed.

When forming solder bumps on the multilayer printed wiring board 310, a metal mask 198 is placed on the multilayer printed wiring board 310 as shown in FIG. Each opening 181, 18
1, 181 is printed with a solder paste. Here, the metal mask 198 has openings 18 of the plating resist 180.
Openings 198a, 198b are formed corresponding to the respective positions of No. 1. Here, the opening 198b corresponding to the via hole 170 is formed to have a relatively large diameter.
The opening 198a corresponding to the conductor circuit 172 has a relatively small diameter. Thereby, the via hole 17
More solder paste can be printed on the 0 side.

After the solder paste is printed, the solder paste is reflowed by passing the multilayer printed wiring board 310 through a heating furnace to complete the solder bumps 188 as shown in FIG. Thereafter, the flux that has flowed out of the solder during reflow is washed. And FIG.
As shown in (D), the IC chip 190 is mounted on the multilayer printed wiring board 310 and the solder pads 192 of the IC chip 190 are provided.
Are placed so as to correspond to the solder bumps 188 on the multilayer printed wiring board 310 side, and the solder pads 188 are melted by passing through a heating furnace.
An electrical connection with the C chip 190 is established. Thereafter, the flux that has flowed out of the solder during reflow is washed.

[0006]

However, in the above-mentioned multilayer printed wiring board, the connection with the IC chip may not be properly established. That is, as shown in FIG. 10C, the height h1 of the solder bump 188 formed on the concave via hole 170 and the flat conductor circuit 172
Since it is difficult to make the height h2 of the solder bumps 188 formed thereon the same, as shown in FIG. 10D, one of the solder pads 188 on the side of the multilayer printed wiring board 310 is connected to the IC chip 190. In some cases, connection with the solder pad 192 on the side cannot be performed properly.

As described above with reference to FIG. 10B, the metal mask has openings 198a and 198 having different diameters.
Since it is necessary to perforate b in correspondence with each position of the opening 181 of the plating resist 180, the adjustment is difficult. Further, after reflowing the solder to form the solder bumps as described above, and after performing the connection between the solder bumps and the solder pads of the IC chip by reflow,
It is necessary to clean the flux from the solder. However, since the via holes 170 are filled with solder, the amount of solder increases and the amount of flux that seeps out increases, making it difficult to completely clean. For this reason, the flux may remain even after cleaning, which may cause a short circuit of the wiring. Furthermore, during the reflow, the multilayer printed wiring board 310 may be warped, and the mounting reliability with the IC chip 90 may be reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a multilayer printed wiring board having excellent solder bump connection reliability.

[0009]

According to the present invention, there is provided a multilayer printed wiring board comprising an interlayer resin insulation layer and a conductor circuit alternately laminated on an outermost interlayer resin insulation layer. And a solder bump formed on a via hole formed by filling a metal in an opening formed in the outermost interlayer resin insulating layer, and a solder bump formed on the arranged conductor circuit. This is a technical feature.

In the present invention, the height of the surface of the via hole is reduced by filling the opening with metal (plating).
The height is set equal to the height of the conductor circuit on which the solder bumps are formed. Therefore, by printing the same amount of solder paste on the via hole and the conductor circuit, the height of the solder bump formed on the via hole and the height of the solder bump formed on the conductor circuit can be made equal. Therefore, the connection reliability of the solder bumps can be improved.

According to the present invention, there is provided a multilayer printed wiring board comprising an interlayer resin insulating layer and a conductive circuit alternately stacked, wherein metal is filled in an opening formed in the interlayer resin insulating layer. A multilayer printed wiring board characterized in that a solder bump is formed on a via hole formed as described above.

In the present invention, the openings are filled with metal so that the heights of the surfaces of the via holes are all equal. Therefore, by printing the solder paste, the heights of the solder bumps formed in the via holes can all be made equal. Therefore, the connection reliability of the solder bumps can be improved.

In a preferred aspect of the present invention, since the recess is formed at the center of the via hole, the via hole and the solder bump can be firmly connected, and the connection reliability of the solder bump can be improved. Such a depression is desirably in the thickness range of the conductor circuit (that is, the range in which the depression does not reach the opening), and specifically, 0.5 to 30.
μm.

In a preferred aspect of the present invention, since the side surface of the opening of the interlayer resin insulating layer is roughened, the adhesion to the via hole formed in the opening can be improved.

In a preferred aspect of the present invention, since the surfaces of the via hole and the conductor circuit are roughened, the adhesion between the via hole and the solder bump formed on the conductor circuit is improved. be able to.

In a preferred aspect of the present invention, since a solder bump is formed via a noble metal on the surface of the via hole filled with plating, the surface of the via hole made of copper or the like and the solder bump are interposed. , No oxide film is formed,
The adhesion between the via hole and the solder bump can be improved.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a multilayer printed wiring board according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 7 shows a cross section of the multilayer printed wiring board, and FIG.
This shows a state where the chip 90 is attached and mounted on the motherboard 95 side. The multilayer printed wiring board 10 shown in FIG. 6 (U) is provided with solder bumps 88U for connection to the bumps 92 of the IC chip 90 on the upper surface and solder for connection to the bumps 96 of the motherboard 95 on the lower surface. The bumps 88D are provided, and are configured as a package substrate that serves to transfer signals and the like between the IC chip 90 and the motherboard 95.

As shown in FIG. 7, the multilayer printed wiring board 10
The upper surface side upper layer and the lower surface side upper layer (here,
The upper layer is the upper side of the upper surface with the substrate 30 as the center,
On the lower surface of the substrate, which means the lower side, inner-layer copper patterns 34 serving as ground layers are formed.
On the upper layer of the inner layer copper pattern 34, a conductor circuit 52 for forming a signal line with a lower interlayer resin insulation layer 40 interposed therebetween,
Further, a lower via hole 50 is formed penetrating through the interlayer resin insulating layer 40. In the upper layer of the lower via hole 50 and the conductor circuit 52, copper plating is applied to the outermost conductor circuit 72 and the opening 62 formed in the outermost interlayer resin insulation layer 60 via the outermost interlayer resin insulation layer 60. The filled upper via hole 70 is formed.

On the upper surface side of the conductor circuit 72 and the upper via hole 70, a solder pad 8 supporting a solder bump 88U is provided.
6U are formed. Here, the solder pad 86U on the IC chip side is formed to have a diameter of 133 μm. On the other hand, a solder pad 86 supporting a solder bump 88D is provided in the conductor circuit 72 on the lower surface side and the upper via hole (not shown).
D is formed. Here, the solder pad 86D on the motherboard side is formed to have a diameter of 600 μm. The solder bumps 88 </ b> U and 88 </ b> D are formed in openings (pad portions) 81 of the solder resist 80.

In the multilayer printed wiring board of the first embodiment, plating is filled in the opening 62 of the outermost interlayer resin insulation layer 60 to form the via hole 70. For this reason, the via hole 70 differs from the concave via hole 170 of the multilayer printed wiring board according to the prior art described above with reference to FIG. It is equal to the height. Therefore, by printing the same amount of solder paste on the via hole 70 and the conductor circuit 72 as described later, the solder bump 88U formed in the via hole 70 and the conductor circuit 7
2 can be made equal in height to the solder bump 88U. For this reason, as shown in FIG.
When placing the C chip 90, the solder pads 92 of the IC chip and the solder bumps 88U of the multilayer printed wiring board 10
Connection reliability can be improved.

Further, a depth of 1 is provided at the center of the via hole 70.
Since the recess 70a of 0 μm is formed, the connection reliability between the via hole 70 and the solder bump 88U can be improved. In particular, since the roughening layer 78 is provided perpendicularly to the curved surface of the recess 70a, the roughening layer 78 is protected from the stress applied between the via hole 70 and the solder bump 88 due to the temperature rise of the IC chip 90. The connection can be made firmly, and the connection reliability between the via hole 70 and the solder bump 88U can be improved. Here, the depth of the recess 70a does not reach the opening 62 formed in the upper interlayer resin insulation layer 60, and is within the thickness range of the conductor circuit. Therefore, it is in the range of 0.5 to 15 μm. On the other hand, the opening 62 of the outermost interlayer resin insulation layer 60 is formed.
Since the side surface 62a is roughened as shown in the figure, the adhesion to the via hole 70 formed in the opening 62 can be improved.

Due to the difference in the coefficient of thermal expansion between the via hole 70 made of copper and the outermost interlayer resin insulating layer 60 made of the resin in which the via hole 70 is formed, a large stress is applied during thermal contraction. Is added. For this reason, in the multilayer printed wiring board 10, the outermost interlayer resin insulation layer 60
By using a composite of a thermoplastic resin and a thermosetting resin having high toughness, generation of cracks due to the stress is prevented. Here, a composite of a thermoplastic resin and a thermosetting resin is used. Alternatively, the outermost interlayer resin insulation layer 60 may be formed mainly by using a thermoplastic resin such as a fluororesin having high toughness. It is possible.

Further, since the surface of the conductor circuit 72 is roughened and the roughened layer 78 is formed, the adhesion between the conductor circuit 72 and the solder bump 88U formed on the conductor circuit 72 can be improved. Further, on the surfaces of via holes 70 filled with copper plating and conductive circuits 72 formed of copper plating,
Nickel plating layer 82 and gold plating layer (noble metal layer) 84
Is formed, and the solder bump 88U is formed via the gold plating layer 84.
Is formed, the via hole 7 made of copper or the like is formed.
0, no oxide film is formed between the surface of the conductor circuit 72 and the solder bump 88U, and the adhesion between the via hole and the conductor circuit and the solder bump can be improved. Further, the solder resist 80 includes the via hole 70 and the conductor circuit 72.
, Except for the portion where the solder pad 86U is formed, the solder resist 80 protects the via hole 70 and the conductor circuit 72, and increases the strength of the entire substrate. In the above description, the solder bump 88U on the upper surface side of the multilayer printed wiring board 10 has been described, but the solder bump 88D on the lower side is similarly formed.

Next, a manufacturing process of the package substrate shown in FIG. 7 will be described with reference to FIGS. (1) 1 mm thick BT (bismaleimide triazine)
A starting material is a copper-clad laminate 30A in which 18 μm copper foils 32 are laminated on both sides of a core substrate 30 made of resin or glass epoxy resin (see FIG. 1A). First, an inner layer copper pattern (conductor circuit) 34 is formed on both surfaces of the substrate 30 by etching the copper-clad laminate 30A into a pattern (see FIG. 1B).

Further, after the substrate 30 on which the inner layer copper pattern 34 is formed is washed with water and dried, copper sulfate 8 g / l, nickel sulfate 0.6 g / l, citric acid 15 g / l, sodium hypophosphite 29 g / l l, boric acid 31 g / l, surfactant 0.1 g / l, immersed in an electroless plating solution having a pH of 9 and the surface of the inner layer copper pattern 34 was made of copper-nickel-phosphorus having a thickness of 3 μm. Formation of the oxide layer 38 (FIG. 1)
(C)). The substrate 30 is washed with water, and 0.1 mol
/ L tin borofluoride-1.0 mol / l immersion in an electroless tin displacement plating bath consisting of a thiourea solution at 50 ° C for 1 hour,
A 0.3 μm tin layer (not shown) is provided on the surface of the roughened layer.

(2) Here, an adhesive for electroless plating for forming an interlayer resin insulating layer is prepared. Here, cresol novolak type epoxy resin (Nippon Kayaku:
35 parts by weight (solid content: 80%) of a 25% acrylate having a molecular weight of 2500), 4 parts by weight of a photosensitive monomer (trade name: Aronix M315, manufactured by Toagosei Co., Ltd.), 0.5 parts by weight of an antifoaming agent (S-65, manufactured by San Nopco) And 3.6 parts by weight of NMP. Polyether sulfone (PE) as thermoplastic resin
S) 8 parts by weight, an average particle diameter of epoxy resin particles (manufactured by Sanyo Kasei Co., Ltd., polymer pole) as a thermosetting resin.
After mixing 7.245 parts by weight of a 5 μm one, 20 parts by weight of NMP is further added and stirred and mixed. Imidazole curing agent (Shikoku Chemicals: trade name 2E4MZ
-CN) 2 parts by weight, photoinitiator (Irgacure-907 manufactured by Ciba Geigy) 2 parts by weight, photosensitizer (Nippon Kayaku:
0.2 parts by weight of DETX-S) and 1.5 parts by weight of NMP are stirred and mixed. Are mixed and stirred to obtain an adhesive for electroless plating.

(3) The adhesive for electroless plating of (1) is applied to the substrate 30 of (2) with a roll coater, left in a horizontal state for 20 minutes, and then dried at 60 ° C. for 30 minutes (prebaked). ) To form an interlayer resin insulation layer 40 (FIG. 1).
(D)).

Substrate 3 on which lower interlayer resin insulation layer 40 is formed
A photomask film on which black circles of a predetermined diameter are printed is adhered to both sides of the photomask, and 500 mJ / c by an ultra-high pressure mercury lamp.
Exposure at m ² . This was spray-developed with a DMDG solution, and the substrate was 3,000 m long using an ultra-high pressure mercury lamp.
Exposure at J / cm ² , 1 hour at 100 ° C., then 150
By performing a heat treatment (post-baking) at 5 ° C. for 5 hours, a thickness of 20 μm having a 60 μmφ opening (via hole forming opening 42: bottom 61 μm, top 67 μm) having excellent dimensional accuracy equivalent to a photomask film Is formed (see FIG. 2E).

(4) Substrate 30 with Opening 42 Formed
Is immersed in chromic acid for 2 minutes to dissolve and remove the epoxy resin particles on the surface of the interlayer resin insulating layer 40, thereby forming a roughened surface having a depth of 4 μm on the surface of the interlayer resin insulating layer 40. This roughened surface is similarly formed on the side surface 42a inside the opening 42 (see FIG. 2F). Then, it is immersed in a neutralizing solution (manufactured by Shipley) and then washed with water. Further, by applying a palladium catalyst (manufactured by Atotech) to the surface of the surface-roughened substrate, a catalyst nucleus is attached to the surface of the interlayer resin insulating layer 40 and the inner wall surface of the via hole opening 42.

(5) The substrate is immersed in an electroless copper plating bath having the following composition to form an electroless copper plating film 44 having a thickness of 0.6 μm on the entire rough surface (see FIG. 2 (G)). . [Electroless plating solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l

(6) A commercially available photosensitive dry film is stuck on the electroless copper plating film 44 formed in (5) above,
Place a mask and expose at 100 mJ / cm ² , 0.8
% Sodium carbonate, with a thickness of 15 μm, L /
A plating resist 46 of S = 25/25 μm is provided (see FIG. 2H).

(7) Next, electrolytic copper plating is applied to the non-resist-forming portion under the following conditions to deposit an electrolytic copper plating film 48 having a thickness of 20 μm, and the opening 42 is filled with the plating film (FIG. 3). (I)). Liquid condition: Copper sulfate pentahydrate 60 g / l Sulfuric acid 190 g / l Chloride ion 40 ppm Leveling agent (HL manufactured by Atotech) 40 ml / l Brightener (UV manufactured by Atotech) 0.5 ml / l Operating condition: Bubbling 3.00 l / Min Current density 0.5 A / dm ² Set current value 0.18 A Plating time 100 minutes In this embodiment, filling is performed by plating. However, instead of plating, conductive paste can be filled. Examples of the conductive paste include DD paste (AE16001) manufactured by Tatta Electric Wire.

(8) After stripping and removing the plating resist 46 with 5% KOH, the electroless plating film 44 under the plating resist 46 is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide. A conductor circuit 52 and a via hole 50 each having a thickness of about 15 μm and including a plating film 44 and an electrolytic copper plating film 48 are formed (see FIG. 3 (J)).

(9) Subsequently, the conductor circuit 52 of the substrate 30
Then, a roughened layer 58 is formed in the via hole 50 in the same manner as in the above (2) (see FIG. 3K).

(10) By repeating the above steps (2) to (8), a conductor circuit in a further upper layer is formed. That is, an adhesive for electroless plating is applied to both surfaces of the substrate 30, dried in a state of being left in a horizontal state, and then a photomask film is brought into close contact, exposed and developed, and the opening 62 for forming a via hole is formed. Then, an interlayer resin insulating layer 60 having a thickness of 20 μm is formed (see FIG. 3L). Next, after roughening the surface of the interlayer resin insulating layer 60 and the side surface 62a of the opening 62, an electroless copper plating film 64 is formed on the surface of the substrate 30 subjected to the roughening treatment. (M)). Subsequently, a plating resist 66 is formed on the electroless copper plating film 64.
Is provided, the electrolytic copper plating film 68
Is formed (see FIG. 4 (N)). Then, after the plating resist 66 is peeled off, the electroless plating film 64 under the plating resist 66 is dissolved and removed, and the upper via hole 70 is removed.
Then, a conductor circuit 72 is formed (see FIG. 4 (O)). In the manufacturing method according to the present embodiment, electrolytic plating is performed so that a depression 70 a is formed in the center of the electrolytic copper plating 68 at a position where the via hole 70 is formed. Further, the upper via hole 7
The roughened layer 78 is formed on the surface of the conductive circuit 72 and the conductor circuit 72 to complete the package substrate (see FIG. 5 (P)). Here, the roughened layer 78 is formed perpendicular to the curved surface of the central recess 70 a of the via hole 70.

In this embodiment, the ratio between the diameter of the via hole (opening diameter of the opening 62: 67 μm) and the thickness (20 μm) of the outermost interlayer resin insulating layer 60 is set to 3.35. is there. Here, if the ratio between the diameter of the via hole and the thickness of the interlayer resin insulating layer is 1 or less, the plating solution is too deep with respect to the diameter of the opening 62 in the plating step, and the plating solution is And the plating cannot be performed efficiently. On the other hand, when the ratio of the diameter of the via hole to the thickness of the interlayer resin insulating layer exceeds 4, the opening diameter of the opening for forming the via hole is too large with respect to the depth, so that a depression is formed in the center of the via hole. Can not do. Therefore, the ratio of the diameter of the via hole to the thickness of the interlayer resin insulating layer is preferably more than 1 and 4 or less.

The thickness of the conductive circuit 72 is preferably 20 μm or less, and more preferably 40 μm or less. This is because the thickness of the conductive circuit is determined by the thickness of the plating resist 66 described above. If the thickness of the optically formed plating resist exceeds 40 μm, the resolution is reduced and a desired shape is formed. Because it is difficult.

(11) Subsequently, solder bumps are formed on the package substrate described above. First, adjustment of the solder resist composition for a solder bump will be described. Here, the epoxy group 5 of an 80% by weight cresol novolak type epoxy resin (manufactured by Nippon Kayaku) dissolved in DMDG is used.
46.67 g of a photosensitizing oligomer (molecular weight: 4000) in which 0% was acrylated, 15.0 g of a 80% by weight bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (Shikoku Chemicals, product name: 2E4MZ-
CN), 1.6 g, polyvalent acrylic monomer (trade name: R604, manufactured by Nippon Kayaku Co., Ltd.), which is a photosensitive monomer, and polyvalent acrylic monomer (trade name, manufactured by Kyoeisha Chemical; trade name: DPE)
6A) 1.5 g and 0.71 g of a dispersion antifoaming agent (manufactured by San Nopco, trade name: S-65) were mixed, and 2 g of benzophenone (manufactured by Kanto Chemical) as a photoinitiator was added to the mixture. 0.2 g of Michler's ketone (manufactured by Kanto Chemical Co.) as a photosensitizer was added, and the viscosity was 2.0 Pa ·
s is obtained. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type).
In the case of 0 rpm, the rotor No. In the case of 4, 6 rpm, the rotor No. According to 3.

(12) The substrate is coated with a solder resist composition in a thickness of 20 μm. Next, after performing a drying process at 70 ° C. for 20 minutes and at 70 ° C. for 30 minutes,
Exposure to ultraviolet light of mJ / cm ² , DMTG development processing,
A solder resist layer 80 having an opening in the pad portion 81 is obtained (see FIG. 5 (Q)). The opening diameter of the pad portion 81 is 1 on the upper surface side.
33 μm and 600 μm on the lower surface side.

(13) Next, the substrate 30 on which the solder resist layer 80 was formed was replaced with 30 g / l of nickel chloride, 10 g / l of sodium hypophosphite, and 10 g of sodium citrate.
/ L of electroless nickel plating solution of pH = 5
Then, a nickel plating layer 82 having a thickness of 5 μm is formed in the pad (opening) 81 (see FIG. 5 (R)).
Further, the substrate 30 was coated with 2 g of potassium gold cyanide /
l, 75 g / l ammonium chloride, 50 g / l sodium citrate, and 10 g / l sodium hypophosphite in an electroless gold plating solution at 93 ° C. for 23 seconds.
A gold plating layer 84 having a thickness of 0.03 μm is deposited on the nickel plating layer 82 and a solder pad 8 having a diameter of 133 μm is formed on the upper surface.
6U, a solder pad 86D having a diameter of 600 μm is formed on the lower surface.

(14) A metal mask 98 having an opening 98 a having a thickness of 40 μm and a diameter of 160 μm is placed, and an upper surface side solder pad 86 in the opening 81 of the solder resist layer 80 is placed.
A solder paste having an average particle diameter of 20 μm is printed on U (see FIG. 6 (S)), and the solder paste is similarly printed on the solder pad 86D on the lower surface side. In this solder paste printing step, the same amount of solder paste as on the conductor circuit 72 may be printed on the via holes 70, and therefore, the metal mask 9
The diameters of all the eight openings 98a can be made equal. For this reason, openings 19 of a plurality of diameters for forming the multilayer printed wiring board of the prior art described above with reference to FIG.
The metal mask 98 of the present embodiment can be easily formed as compared with the metal mask 198 including 8a and 198b.

Following the printing of the solder paste, the substrate 30 was
Heat reflow is performed at 00 ° C. to provide a solder bump 88U having a diameter of 133 μm on the upper surface side solder pad 86U and a solder bump 88D having a diameter of 600 μm on the lower surface side solder pad 86D, thereby completing the formation of the solder bump (see FIG. 6 (T)). ). Thereafter, the surface of the multilayer printed wiring board 10 is washed with a surfactant solution, and the flux that has permeated from the solder paste during the reflow is washed away.

In the conventional multilayer printed wiring board 310 described above with reference to FIG. 10C during flux cleaning, a large amount of solder paste is inserted into the via hole 170 to form the via hole 170. A large amount of flux is emitted from the solder bumps, and it is difficult to completely remove the flux. On the other hand, in the multilayer printed wiring board 10 of the present embodiment, only a small amount of solder paste is printed on the via holes 70 as on the conductor circuit 72, so that the flux can be completely washed away.

Further, at the time of reflow at 200 ° C., the multilayer printed wiring board 310 according to the prior art greatly warps,
The mounting accuracy of the C chip has decreased. On the other hand, in the multilayer printed wiring board 10 of the present embodiment, warpage at the time of reflow is reduced. The reason for this is that, in the conventional multilayer printed wiring board 310, the via hole 170 is hollow, and the via hole itself is deformed, whereas in the present embodiment, the via hole 70 is formed of copper plating 68
It is presumed that the via holes 70 themselves are not deformed by heat.

Finally, an IC is mounted on the multilayer printed wiring board 10.
The chip 90 is mounted so that the solder pads 92 of the IC chip 90 correspond to the solder bumps 88U on the multilayer printed wiring board side, and reflowed in a heating furnace to attach the IC chip 90 to the multilayer printed wiring board 10. (See FIG. 6 (U)). Then, the multilayer printed wiring board 10 and I
A surfactant solution is injected into the space between the C chip 90 and the flux that has oozed out of the solder paste during the reflow.

In cleaning the flux, a surfactant solution must be injected into a narrow space between the multilayer printed wiring board 10 and the IC chip, so that the prior art described with reference to FIG. In the multilayer printed wiring board 310, it was difficult to completely remove the flux of the solder bumps formed in the via holes 170. On the other hand, in the multilayer printed wiring board 10 of the present embodiment, only a small amount of solder paste is printed on the via holes 70 as on the conductor circuit 72, so that the flux can be completely washed away.

After the reflow process, a resin is injected into the space between the multilayer printed wiring board 10 and the IC chip, the space is sealed with resin, and the entire IC chip 90 is covered with the resin. Perform resin molding (not shown). Thereafter, the multilayer printed wiring board on which the IC chip 90 is mounted is mounted on the motherboard 95 (see FIG. 6 (U)).

FIG. 8 shows a multilayer printed wiring board 110 according to a second embodiment of the present invention. In the multilayer printed wiring board according to the first embodiment described above with reference to FIG.
Copper plating was filled not only in the upper via holes 70 where the solder bumps are formed but also in the lower via holes 40 formed in the lower interlayer resin insulation layer 40. On the other hand, in the multilayer printed wiring board of the second embodiment, the lower via hole 50 is filled with resin as in the prior art described above with reference to FIG. The upper via hole 70 of the first embodiment has a recess 70a at the center, whereas the upper via hole 70 of the second embodiment has a smooth surface. Further, in the first embodiment, the gold plating layer 84 is formed as a noble metal layer on the upper surface of the upper via hole 70 and the conductor circuit 72.
Whereas, in the second embodiment, a platinum plating layer 84 is formed. Also in the second embodiment, similarly to the first embodiment, the solder bumps 88U, 88D
Connection reliability can be improved.

FIG. 9 shows a multilayer printed wiring board 210 according to a third embodiment of the present invention. In the multilayer printed wiring board according to the first embodiment described above with reference to FIG.
Solder bumps 8 in conductor circuit 72 and upper via hole 70
8U and 88D are formed. On the other hand, in the multilayer printed wiring board of the third embodiment, the upper via hole 7
0 are formed with solder bumps 88U and 88D. Also in the multilayer printed wiring board 210 of the third embodiment, the openings 6 of the upper interlayer resin insulation layer 60 are formed similarly to the first embodiment.
2 is roughened, and the via holes 7
2 and the surface of the conductor circuit 70 are roughened. Further, a nickel plating layer 8 is formed on the surface of the via hole 72.
2 and a gold plating layer 84 are formed.
Solder bumps are formed on the

Also in the third embodiment, as in the first embodiment, the opening 62 of the interlayer resin insulating layer 60 is filled with an electrolytic copper plating film (metal) 68 so that the height of the surface of the via hole 70 is increased. Are all equal. Therefore, by printing the solder paste, the heights of the solder bumps 88U and 88D formed in the via hole 70 can all be made equal. Therefore, the connection reliability of the solder bumps 88U and 88D can be improved.

In the above-described embodiment, the package substrate formed by the semi-additive method is exemplified.
The structure of the present invention can be applied to a package substrate formed by a full additive method. Further, in the above-described embodiment, the package substrate is taken as an example of the multilayer printed wiring board. However, it goes without saying that the configuration of the present invention can be suitably applied to a multilayer printed wiring board other than the package substrate.

[0052]

As described above, in the multilayer printed wiring board according to the first aspect, by filling the openings with plating, the height of the surface of the via hole can be reduced to the height of the conductor circuit on which the solder bumps are formed. They are equal. Therefore, by printing the same amount of solder paste on the via hole and the conductor circuit, the solder bump formed in the via hole,
Since the height can be made equal to the height of the solder bump formed on the conductor circuit, the connection reliability of the solder bump can be improved.

Further, in the multilayer printed wiring board according to the second aspect, by filling the openings with metal, the heights of the surfaces of the via holes are all equal. Therefore, by printing the solder paste, the heights of the solder bumps formed in the via holes can all be made equal. For this reason, the connection reliability of the solder bumps can be improved.

[Brief description of the drawings]

1 (A), 1 (B), 1 (C), 1
(D) is a figure which shows the manufacturing process of the multilayer printed wiring board which concerns on 1st Embodiment of this invention.

FIG. 2 (E), FIG. 2 (F), FIG. 2 (G), FIG.
(H) is a figure which shows the manufacturing process of the multilayer printed wiring board which concerns on 1st Embodiment of this invention.

FIG. 3 (I), FIG. 3 (J), FIG. 3 (K), FIG.
(L) is a figure which shows the manufacturing process of the multilayer printed wiring board which concerns on 1st Embodiment of this invention.

FIG. 4 (M), FIG. 4 (N), and FIG. 4 (O) are views showing a manufacturing process of the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 5 (P), FIG. 5 (Q), and FIG. 5 (R) are views showing the steps of manufacturing the multilayer printed wiring board according to the first embodiment of the present invention.

FIGS. 6 (S), 6 (T), and 6 (U) are cross-sectional views showing a multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a sectional view showing the multilayer printed wiring board according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing a multilayer printed wiring board according to a second embodiment of the present invention.

FIG. 9 is a sectional view showing a multilayer printed wiring board according to a third embodiment of the present invention.

10 (A), 10 (B), 10
(C), FIG.10 (D) is a figure which shows the manufacturing process of the multilayer printed wiring board based on a prior art.

DESCRIPTION OF SYMBOLS 30 core substrate 40 interlayer resin insulation layer 50 via hole 52 conductor circuit 60 outermost interlayer resin insulation layer 62 opening 62a side surface 68 electrolytic copper plating film (metal) 70 upper layer via hole 70a recess 72 conductor circuit 80 solder Resist layer 84 Gold plating 86U, 86D Solder pad 88U, 88D Solder bump

Claims (6)

[Claims] 1. A multilayer printed wiring board in which interlayer resin insulation layers and conductor circuits are alternately laminated, wherein: a solder bump formed on a conductor circuit provided on an outermost interlayer resin insulation layer; And a solder bump formed on a via hole formed by filling a metal in an opening formed in the outermost interlayer resin insulating layer. 2. A multilayer printed wiring board in which interlayer resin insulating layers and conductive circuits are alternately laminated, wherein a solder bump is formed on a via hole formed by filling an opening formed in the interlayer resin insulating layer with metal. The multilayer printed wiring board characterized by being formed. 3. The multilayer printed wiring board according to claim 1, wherein a recess is formed in a central portion of the via hole. 4. The multilayer printed wiring board according to claim 1, wherein a side surface of the opening of the interlayer resin insulating layer is roughened. 5. The surface of the via hole and the conductor circuit are roughened.
The multilayer printed wiring board according to any one of the above. 6. The via hole according to claim 1, wherein a metal layer having a noble metal layer is formed on at least the surface of the via hole, and a solder bump is formed on the noble metal. A multilayer printed wiring board according to any one of the above.