KR20170037319A - Printed circuit board and method for manufacturing the same - Google Patents

Abstract

A printed circuit board according to an embodiment of the present invention includes an insulating layer on which a via hole is formed, a copper foil layer formed on one surface of the insulating layer by avoiding the via hole, and an electroless copper plating layer formed in the via hole, The thickness of the copper foil layer is thinner than the thickness of the electroless copper plating layer. Accordingly, the present invention can implement a micro circuit.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a printed circuit board

The present invention relates to a printed circuit board and a manufacturing method thereof.

The demand for electronic devices is not limited not only to reduction in size and weight, but also to high-speed communication and large capacity communication. For this reason, further miniaturization of electronic components, an increase in the number of parts, and an increase in the number of LSI input / output, etc., continue to progress. On the other hand, from the viewpoint of miniaturization, E weight reduction, and E thinning, there is a limitation in the area of the wiring board on which these electronic parts are mounted, and therefore, it is difficult to design larger than necessary. Therefore, it is required to form wiring with a higher density for the wiring board.

Japanese Patent Registration No. 3142270 (Manufacturing Method of Printed Circuit Board, published on Mar. 3, 2001)

An object of the present invention is to provide a printed circuit board capable of realizing a fine circuit and a method of manufacturing the same.

A printed circuit board according to an embodiment of the present invention includes an insulating layer formed with a via hole, an electroless plated layer formed in the via hole, a copper foil layer formed on one surface of the insulating layer, a via formed by plating on the electroless plated layer, And a circuit layer formed by plating on the copper foil layer, wherein the thickness of the copper foil layer is thinner than the thickness of the electroless copper plating layer.

A method of manufacturing a printed circuit board according to an embodiment of the present invention includes the steps of forming a copper foil layer on one side of an insulating layer, forming a film layer on the copper foil layer, passing through the copper foil layer, A step of forming an electroless plated layer in which the end portion is in contact with the copper foil layer and a step of removing the film layer in the via hole, wherein the thickness of the copper foil layer is thinner than the thickness of the electroless plated layer .

1 illustrates a printed circuit board according to one embodiment of the present invention.
2 to 10 are process drawings illustrating a method of manufacturing a printed circuit board according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective view of a printed circuit board according to a first embodiment of the present invention; Fig. A duplicate description will be omitted.

It is also to be understood that the terms first, second, etc. used hereinafter are merely reference numerals for distinguishing between identical or corresponding components, and the same or corresponding components are defined by terms such as first, second, no.

In addition, the term " coupled " is used not only in the case of direct physical contact between the respective constituent elements in the contact relation between the constituent elements, but also means that other constituent elements are interposed between the constituent elements, Use them as a concept to cover each contact.

Printed circuit board

1, a printed circuit board according to an embodiment of the present invention includes an insulating layer 110, a copper foil layer 120, and an electroless copper plated layer 130, and includes a circuit layer 140, a via 150, As shown in FIG. The seed layer of the circuit layer 140 is the copper foil layer 120 and the seed layer of the via 150 is the electroless copper plating layer 130. [

The insulating layer 110 may be a prepreg (PPG) or a build-up film. The prepreg may include a reinforcing material such as glass cloth. The buildup film layer may be a resin filled with a filler such as silica, and ABF (Ajinomoto Build-up Film) may be used.

The insulating layer 110 may be composed of multiple layers 111 and 112 and a via hole VH may be formed in the insulating layer 110. The via hole VH may be formed in the outermost layer 112 of the insulating layer 110 composed of multiple layers. The via hole VH may be formed by a laser process such as a CO ₂ laser or the like and may have an inverted trapezoidal cross section. On the other hand, the thickness of the via hole VH may be 60 mu m.

The inner layer circuit 113 and the inner layer pad 114 may be embedded in the insulating layer 110. In the case of the multilayer insulating layer 110, the inner layer circuit 113 and the innerlayer pad 114 are formed on the first layer 111 located at the lower portion, and the second layer 112 located at the upper portion is formed on the innerlayer circuit (113) and the inner layer pad (114). The inner layer circuit 113 and the inner layer pad 114 are electrically connected.

The innerlayer pad 114 is at least partially exposed by the via hole VH. That is, the via hole VH is formed on the innerlayer pad 114. The inner layer pad 114 is in electrical contact with the circuit layer 140 in contact with the via 150.

The copper foil layer 120 may be formed on one surface of the outermost layer of the insulating layer 110. The copper foil layer 120 serves as a base layer of the circuit layer 140 to be described later. That is, the copper foil layer 120 is formed by avoiding the via hole VH, and is formed only in a region where the circuit layer 140 is formed on one surface of the outermost layer of the insulating layer 110. Specifically, after the copper foil layer 120 'is formed by avoiding the via hole VH on the entire surface of the insulating layer 110, portions other than the region where the circuit layer 140 is formed are removed. Here, unnecessary removal of the copper foil layer can be performed by an etching method.

The copper foil layer 120 may be 0.05 탆 to 5 탆 thick, and may preferably be 1 탆 or less, for example, 0.3 탆. When the thickness of the copper foil layer 120 is 1 占 퐉 or less, the removal by the etching described above can be facilitated.

That is, in the step of etching the unnecessary copper foil layer, when the etching is an isotropic etching, it can be etched to the area of the circuit layer 140 beyond the desired area, 110). ≪ / RTI > However, when the thickness of the copper foil layer 120 is as thin as 1 占 퐉 or less, there is no problem of etching to the area to be the circuit layer 140 in the etching step.

The copper foil layer 120 may be formed by an electroless plating method, a sputtering method, or a laminate of commercially available metal foils. However, the copper foil layer 120 is not particularly limited as long as it can form a desired microcircuit in the present invention.

The copper foil layer 120 may be formed of a metal such as copper, chromium, titanium, or nickel in terms of electrical resistance, ease of etching, and cost. On the other hand, as the commercially available metal foil, a copper foil, an aluminum foil and the like can be used.

The electroless plating layer 130 may be a copper layer formed inside the via hole VH. The electroless plating plating layer 130 is formed only inside the via hole VH by avoiding one surface of the outermost layer of the insulating layer 110. That is, on the inner wall and bottom of the via hole VH. The electroless plating plating layer 130 may be formed by electroless plating, or a catalyst such as palladium (Pd) may be used.

Here, the thickness of the copper foil layer 120 may be thinner than the thickness of the electroless copper plating layer 130. That is, the copper foil layer 120 has a smaller thickness than the electroless copper plating layer 130. For example, the thickness of the electroless plated layer 130 may be greater than 1 um while the thickness of the copper foil layer 120 may be 0.3 um.

Since the electroless plating layer 130 is not formed on the copper foil layer 120 but is formed only in the via hole VH, the circuit layer 140 growing from the copper foil layer 120 can be realized as a microcircuit.

The circuit layer 140 is formed on the copper foil layer 120 as an outer layer circuit, and may be formed by plating. If the plating resist R is formed in a region other than the region where the circuit layer 140 is to be formed in the copper foil layer 120 ', the copper foil layer 120 is exposed only to the region where the circuit layer 140 is to be formed , And this is called an opening area (O). When the opening region O is plated, the plating layer grows from the exposed copper foil layer 120, and the circuit layer 140 is formed only in a desired region.

Thereafter, the plating resist R is removed, and the copper foil layers other than the regions where the circuit layers 140 are formed are removed by the above-described etching. In this case, the copper foil layer can be removed by flash etching.

The via 150 is formed on the electroless plated layer 130 and may be formed by plating. Also in this case, when the plating resist R is used for the portion excluding the via hole VH and plating is performed for the via hole VH, the plating layer is removed from the electroless copper plating layer 130 It grows. When the plating resist R is peeled off after the completion of the plating layer growth, the via 150 is formed in the via hole VH.

The circuit layer 140 and the vias 150 may be formed by the same plating process, in which case the same plating resist R may be used. The circuit layer 140 and the vias 150 can be simultaneously formed by plating after the plating resist R is formed on the remaining region except for the area where the circuit layer 140 and the via 150 are to be formed. That is, the opening area O of the photoresist becomes the area where the circuit layer 140 is formed and the via hole VH. In this case, since the volume of the plating region on the circuit layer 140 is different from the volume of the plating region on the via hole VH, the plating thickness can be adjusted using a lever or the like.

Circuit layer 140 and vias 150 may be formed by electroplating. The circuit layer 140 may be formed on the copper foil layer 120 and the vias 150 may be formed by electroplating based on the electroless copper plating layer 130. Since the electroless plated layer 130 is a conductive layer, the via 150 is formed by electroplating because it is electrically conductive.

In addition, the via pad 151 may be formed on the via 150, and the thickness of the via pad 151 may be the same as the thickness of the circuit layer 140. The cross sectional area of the via pad 151 may be larger than the cross sectional area of the via 150. In this case, the opening area O of the plating resist R around the via hole VH may be larger than the cross sectional area of the via hole VH .

The via pad 151 is in contact with the via 150 and may be electrically connected to the circuit layer 140. The via 150 is interposed between the inner layer pad 114 and the via pad 151 to interlayer connect the circuit layer 140 and the inner layer circuit 113 in the different layers of the insulating layer 110 .

Printed circuit board manufacturing method

2 to 10 are process diagrams illustrating a method of manufacturing a printed circuit board according to an embodiment of the present invention. 2 to 10, a method of manufacturing a printed circuit board includes the steps of forming a copper foil layer 120 ', forming a film layer F on the copper foil layer 120', forming a via hole VH Forming the electroless copper plating layer 130, removing the film layer F, and forming the circuit layer 140 and the vias 150. [0064]

The step of forming the copper foil layer 120 'is a step in which the copper foil layer 120' serving as a base of the circuit layer 140 is formed on one surface of the outermost layer of the insulating layer 110. The copper foil layer 120 'may be formed by an electroless plating method, a sputtering method, or a laminate of commercially available metal foils.

The step of forming the copper foil layer 120 'on one side of the outermost layer of the insulating layer 110 may include the steps of providing a carrier provided with the copper foil layer 120' Depositing a dielectric layer on the insulating layer 110 and removing the carrier.

The copper foil layer 120 'may be formed on the carrier by a plating method or a sputtering method. The carrier is stacked on the insulating layer 110, wherein the copper foil layer 120 'is interposed between the carrier and the insulating layer 110. When the carrier is removed, the copper foil layer 120 'remains on the insulating layer 110. The carrier is a material for protecting the copper foil layer 120 '.

The copper foil layer 120 'is formed on one surface of the insulating layer 110. The copper foil layer 120 'may be 0.05 袖 m to 5 袖 m thick, and may preferably be 1 袖 m or less, for example, 0.3 袖 m. When the thickness of the copper foil layer 120 is 1 占 퐉 or less, the removal by etching can be facilitated.

The copper foil layer 120 'may be formed of a metal such as copper, chromium, titanium, or nickel in terms of electrical resistance, ease of etching, and cost. On the other hand, as the commercially available metal foil, a copper foil, an aluminum foil and the like can be used.

The step of forming the film layer F on the copper foil layer 120 'is a step of forming a film layer F covering the copper foil layer 120'.

The film layer (F) may be a resin film. Further, the film layer (F) may be a film composed of a polyolefin material selected from polyethylene, polypropylene, polymethylpentene and a copolymer or a polymer blend composed of these components. These films of these components are excellent in chemical resistance, and therefore are not deformed, deformed, swelled, dissolved, or the like due to a dispersion liquid. In addition, such a film may be laminated on the copper foil layer 120 'with a laminator for a dry film.

The film layer (F) may be in the form of a single film on which no adhesive or release agent is formed. Further, the film layer (F) may contain no plasticizer. Since the adhesive layer, the release material, the plasticizer, and the like are not formed on the film layer F, unnecessary foreign matters are not generated in the process of manufacturing the printed circuit board.

On the other hand, the film layer F has a thickness of 3 to 50 mu m and preferably has a thickness of 5 to 20 mu m in consideration of ease of handling, availability and cost.

The step of forming the via hole VH is a step of forming a hole penetrating the film layer F, the copper foil layer 120 'and the insulating layer 110. The via hole VH can be formed by laser machining or drilling.

In the process of forming the via hole VH, a resin residue may exist in the via hole VH while the resin of the insulating layer 110 is melted. Such a resin residue is called a smear, and a desmearing step may be included to remove the smear. In the desmear step, the smear is removed by the desmear liquid.

In the desmear step, the film layer (F) prevents the copper foil layer 120 'from being damaged by the liquid dispersion. In addition, since the film layer F itself should not be damaged by the desmear liquid, the film layer F may contain components such as polyethylene, polypropylene, polymethylpentene and the like.

The step of forming the electroless plating plating layer 130 is a step of forming a conductive layer on the inner wall and the bottom of the via hole VH. This conductive layer may be copper. The electroless plating plating layer 130 may be formed by electroless plating, or a catalyst such as palladium (Pd) may be used.

The film layer F prevents the electroless plated layer 130 from being formed on one surface of the insulating layer 110 or on the copper foil layer 120 '. That is, since the copper foil layer 120 'is covered with the film layer F, the electroless copper plating layer 130 may not be formed on the copper foil layer 120'.

The thickness of the copper foil layer 120 'may be thinner than the thickness of the electroless plated layer 130. That is, the copper foil layer 120 'has a thickness smaller than that of the electroless copper plating layer 130. In this case, since the electroless plated layer 130 is not formed on the copper foil layer 120 'but is formed only in the via hole VH, the circuit layer 140 growing from the copper foil layer 120' .

If there is no film layer F, the electroless copper plating layer 130 may be formed on the copper foil layer 120 ', and the circuit layer 140 may be formed on the copper foil layer 120' and the electroless copper plating layer 130. [ The height of the entire circuit becomes higher than that of the electroless plated layer 130, and a minute circuit can not be realized.

That is, by using the film layer F, the electroless plated layer 130 can be formed only in the via hole VH, and the circuit layer 140 can be formed finer.

The step of removing the film layer F is a step of removing the film layer F covering the copper foil layer 120 'by peeling or the like after the electroless copper plating layer 130 is formed. The method of removing the film layer (F) is not limited.

The step of forming the circuit layer 140 is a step of forming a plating resist R on the copper foil layer 120 'and forming a plating layer after patterning the plating resist R. The step of forming the via 150 is a step of forming a plating layer inside the via hole VH.

The circuit layer 140 and the vias 150 can be formed by the same plating process. In this case, the same plating resist R can be used. That is, the plating resist R is laminated on the copper foil layer 120 'and the via hole VH to remove the plating resist R on the region where the circuit layer 140 is to be formed and the via hole VH region. The removed region of the plating resist R may be referred to as an opening region O. [

When the opening area O is plated, the circuit layer 140 and the vias 150 are formed. In this case, the circuit layer 140 and the vias 150 may be formed by electroplating. The circuit layer 140 may be formed on the copper foil layer 120 and the vias 150 may be formed by electroplating based on the electroless copper plating layer 130.

The step of forming the circuit layer 140 includes removing the copper foil layer on which the circuit layer 140 is not formed. The copper foil layer 120 may be removed by etching. At this time, an etching resist may be used to remove only the copper foil layer in a specific region.

If there is no film layer F as described above, since the electroless plated layer 130 is added to the copper foil layer 120 as the basis for forming the circuit layer 140, the overall thickness of the circuit is increased as described above. In this case, it is a natural result that the etching time is also increased at the time of etching for removing the unnecessary copper foil layer.

That is, by using the film layer F as in the embodiment of the present invention, not only the circuit thickness but also the etching time can be reduced. In addition, as the circuit thickness is reduced, a microcircuit can be realized and the yield for a microcircuit can be increased.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit of the invention as set forth in the appended claims. The present invention can be variously modified and changed by those skilled in the art, and it is also within the scope of the present invention.

110: insulating layer
111: first layer
112: Second layer
113: Inner layer circuit
114: Inner layer pad
VH: Via hole
120, 120 ': copper foil layer
130: electroless galvanized layer
140: Circuit layer
150: Via
151: via pad
F: film layer
R: plating resist
O: opening area

Claims (10)

An insulating layer on which a via hole is formed;
An electroless plated layer formed in the via hole;
A copper foil layer formed on one surface of the insulating layer;
A via formed on the electroless plated layer by plating; And
And a circuit layer formed by plating on the copper foil layer,
Wherein the thickness of the copper foil layer is thinner than the thickness of the electroless copper plating layer.
The method according to claim 1,
Wherein the thickness of the copper foil layer is 1um or less.
The method according to claim 1,
And an inner layer pad formed in the insulating layer, wherein at least a portion of the inner layer pad is in contact with the via.
The method according to claim 1,
And the electroless plated layer is formed only inside the via hole.
Forming a copper foil layer on one surface of the insulating layer;
Forming a film layer on the copper foil layer;
Forming a via hole through the copper foil layer, the film layer, and the insulating layer;
Forming an electroless plated layer on the inside of the via hole, the end of the plated layer being in contact with the copper foil layer; And
Removing the film layer,
Wherein the thickness of the copper foil layer is thinner than the thickness of the electroless copper plating layer.
6. The method of claim 5,
Forming a circuit layer on the copper foil layer; And
And forming a via on the electroless copper plating layer.
6. The method of claim 5,
Wherein the thickness of the copper foil layer is 1um or less.
6. The method of claim 5,
Wherein the film layer is formed of a material containing at least one of polyethylene, polypropylene, and polymethylpentene.
6. The method of claim 5,
Between the step of forming the via hole and the step of forming the electroless plated layer,
The method further comprising a desmear step.
6. The method of claim 5,
Wherein the step of forming the copper foil layer on one surface of the insulating layer comprises:
Providing a carrier having the copper foil layer;
Depositing the carrier on the insulating layer such that the copper foil layer is interposed therebetween; And
And removing the carrier.

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