CN106455312A - Wiring board and manufacturing method thereof - Google Patents
Wiring board and manufacturing method thereof Download PDFInfo
- Publication number
- CN106455312A CN106455312A CN201610462783.4A CN201610462783A CN106455312A CN 106455312 A CN106455312 A CN 106455312A CN 201610462783 A CN201610462783 A CN 201610462783A CN 106455312 A CN106455312 A CN 106455312A
- Authority
- CN
- China
- Prior art keywords
- wiring
- layer
- insulating barrier
- circuit board
- width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
- H05K2201/098—Special shape of the cross-section of conductors, e.g. very thick plated conductors
Abstract
The invention provides a wiring board and a manufacturing method thereof. According to the wiring board, on the surface of an insulating layer, an embedded wiring conductor is exposed out of the top surface, and the wiring conductor is embedded in a wiring step portion or a wiring inclination portion embedded in the insulating layer and equipped with the width wider than the width of the top surface.
Description
Technical field
The present invention relates to circuit board and its manufacture method with highdensity fine wiring.
Background technology
In the past, comprise the circuit board of multiple insulating barrier between each insulating barrier and the surface tool of insulating barrier on top layer
Standby wiring conductor.Form multiple via at each insulating barrier.The coating mistake being integrally formed with wiring conductor in the inside of via
Hole conductor.Via conductor obtains the conducting between the wiring conductor being formed at each insulating barrier.The wiring conductor of the superiors is embedded in
Insulating barrier, so that end face exposes on the surface of insulating barrier.In addition, a part for the wiring conductor of the superiors forms semiconductor element
Part connects pad.Connect the electricity via semiconductor elements such as solder connection semiconductor integrated circuit elements for the pad at semiconductor element
Pole.The part being formed at undermost wiring conductor forms circuit substrate connection pad.Connect pad at circuit substrate to connect
Carry the electrode of the circuit substrate of this circuit board.Further, by leading via wiring between semiconductor element and circuit substrate
Body enters the transmission of horizontal electrical signal, thus semiconductor element works.Such circuit board is for example recorded in the clear 63-of TOHKEMY
In No. 232483 publications.
Content of the invention
The circuit board of the disclosure makes end face bury wiring conductor underground with exposing on the surface of insulating barrier, and described wiring conductor exists
The part being embedded in described insulating barrier possess width be wider than described end face width wiring stage portion or wiring rake.
In the manufacture method of the circuit board involved by the disclosure, substrate metal layer is formed and possesses patterns of openings
Plating resist oxidant layer, this patterns of openings possesses the opening stage portion of narrowed width or opening rake towards this substrate metal layer side,
In described patterns of openings, filling has wiring stage portion corresponding with described opening stage portion or opening rake or wiring is inclined
The metal plating layer of the wiring conductor in oblique portion, and remove described plating resist oxidant layer, on described substrate metal layer and described
Form the insulating barrier that described metal plating layer is buried underground completely on metal plating layer, and the etching of described substrate metal layer removed,
Forming wiring conductor, its end face exposes from described insulating barrier, and is included in the part being embedded in described insulating barrier and possesses width
It is wider than the described wiring stage portion of the width of described end face or the described metal plating layer of wiring rake.
Brief description
Fig. 1 is the general profile chart of 1 embodiment representing the circuit board involved by the disclosure.
Fig. 2 is the major part amplification view in 1 embodiment of the circuit board involved by the disclosure.
Fig. 3 A～D is the outline of 1 embodiment of the manufacture method for the circuit board involved by the disclosure is described
Sectional view.
Fig. 4 E～I is the outline of 1 embodiment of the manufacture method for the circuit board involved by the disclosure is described
Sectional view.
Fig. 5 J～L is the outline of 1 embodiment of the manufacture method for the circuit board involved by the disclosure is described
Sectional view.
Fig. 6 M～O is the outline of 1 embodiment of the manufacture method for the circuit board involved by the disclosure is described
Sectional view.
Fig. 7 is the major part amplification view of other embodiments representing the circuit board involved by the disclosure.
Fig. 8 is the major part of other embodiments of the manufacture method for the circuit board involved by the disclosure is described
Amplification view.
Fig. 9 is the main portion of the still another embodiment of the manufacture method for the circuit board involved by the disclosure is described
Divide amplification view.
Detailed description of the invention
With the propelling of the miniaturization of wiring conductor, wiring conductor diminishes with insulating barrier contact area.Its result, wiring is led
The contiguity intensity of body diminishes, and wiring conductor becomes prone to peel off from insulating barrier.Have for this and can not pass well via wiring conductor
The situation that power transmission signal, semiconductor element work astatically.
In the circuit board of the disclosure, buried underground wiring conductor for making end face expose on the surface of insulating barrier, buried
The part being located in insulating barrier possess width be wider than end face width wiring stage portion or wiring rake.So, due to width
Degree is wider than the wiring stage portion of the width of end face or wiring rake is embedded in insulating barrier, and wiring conductor therefore can be suppressed from absolutely
Edge layer is peeled off.Hereinafter, 1 embodiment of the circuit board involved by the disclosure is described based on Fig. 1 and Fig. 2.Fig. 2 is figure
The major part enlarged drawing of 1.
As shown in Figure 1, the circuit board A of 1 embodiment for example has the multilayer of the insulating barrier 1 being laminated 4 layers
Structure, between each insulating barrier 1 and top layer insulating barrier 1 surface formed wiring conductor 2.Insulating barrier 1 for example can be by
The heat-curing resin such as epoxy resin, bismaleimide-triazine resin is formed, and is dispersed with inorganic insulation filler.At insulating barrier
1 for example forms multiple via 3 by Laser Processing, is filled the via conductor 4 for obtaining interlayer conduction in via.Via 3
For example can there is the diameter of 20～100 μm of degree.It is coated in the inside of via 3 and lead with the via that wiring conductor 2 forms
Body 4.
Wiring conductor 2 is for example formed by the good conductive material of electroless plating, electrolysis plating etc..The wiring conductor 2 of the superiors
A part formed semiconductor element connect pad 5.Connect pad 5 at semiconductor element and connect semiconductor integrated circuit element etc.
The electrode of semiconductor element.The part being formed at undermost wiring conductor 2 forms circuit substrate connection pad 6.At electricity
Base board connects the electrode that pad 6 connects the circuit substrate carrying this circuit board A.Further, by semiconductor element and electricity
Enter the transmission of horizontal electrical signal between base board via wiring conductor 2, thus semiconductor element works.The wiring conductor 2 of the superiors
It is embedded in insulating barrier 1 as shown in Figure 2, so that end face exposes on the surface of insulating barrier 1.And then, it is being embedded in insulation
The part of layer 1 possesses the wiring rake 2a that width is wider than the width of end face.
So, the circuit board according to the disclosure, the wiring rake 2a that width is wider than the width of end face is embedded in absolutely
Edge layer 1.Thus, even if advancing the miniaturization of wiring conductor 2, the contiguity intensity of wiring conductor 2 is also difficult to diminish, and also can prevent cloth
Line conductor 2 peels off from insulating barrier 1.Therefore its result, owing to can be provided that half only by wiring conductor 2 transmitting telecommunication number well
The circuit board of conductor element energy steady operation.
It follows that 1 embodiment party of the manufacture method of the circuit board involved by the disclosure is described based on Fig. 3～Fig. 6
Formula.In addition, add identical symbol, detailed to Fig. 1 same area.
As shown in Figure 3A, prepare prepreg (prepreg) the 7th, 2 adhering films 8 and 2 and can separate metal forming
9.Prepreg 7 uses to form supporting substrates 10, and this supporting substrates 10 is for manufacturing midway when manufacturing substrate A
Circuit board A maintains the flatness needing ground to be supported.Prepreg 7 has a goods formation region X at central portion, and
Peripheral part has to have more than needed gives up region Y.
Goods formation region X is the region of square shape, at this goods formation formation circuit board A on the X of region.?
In present embodiment, in order to easy and only illustrate the corresponding goods formation region X with 1 circuit board A.In fact, goods
Formation region has and the corresponding area of tens of～thousands of circuit board A.The region Y that gives up more than needed is to surround goods formation district
The region of the corner frame-shaped of territory X.Prepreg 7 has substantially square shape, can have the thickness of 0.1～0.2mm degree, have
It is respectively the length of 400～900mm degree in length and breadth.Prepreg 7 has for example makes glass fibre be impregnated with the thermosettings such as epoxy resin
The property changed resin the tabular in semi-cured state.
Adhering film 8 is inserted into prepreg 7 and can separate between metal forming 9, by cured prepreg 7 and energy
Separate metal forming 9 bonding.Adhering film 8 can have the thickness of 24～50 μm of degree, can also have in length and breadth be respectively 400～
The length of 900mm degree.Adhering film 8 is for example formed by the heat-pesistant thin film of epoxy resin, polyimide resin etc..
Metal forming 9 can be separated and comprise the 1st metal forming 9a and the 2nd metal forming 9b.1st metal forming 9a and the 2nd metal forming 9b exist
Hold with little try hard to keep to the contiguity that can be separated from each other across adhesive linkage (not shown) therebetween.1st metal forming 9a has more than goods
Formed by region X, the size being less than the 2nd metal forming 9b.1st metal forming 9a also can have the thickness of 15～20 μm of degree.2nd
Metal forming 9b has the size distinguishing little 5mm degree than prepreg 7 in length and breadth.1st metal forming 9a also can have 5～9 μm of journeys
The thickness of degree.
Metal forming 9 can be separated and for example comprise copper etc..Adhesive linkage considers to be resistant to the heat applied in the formation of circuit board A
Load, for example, can be formed by the metal level of the heat resistance sticky materials such as silicones system, acrylic resin or nickel system.So
Adhesive linkage consider when separating lamination described later (buildup) portion 12 from supporting substrates 10 at the 1st metal forming 9a and the 2nd gold medal
Belong to and mutually separating without peeling off residual ground between paper tinsel 9b, can have the little adhesion strength of 1～9N/m degree.
It follows that as shown in fig. 3b, the central portion in prepreg 7 upper and lower surface configures energy across adhering film 8
Separate metal forming 9, make the 1st metal forming 9a become prepreg 7 side.By the duplexer shown in Fig. 3 B while from pressurizeing on one side up and down
Heat.By so pressurizeing and heating, as shown in Figure 3 C, upper and lower at the prepreg 7 being cured
Surface forms the supporting substrates 10 that fixed bonding can separate metal forming 9.It follows that as shown in Figure 3 D, comprising to divide
Two interareas from the supporting substrates 10 of metal forming 9 form conductor layer 11 (substrate metal layer).Conductor layer 11 for example can be with known
Plating method formed, there is the thickness of 0.01～0.1 μm of degree.
As shown in Figure 4 E, coating on the surface of conductor layer 11 have multiple patterns of openings P corresponding with wiring pattern
Plating resist agent R.Patterns of openings P has the opening rake Pa of narrowed width towards conductor layer 11 side.Plating resist agent R is for example as follows
Formed like that.First, the resin flake being made up of photoresist or resin plaster are coated to or are coated in conductor layer 11 surface.Connect
Get off, across being exposed the mask with the corresponding part shading of patterns of openings P to photoresist.It follows that by photosensitive
Property resin development removes non-exposed part, is consequently formed the plating resist agent R with patterns of openings P.
For example, the surface by making conductor layer 11 is smooth forms opening rake Pa.Conductor layer 11 can have 60nm
Following surface roughness (Ra).Smooth by the surface that makes conductor layer 11, reach the incidence during exposure on conductor layer 11 surface
Light will not be blocked by the protuberance on conductor layer 11 surface.Its result, light during exposure incides wiring pattern region, thus conductor layer
Photoresist near 11 is solidified to form opening rake Pa.
As illustrated in figure 4f, in patterns of openings P, filling has wiring rake 2a corresponding with opening rake Pa
The metal plating layer 2P of wiring conductor.For example by known semi-additive process (semi-additive method) at conductor layer
The coating conductive pattern being formed by electrolytic copper free plating and cathode copper plating in the surface of 11, is consequently formed metal plating layer 2P.
It follows that as shown in Figure 4 G, by removing plating resist agent R, the side of the wiring rake 2a comprising metal plating layer 2P is made
Expose.
As shown at figure 4h, it is laminated insulating barrier 1, so that coated conductor layer 11 and metal plating layer 2P.At this moment, absolutely
Edge layer 1 enters between conductor layer 11 and wiring rake 2a, buries wiring rake 2a underground.It follows that as shown in fig. 41 that
Sample, forms metal plating layer 2P as the via 3 of bottom surface at insulating barrier 1.It follows that as indicated at figure 5j, in via 3
Form via conductor 4, form wiring conductor 2 on the surface of insulating barrier 1.It follows that as it can be seen from figure 5k, exhausted by next layer
The similarly mutual multilayer of edge layer 1 and wiring conductor 2 is laminated, and is consequently formed the lamination portion 12 of circuit board.
Insulating barrier 1 as described above, is formed by the heat-curing resin such as epoxy resin, bismaleimide-triazine resin.
Insulating barrier 1 is for example formed as follows.First, the uncured thing at epoxy resin or bismaleimide-triazine resin constituent
Middle dispersion inorganic insulation filler forms film.The film being formed is being coated in vacuum state the two of supporting substrates 10
Carry out thermo-compression bonding in the state of insulating barrier 1 surface of conductor layer 11 surface of interarea or lower floor, be consequently formed insulating barrier 1.Absolutely
Edge layer 1 forms multiple via 3 by such as Laser Processing, is filled with the via conductor 4 for obtaining interlayer conduction in via.
As shown in fig. 5l, by by supporting substrates the 10th, conductor layer 11 and lamination portion 12 at goods formation region X
Cut off on the border of region Y with more than needed giving up, cut out supporting substrates the 10th, the conductor layer 11 of goods formation region X and amass
Layer portion 12.Dicing device is for example used in cut-out.
It follows that as shown in Fig. 6 M, conductor layer 11 and lamination portion 12 are separated from the 1st metal forming 9a.Thus, exist
The one side of conductor layer 11 forms the duplexer 13 that fixed bonding has the circuit board of the 2nd metal forming 9b.2nd metal forming 9 across
Adhesive linkage is maintained in the 1st metal forming 9a to the contiguity power that can separate with little.Thus, it is by the 1st metal forming 9a and the 2nd metal
Open between paper tinsel 9b and be easy to carry out separating without making duplexer 13 breakage.
It follows that etch removing the 2nd metal forming 9b as shown in fig. 6n.Finally, as shown in Fig. 6 O, etching solution is used
Conductor layer 11 is fully etched removing.Thus metal plating layer 2P exposes.So, formation has wiring as shown in Figure 1
The circuit board A of conductor 2, the end face of this wiring conductor 2 exposes from insulating barrier 1 and the part in being embedded in insulating barrier 1 possesses
Width is wider than the wiring rake 2a of the width of end face.
As described above, the manufacture method of the circuit board according to involved by the disclosure, forms wiring conductor 2, its end face
Expose from insulating barrier 1, and the part in being embedded in insulating barrier 1 possesses the wiring rake 2a that width is wider than the width of end face.
So, width is wider than the wiring rake 2a of the width of end face and is embedded in insulating barrier 1.Thus, even if advancing wiring conductor 2
Miniaturization, the contiguity intensity of wiring conductor 2 is also difficult to diminish, and also can prevent wiring conductor 2 from peeling off from insulating barrier 1.Its result,
Owing to can therefore be provided that semiconductor element can the circuit board of steady operation via wiring conductor 2 transmitting telecommunication number well.
The manufacture method of the circuit board of the disclosure and circuit board is not limited to above-mentioned 1 embodiment, only
If without departing from the scope of idea of the invention, various change just can be carried out.
For example, in the above-mentioned circuit board involved by 1 embodiment, wiring conductor 2 has width and is wider than end face
The wiring rake 2a of width.But also can as shown in Figure 7, wiring conductor 2 has the cloth that width is wider than the width of end face
Line stage portion 2b.The surface of insulating layer on top layer for the above-mentioned circuit board involved by 1 embodiment is not coated to solder mask.
But also can be coated to solder mask.
For example in the manufacture method involved by 1 above-mentioned embodiment, as shown in Figure 4, plating resist agent R is being removed
Afterwards by insulating layer coating 1.But also can remove after plating resist agent R, add like that as shown in FIG. 8 and 9 to conductor layer 11 and
Metal plating layer 2P is etched the operation processing.
By carrying out such etch processes, the surface of conductor layer 11 and the surface of metal plating layer 2P are slowly dissolved.
On the other hand, being formed at the wiring rake 2a of metal plating layer 2P, etching solution is detained and is become compared to position dissolution velocity
Hurry up.Thus, compared to the situation not being etched process, district shared by rake 2a for the wiring in metal plating layer 2P is expanded
Territory.So, being expanded by making the wiring rake 2a being embedded in insulating barrier 1, the contiguity that can more promote wiring conductor 2 is strong
Degree.
Claims (6)
1. a circuit board, it is characterised in that
Make end face bury wiring conductor underground with exposing on the surface of insulating barrier, described wiring conductor is in being embedded in described insulating barrier
Part possess width be wider than described end face width wiring stage portion or wiring rake.
2. circuit board according to claim 1, wherein,
Described insulating barrier has sandwich construction, is at least made end face expose on the surface being formed at outermost insulating barrier by burying underground into
Wiring conductor, the part in being embedded in insulating barrier possesses the wiring stage portion of width or the cloth that width is wider than described end face
Line rake.
3. the manufacture method of a circuit board, it is characterised in that
Forming the plating resist oxidant layer with patterns of openings on substrate metal layer, this patterns of openings possesses towards this substrate metal layer side
And the opening stage portion of narrowed width or opening rake,
Fill in described patterns of openings and there is wiring stage portion corresponding with described opening stage portion or opening rake or cloth
Described plating resist oxidant layer is removed by the metal plating layer of the wiring conductor of line rake,
Form the insulation that described metal plating layer is buried underground completely on described substrate metal layer and on described metal plating layer
Layer, and the etching of described substrate metal layer is removed,
Forming wiring conductor, its end face exposes from described insulating barrier, and is included in the part tool being embedded in described insulating barrier
Standby width is wider than the described wiring stage portion of the width of described end face or the described metal plating layer of wiring rake.
4. the manufacture method of circuit board according to claim 3, wherein,
Described substrate metal layer has smooth surface.
5. the manufacture method of circuit board according to claim 4, wherein,
The surface of described substrate metal layer has the surface roughness of below 60nm.
6. the manufacture method of circuit board according to claim 3, wherein,
After described plating resist oxidant layer is removed, described metal plating layer and described substrate metal layer are etched further.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015126539 | 2015-06-24 | ||
| JP2015-126539 | 2015-06-24 | ||
| JP2015-147375 | 2015-07-27 | ||
| JP2015147375A JP2017011251A (en) | 2015-06-24 | 2015-07-27 | Wiring board and manufacturing method for the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106455312A true CN106455312A (en) | 2017-02-22 |
Family
ID=57761789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610462783.4A Pending CN106455312A (en) | 2015-06-24 | 2016-06-23 | Wiring board and manufacturing method thereof |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2017011251A (en) |
| KR (1) | KR20170000795A (en) |
| CN (1) | CN106455312A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI763052B (en) * | 2019-09-30 | 2022-05-01 | 日商京瓷股份有限公司 | Wiring substrate |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021140971A1 (en) * | 2020-01-08 | 2021-07-15 | パナソニックＩｐマネジメント株式会社 | Method for manufacturing wiring body, pattern plate, and wiring body |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000058986A (en) * | 1998-08-04 | 2000-02-25 | Matsushita Electric Ind Co Ltd | Wiring board and its manufacture |
| JP2008047655A (en) * | 2006-08-11 | 2008-02-28 | Mitsui Mining & Smelting Co Ltd | Wiring substrate and its manufacturing method |
| JP5032187B2 (en) * | 2007-04-17 | 2012-09-26 | 新光電気工業株式会社 | Wiring substrate manufacturing method, semiconductor device manufacturing method, and wiring substrate |
| JP6161437B2 (en) * | 2013-07-03 | 2017-07-12 | 新光電気工業株式会社 | Wiring substrate, manufacturing method thereof, and semiconductor package |
-
2015
- 2015-07-27 JP JP2015147375A patent/JP2017011251A/en active Pending
-
2016
- 2016-06-23 CN CN201610462783.4A patent/CN106455312A/en active Pending
- 2016-06-23 KR KR1020160078566A patent/KR20170000795A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI763052B (en) * | 2019-09-30 | 2022-05-01 | 日商京瓷股份有限公司 | Wiring substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2017011251A (en) | 2017-01-12 |
| KR20170000795A (en) | 2017-01-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20060016553A1 (en) | Method of fabricating high density printed circuit board | |
| US9899235B2 (en) | Fabrication method of packaging substrate | |
| CN109788666B (en) | Circuit substrate and manufacturing method thereof | |
| TW201438537A (en) | Method for manufacturing wiring substrates | |
| US7585419B2 (en) | Substrate structure and the fabrication method thereof | |
| JP2010153839A (en) | Method of manufacturing wiring substrate | |
| CN105122449A (en) | Low cost interposer comprising an oxidation layer | |
| CN106455312A (en) | Wiring board and manufacturing method thereof | |
| JP2015198094A (en) | Interposer, semiconductor device, and method of manufacturing them | |
| TWI531291B (en) | Package board and method for manufactuing same | |
| WO2004017689A1 (en) | Multilayer printed wiring board and production method therefor | |
| JP5432800B2 (en) | Wiring board manufacturing method | |
| CN103906354B (en) | Circuit board and method for manufacturing the same | |
| JP2013062293A (en) | Manufacturing method of multilayer wiring board | |
| US20090090548A1 (en) | Circuit board and fabrication method thereof | |
| TWI636720B (en) | Circuit board structure and method for fabricating the same | |
| US20160381793A1 (en) | Wiring board and method for manufacturing the same | |
| CN210694480U (en) | Line structure with interlayer guide hole | |
| KR101758859B1 (en) | Printed circuit board and method for manufacturing the same | |
| JP5408754B1 (en) | Multilayer wiring board and manufacturing method thereof | |
| JP4160813B2 (en) | Multilayer circuit board manufacturing method | |
| KR100736146B1 (en) | Method for fabricating the flexible circuit board | |
| JP2013045960A (en) | Wiring board and manufacturing method of the same | |
| JP2023129238A (en) | Package structure and manufacturing method thereof | |
| CN112638031A (en) | Circuit structure with interlayer guide hole and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20170222 |
|
| WD01 | Invention patent application deemed withdrawn after publication |