JP2013062293A - Manufacturing method of multilayer wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method which enables a multilayer wiring board having a preferably shaped inner layer wiring pattern to be relatively easily manufactured despite the fact that the strictness is not required for removal work of a conductive material during the pattern formation.SOLUTION: In a manufacturing method of a multilayer wiring board K1 of this invention, a barrier layer 61 is formed on a lower layer side resin insulation layer 16. Then, laser processing is performed simultaneously to the barrier layer 61 and the lower layer side resin insulation layer 16. An opening 63, penetrating through the barrier layer 61, is formed by this processing, and a groove 62 for inner layer wiring pattern formation, which communicates with the opening 63, is formed at the lower layer side resin insulation layer 16. Subsequently, the groove 62 and the opening 63 are buried with a conductive material 42 that should become an inner layer wiring pattern 28. Then, the barrier layer 61 is selectively removed. An upper layer side resin insulation layer 30 is formed on the lower layer side resin insulation layer 16 to bury the inner layer wiring pattern 28 between the lower layer side resin insulation layer 16 and the upper layer side resin insulation layer 30.

Description

  The present invention relates to a method for manufacturing a multilayer wiring board, and more particularly to a method for manufacturing a multilayer wiring board having a structure in which a fine inner layer wiring pattern made of a plating layer is disposed between adjacent resin insulation layers.

  In recent years, with the miniaturization and high performance of electronic devices, high-density mounting of electronic components is required. In achieving such high-density mounting, a multilayer circuit board technology for mounting an IC chip is regarded as important. As a concrete example using the multilayer technology, a multilayer wiring board (so-called build-up) having a build-up layer in which a resin insulating layer and a conductor layer are alternately laminated on one side or both sides of a core board provided with a through-hole portion or the like. Multilayer wiring boards) are well known.

  As a method for forming an inner layer wiring pattern in a multilayer wiring board, a semi-additive method is conventionally well known, but recently a method called a trench filling method has been proposed (for example, see Patent Documents 1 to 3). . The trench filling method employs a process of sequentially forming grooves (trench) in the lower resin insulation layer, filling the grooves by electroless copper plating, and removing excess copper plating protruding from the grooves (etching, polishing, etc.). ing. As a result, an inner layer wiring pattern made of copper plating buried in the groove is formed. Incidentally, the trench filling method is currently being studied as a method for forming a fine inner layer wiring pattern that is difficult to form by the semi-additive method.

JP-A-11-87276 JP 2007-84891 A JP 2009-132982 A

  However, in the trench filling method, it is necessary to remove excess copper plating protruding from the groove by etching or the like, but this operation is technically very difficult. In this case, if the removal operation is excessively performed, even the copper plating in the groove which is originally necessary is removed, so that the wiring breakage easily occurs. On the contrary, if the removal work is insufficient, excess copper plating protruding from the groove remains, so that a short circuit is likely to occur. Therefore, in the trench filling method, it is necessary to strictly control conditions such as etching for removing copper plating, and a multilayer wiring board cannot be easily manufactured.

  The present invention has been made in view of the above problems, and its purpose is to compare a multilayer wiring board having an inner layer wiring pattern having a suitable shape without requiring strictness in the work of removing a conductive material during pattern formation. An object of the present invention is to provide a manufacturing method that can be manufactured easily.

  As means for solving the above problems (means 1), a plurality of resin insulation layers are laminated, a substrate body having a substrate main surface and a substrate back surface, and an inner layer wiring extending along the surface direction of the substrate body A multilayer wiring board comprising: a pattern; a lower-layer resin insulation layer in contact with a bottom surface side of the inner-layer wiring pattern; and an upper-layer resin insulation layer adjacent to the lower-layer resin insulation layer and in contact with the upper surface side of the inner-layer wiring pattern In the manufacturing method, a barrier layer forming step of forming a barrier layer on the lower resin insulating layer and a laser processing of the barrier layer and the lower resin insulating layer simultaneously to form an opening penetrating the barrier layer And forming a groove for forming an inner layer wiring pattern in communication with the opening in the lower resin insulating layer, and forming the groove and the opening into the inner layer wiring pattern. A filling step of filling with a conductive material; a barrier layer removing step of selectively removing the barrier layer after the filling step; and forming the upper layer side resin insulation layer on the lower layer side resin insulation layer to form the lower layer side resin insulation And a burying step of embedding the inner layer wiring pattern between the upper layer and the upper resin insulating layer.

  Therefore, according to the invention relating to the above means, the barrier layer is formed in advance on the lower resin insulating layer, and both layers are laser processed simultaneously, thereby forming the opening and the groove for forming the inner layer wiring pattern communicating therewith. Is done. Next, after the trench and the opening are filled with a conductive material, the barrier layer is selectively removed. At this time, since the conductive material is not formed directly on the lower resin insulating layer but on the barrier layer, the excess conductive material can be removed relatively easily without excess or deficiency by removing the barrier layer. . As described above, according to the present invention, strictness is not required for the operation of removing the conductive material at the time of pattern formation, and a multilayer wiring board having a suitably shaped inner layer wiring pattern can be manufactured relatively easily.

  The plurality of resin insulating layers constituting the multilayer wiring board are formed using, for example, a thermosetting resin. Preferable examples of the thermosetting resin include EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide-triazine resin), phenol resin, xylene resin, polyester resin, silicon resin and the like. . Among these, it is preferable to select an EP resin, a PI resin, or a BT resin. For example, as the epoxy resin, a so-called BP (bisphenol) type, PN (phenol novolac) type, or CN (cresol novolac) type may be used. In particular, BP type is mainly used, and BPA (bisphenol A) type and BPF (bisphenol F) type are the best. Note that the plurality of resin insulating layers constituting the multilayer wiring board may be formed using a photocurable resin or the like.

  An inner layer wiring pattern is disposed between a plurality of adjacent resin insulation layers. The upper resin insulating layer in contact with the upper surface side of the inner wiring pattern and the lower resin insulating layer in contact with the bottom surface side may be formed using the same type of resin, or using different types of resins. It may be formed. As a suitable example of the lower layer side resin insulation layer and the upper layer side resin insulation layer, for example, the same kind of resin having a low coefficient of thermal expansion (CTE) (for example, 50 ppm / ° C. or less) and having thermosetting properties is used. Are formed. The inner layer wiring pattern is preferably a fine pattern having a maximum width of 20 μm or less, particularly a fine pattern having a maximum width of 10 μm or less.

  The inner layer wiring pattern extends along the surface direction of the substrate body, and is formed using a conductive material. Preferable examples of the conductive material include a plating material. The plating material is not particularly limited, and copper plating, nickel plating, gold plating, silver plating, aluminum plating, tin plating, cobalt plating, titanium plating, and the like can be employed. Considering conductivity, cost, workability, etc., the inner wiring pattern is preferably made of a copper plating layer, and more preferably a structure in which an electrolytic copper plating layer is formed on the electroless copper plating layer. .

  When the inner layer wiring pattern is cut in the stacking direction, the shape of the cut surface is not particularly limited. Further, the maximum width portion on the cut surface may be located at any position. For example, it may be arranged at a position between the upper end of the pattern and the lower end of the pattern. That is, it is preferable that the maximum width portion is not arranged at the upper end of the pattern or the lower end of the pattern. The magnitude relationship between the width at the upper end of the pattern and the width at the lower end of the pattern is not particularly limited. Therefore, the former may be larger than the latter, the latter may be larger than the former, or both may be equal.

  Here, the maximum width portion is arranged at an arbitrary position between the upper end of the pattern and the lower end of the pattern, for example, the same as the virtual plane formed at the boundary between the lower resin insulating layer and the upper resin insulating layer. Arranged in a plane. The maximum width portion may be arranged at a position between the virtual plane and the upper end of the pattern.

  For example, the size (width) of the maximum width portion is preferably 1.1 times or more and 1.5 times or less that of the pattern upper end and pattern lower end having a relatively large width. The reason is that if it is less than 1.1 times, a right-angled or acute-angled portion tends to occur at the upper end of the pattern. Conversely, if it exceeds 1.5 times, there is a possibility that a right-angle or acute-angle portion may occur in the maximum width portion.

  The cut surface in the stacking direction of the inner layer wiring pattern preferably has a shape that does not have an acute angle or a right angle. In other words, all the angles in the cut surface are preferably obtuse. This is because all the corners on the cut surface are less likely to be the starting point of crack generation, and the generation of cracks in the resin insulating layer can be effectively suppressed. Moreover, it is preferable that the corner | angular part in a cut surface is round regardless of an acute angle, a right angle, and an obtuse angle. Also in this case, the corners are unlikely to become the starting point of cracks. Most preferably, the corner portion of the cut surface has a rounded obtuse angle.

  On the cut surface in the stacking direction of the inner layer wiring pattern, the ratio between the width of the maximum width portion and the width of the upper end of the pattern is not limited, but may be set within a range of 10: 1 to 10: 9, for example. Further, the ratio of the width of the maximum width portion to the width of the lower end of the pattern is not limited in the cut surface in the stacking direction of the inner layer wiring pattern, but it may be set within a range of 10: 5 to 10: 9, for example. . When the ratio of the widths is within these preferable ranges, the corners at the cut surface are unlikely to become the starting point of crack generation.

  The inner layer wiring pattern only needs to be buried in at least the lower resin insulation layer, but may be buried in both the lower resin insulation layer and the upper resin insulation layer. In the case of the latter configuration, even if the inner layer wiring pattern is fine, it is difficult for the side layer to fall or peel off, and sufficient adhesion can be imparted to the resin insulating layer. In the inner layer wiring pattern, a portion embedded in the upper resin insulating layer is defined as a top surface conductor portion, and a portion embedded in the lower resin insulating layer is defined as a bottom surface conductor portion. In this case, the ratio of the height of the upper surface side conductor portion and the height of the bottom surface side conductor portion is not limited, but is set within a range of, for example, 1: 9 to 8: 2. If the ratio of the height is within such a preferable range, it is possible to reliably maintain the close contact state between the inner wiring pattern and the upper and lower resin insulating layers. Specifically, the height of the bottom-side conductor portion is preferably 5 μm or more.

  In the barrier layer forming step in the manufacturing method, a barrier layer is formed on the lower resin insulating layer. In the barrier layer, an opening can be easily formed with a laser in the groove forming process, it is not affected by a chemical used in the filling process, and it can be easily removed from the resin insulating layer in the barrier layer removing process, etc. Nature is required. In addition, it is preferable that a conductive material such as metal plating hardly adheres. Any material having these properties can be selected as a material for forming the barrier layer regardless of resin, metal, or ceramic. Among them, it is preferable to select a resin material that is relatively inexpensive, excellent in laser processability, and easy to remove. For example, when metal plating is selected in the previous step, it is preferable to form a resin barrier layer made of a resin material that is insoluble or hardly soluble in a plating solution for forming a metal plating material. Here, specific examples of the material for forming the barrier layer include a resin film represented by a dry film photoresist, for example. You may form a barrier layer by sticking such a resin film on a lower layer side resin insulation layer. It is good also as a barrier layer by exposing the whole surface after sticking a dry film photoresist.

  The thickness of the barrier layer is not particularly limited and is arbitrary, but is set to 5 μm or more and 30 μm or less, for example. This is because if the thickness of the barrier layer is less than 5 μm, there is a possibility that some strictness may be required in the operation of removing the conductive material during pattern formation. This is because if the thickness of the barrier layer is more than 30 μm, the filling process may take a long time due to the increased depth of the groove and the opening. The sum of the depth of the groove and the thickness of the barrier layer is not particularly limited and is arbitrary, but is set to, for example, 10 μm or more and 60 μm or less. If this sum is less than 10 μm, the barrier layer must be thinly formed, and there is a risk that somewhat strictness may be required in the operation of removing the conductive material during pattern formation. This is because if the sum exceeds 60 μm, the filling process may take time due to the increased depth of the groove and the opening. It should be noted that the magnitude relationship between the depth of the groove and the thickness of the barrier layer does not matter, but the depth of the groove is preferably set larger than the thickness of the barrier layer.

  In the groove forming step, the barrier layer and the lower resin insulating layer are simultaneously laser processed. By this laser processing, an opening penetrating the barrier layer is formed, and a groove for forming an inner layer wiring pattern communicating with the opening is formed in the lower resin insulating layer. The advantage of this step is that the opening and the groove do not shift because the barrier layer and the lower resin insulating layer are integrated. Further, the number of man-hours can be reduced as compared with the case where laser processing is individually performed on the barrier layer and the lower resin insulating layer.

  In the filling step, the trench and the opening are filled with a conductive material to be the inner layer wiring pattern. In this case, it is preferable to select a metal plating material as the conductive material and fill the groove and the opening with the metal plating material. In this case, the metal plating material is preferably a copper plating material, more preferably an electroless copper plating material and an electrolytic copper plating material. For example, a conductive metal paste or the like may be selected as the conductive material other than the metal plating material.

  A concave portion may be formed on the upper surface of the conductive material at the time after the filling step. In this case, it is preferable that the depth of the concave portion is equal to or less than the thickness of the barrier layer. If the depth of the recess is set within such a range, the conductive material to be the inner layer wiring pattern can be filled without excess and deficiency, and it becomes easier to obtain an inner layer wiring pattern having a suitable shape. .

  In the barrier layer removing step, the barrier layer is selectively removed after the filling step. That is, the barrier layer is removed so as to leave the lower resin insulating layer and the necessary conductive material. For example, when the barrier layer is a resin barrier layer, the lower resin insulating layer and the conductive material may be selectively removed using an alkaline solution that does not dissolve the conductive material. In the embedding step, an upper resin insulating layer is formed on the lower resin insulating layer, and an inner wiring pattern is embedded between the lower resin insulating layer and the upper resin insulating layer.

  Here, after the barrier layer removing step and before the embedding step, a shape adjusting step of adjusting the shape by removing an excess portion of the conductive material by wet etching to form an inner layer wiring pattern may be further performed. In the shape adjustment step, the shape may be adjusted by removing an excess portion of the conductive material by dry etching, or the shape may be adjusted by removing the excess portion by mechanical polishing.

1 is a schematic sectional view showing a build-up multilayer wiring board according to an embodiment of the present invention. The expanded sectional view which similarly shows the inner layer wiring pattern in a multilayer wiring board. The schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly.

  Hereinafter, a method for manufacturing a multilayer wiring board K1 according to an embodiment of the present invention will be described in detail with reference to FIGS.

  As shown in FIG. 1, the multilayer wiring board K1 of the present embodiment is a so-called buildup multilayer wiring board having buildup layers BU1 and BU2 on both front and back surfaces. The multilayer wiring board K1 includes a substrate body 20 having a substrate main surface 32a and a substrate back surface 33a. The core substrate 1 that forms part of the substrate body 20 has a flat plate shape having a front surface 2 and a back surface 3. A resin insulating layer 12 is formed on the front surface 2 side of the core substrate 1, and a resin insulating layer 13 is formed on the back surface 3 side.

  The build-up layer BU1 disposed on the surface 2 side of the core substrate 1 has a structure in which resin insulating layers 16 and 30 and conductor layers (inner layer wiring patterns 10 and 28, outer layer wiring pattern 34) are alternately stacked. ing. A via hole forming hole 12 a is formed in the resin insulating layer 12, and a filled via conductor 14 that connects the inner wiring pattern 10 and the core substrate side conductor layer 4 is formed therein. A via hole forming hole 18 is formed in the resin insulating layer 16, and a filled via conductor 26 is formed in the resin insulating layer 16 to conduct between the inner layer wiring patterns 10 and 28.

  The build-up layer BU2 disposed on the back surface 3 side of the core substrate 1 has a structure in which resin insulating layers 17 and 31 and conductor layers (inner layer wiring patterns 11 and 29, outer layer wiring pattern 35) are alternately stacked. ing. A via-hole forming hole 13 a is formed in the resin insulating layer 13, and a filled via conductor 15 that connects the inner wiring pattern 11 and the core substrate side conductor layer 5 is formed therein. A via hole forming hole 19 is formed in the resin insulating layer 17, and a filled via conductor 27 is formed in the resin insulating layer 17 to conduct between the inner layer wiring patterns 11 and 29.

  The solder resist 32 entirely covers the outer layer wiring pattern 34 formed on the resin insulating layer 30. The solder resist 32 has openings 36 at predetermined locations, and these openings 36 expose a predetermined portion (that is, the first main surface side land 34a) in the outer layer wiring pattern 34 to the first main surface 32a side. ing. The solder resist 33 entirely covers the outer layer wiring pattern 35 formed on the resin insulating layer 31. The solder resist 33 has openings 37 at predetermined locations, and these openings 37 expose a predetermined portion (that is, the second main surface side land 35a) in the outer layer wiring pattern 35 to the second main surface 33a side. ing.

  A solder bump 38 protruding higher than the first main surface 32a is formed on the first main surface side land 34a. On these solder bumps 38, electronic components such as an IC chip (not shown) can be joined via solder. On the other hand, the second main surface side land 35 is electrically connected to a printed wiring board such as a mother board (not shown).

  As shown in FIG. 1, a through hole is provided inside the wiring board K1. The through hole of this embodiment deposits a cylindrical through hole conductor 7 on the inner wall surface of the through hole forming hole 6 that penetrates the core substrate 1 and the resin insulating layers 12 and 13, and the cavity of the through hole conductor 7. The portion is filled with the filling resin 9. The through-hole conductor 7 of the through-hole provides conduction between the conductor portion in the build-up layer BU1 on the front surface 2 side of the core substrate 1 and the conductor portion in the build-up layer BU2 on the back surface 3 side of the core substrate 1. It is illustrated.

  As shown in FIGS. 1 and 2, the inner layer wiring patterns 28 and 29 in the wiring board K <b> 1 of the present embodiment extend along the surface direction of the board body 20 and are formed of a copper plating material 42. More specifically, the inner layer wiring patterns 28 and 29 have a layer structure in which an electrolytic copper plating layer is laminated on an electroless copper plating layer. The inner layer wiring patterns 28 and 29 are fine inner layer wiring patterns whose line width and line interval are both 15 μm or less. In the build-up layer BU1 on the surface 2 side, the upper resin insulating layer 30 is laminated on the lower resin insulating layer 16 so as to cover the inner wiring pattern layer 28. In the build-up layer BU2 on the back surface 3 side, the upper resin insulating layer 31 is laminated on the lower resin insulating layer 17 so as to cover the wiring pattern layer 29. In this embodiment, these resin insulating layers 16, 17, 30, and 31 are formed using a thermosetting epoxy resin having a CTE of 50 ppm / ° C. or less.

  As shown in FIG. 2, the inner layer wiring pattern 28 is arranged so as to be sandwiched between two resin insulating layers 16 and 30 adjacent on the surface 2 side. The upper resin insulating layer 30 is in contact with the upper surface 43 side of the inner wiring pattern 28, and the lower resin insulating layer 16 is in contact with the lower surface 44 side of the inner wiring pattern 28. The inner layer wiring pattern 28 is buried in both the resin insulating layers 16 and 30.

  The inner layer wiring pattern 29 is arranged so as to be sandwiched between two resin insulating layers 17 and 31 adjacent on the back surface 3 side. The upper resin insulating layer 31 is in contact with the upper surface 43 side of the inner wiring pattern 29, and the lower resin insulating layer 17 is in contact with the lower surface 44 side of the inner wiring pattern 29. The inner layer wiring pattern 29 is buried in both the resin insulating layers 17 and 31.

  As shown in FIG. 2 and the like, when the wiring board K1 is cut in the stacking direction, the inner layer wiring patterns 28 and 29 appearing on the cut surface have a substantially hexagonal cross section in this embodiment. For convenience of explanation, in the inner layer wiring patterns 28 and 29, the portion embedded in the upper resin insulating layers 30 and 31 is the upper surface side conductor portion 45, and the portion embedded in the lower resin insulating layers 16 and 17 is the bottom surface side conductor. Let it be a portion 46. The upper surface side conductor portion 45 has a tapered cross-sectional shape that becomes narrower as the distance from the core substrate 1 increases. The bottom-side conductor portion 46 has an inversely tapered cross-sectional shape that becomes narrower as it approaches the core substrate 1. In the same plane as the virtual plane 53 formed at the boundary between the lower layer side resin insulation layer 16 and the upper layer side resin insulation layer 30, the maximum width portion 54 (about 15 μm in this embodiment) of the inner layer wiring pattern 28 is formed. Has been placed. That is, in the present embodiment, the maximum width portion 54 is not disposed at the pattern upper end 51 or the pattern lower end 52 but is disposed at a position between them. Further, the cut surfaces in the stacking direction of the inner layer wiring patterns 28 and 29 have a shape that does not have an acute angle or a right angle, and all the angles are obtuse. In particular, the two corners positioned at the pattern upper end 51 are rounded obtuse angles.

  In the cut surfaces of the inner layer wiring patterns 28 and 29, the width W1 of the pattern upper end 51 is slightly larger than the width W2 of the pattern lower end 52. When the width W1 of the pattern upper end 51 is used as a reference, the size of the width W3 of the maximum width portion 54 is about 1.2 to 1.3 times that. Incidentally, the ratio (W3: W1) between the width W3 and the width W1 is set to about 10: 7 to 10: 8, and the ratio (W3: W2) between the width W3 and the width W2 is about 10: 5 to 10: 6. Is set to

  In the inner layer wiring patterns 28 and 29, the height of the upper surface side conductor portion 45 is “h11”, and the height of the bottom surface side conductor portion 46 is “h12”. In the present embodiment, the height h11 is about 5 μm, and the height h12 is about 15 μm. Therefore, the height ratio between the two (h11: h12) is 5:15, and is set to be within a preferable range (1: 9 to 8: 2).

  Next, the manufacturing method of the wiring board K1 of this embodiment is demonstrated based on FIGS.

  First, a core substrate 1 mainly composed of a bismaleimide triazine (BT) resin is prepared. Copper foil is attached in advance to the front surface 2 and the back surface 3 of the core substrate 1. The copper foil of the core substrate 1 is patterned by a conventionally known method (here, subtractive method) to form the core substrate side conductor layers 4 and 5 on the front surface 2 and the back surface 3. Next, the resin insulating layers 12 and 13 are formed on the front surface 2 and the back surface 3 of the core substrate 1, and via hole forming holes 12 a and 13 a are further formed. Here, the resin insulating layers 12 and 13 are formed using a thermosetting resin material for forming a buildup layer (so-called buildup material). In this embodiment, an insulating film in which an inorganic filler is dispersed in an epoxy resin is used as a buildup material. Next, after the through hole forming hole 6 penetrating the core substrate 1 and the resin insulating layers 12 and 13 is formed, electroless copper plating and electrolytic copper plating are performed to form the through hole conductor 7 and the filled via conductors 14 and 15. To do. Next, after filling the cavity of the through-hole conductor 7 with the paste of the filling resin 9, electrolytic copper plating is performed to further form a copper plating film on the copper plating film. At this time, both end surfaces of the filling resin 9 are covered with the cover platings 10a and 11a. Subsequently, these two copper plating films are etched by a conventionally known subtractive method to form inner wiring patterns 10 and 11 as shown in FIG. These inner layer wiring patterns 10 and 11 become the first conductor layer in the build-up layers BU1 and BU2.

  Next, as shown in FIG. 4, the epoxy resin-based insulating film is pasted on the resin insulating layer 12 on the core substrate 1 side and the first inner wiring pattern 10, and the first layer resin is bonded. An insulating layer 16 is formed. Similarly, the first insulating resin layer 17 is formed by pasting the insulating film on the resin insulating layer 13 on the core substrate 1 side and the first inner wiring pattern 11.

  Next, a barrier layer forming step is performed to form a barrier layer 61 on the lower resin insulating layers 16 and 17 (see FIG. 5). Here, the barrier layer 61 having a thickness of about 5 μm to 10 μm is formed by exposing the entire surface after attaching a dry film photoresist.

  Next, the barrier layer 61 and the lower resin insulating layers 16 and 17 are simultaneously laser processed (groove forming step). By this laser processing, an opening 63 penetrating the barrier layer 61 is formed, and the inner layer wiring pattern forming groove 62 and the via hole forming holes 18 and 19 communicating with the opening 63 are formed in the lower resin insulating layers 16 and 17. Form (see FIG. 6). In this embodiment, since the barrier layer 61 is made of a resin material, the opening 63 can be formed relatively easily by laser processing. In this case, since it is necessary to make processing depths different between the via hole forming holes 18 and 19 and the groove 62, for example, the laser output, the number of shots, the irradiation time, and the like are changed for irradiation. In FIG. 8, the depth of the groove 62 is indicated by D2. Incidentally, the sum of the depth D2 of the groove 62 and the thickness T2 of the barrier layer 61 is about 10 μm to 25 μm.

  Next, a desmear process is performed to remove smears on the inner wall surfaces of the openings 63, the via hole forming holes 18 and 19 and the grooves 62, and the entire surfaces of the resin insulating layers 16 and 17 including these inner wall surfaces are roughened. (Surface roughness Ra is set to about 2 μm).

  Next, a filling step is performed to fill the grooves 62 and the openings 63 with the copper plating material 42 as a conductive material, thereby forming conductive portions to be the inner layer wiring patterns 28 and 29. Specifically, after a plating catalyst is applied in advance, an electroless copper plating layer having a thickness of about 0.5 μm is formed on the entire surface by electroless copper plating. Further, an electrolytic copper plating layer having a thickness of about 15 μm to 20 μm is formed on the entire surface by electrolytic copper plating (see FIG. 7). The copper plating material 42 is formed so as to protrude at least above the groove 62. Further, at this time, a recess 69 may be formed on the upper surface of the copper plating material 42 located in the groove 62 (see FIG. 8). However, in that case, the depth D1 of the recess 69 is set to be equal to or less than the thickness T2 of the barrier layer 61.

  Next, the copper plating material 42 mainly etched on the surface of the barrier layer 61 is removed by etching the copper plating material 42 using a predetermined etching solution for dissolving copper. As a result, filled via conductors 26 and 27 and inner layer wiring patterns 28 and 29 are formed (see FIGS. 8 to 10). FIG. 8 shows the state of the copper plating material 42 when etching is performed without excess or deficiency. At this time, the height of the surface of the copper plating material 42 is substantially the same as the height of the surface of the barrier layer 61, and the copper plating material 42 is not placed on the surface of the barrier layer 61. FIG. 9 shows the state of the copper plating material 42 when the etching is excessive. In this figure, the height of the surface of the copper plating material 42 is lower than the height of the surface of the barrier layer 61. However, as long as the difference in height is smaller than the thickness T2 of the barrier layer 61, there is no particular problem even in such excessive etching. FIG. 10 shows the state of the copper plating material 42 when etching is insufficient. In this figure, the surplus plating portion 42a is placed around the groove 62 on the surface of the barrier layer 61, but the barrier layer 61 is exposed to the extent that it can be removed in a later step. Therefore, no problem arises even if such etching is insufficient.

  Next, a barrier layer removing step is performed to selectively remove the barrier layer 61 from the resin insulating layers 16 and 17 (see FIGS. 11 and 12). Specifically, the dry film photoresist is stripped using a dedicated stripping solution (for example, an alkaline aqueous solution). At this time, the lower resin insulating layers 16 and 17 and the necessary copper plating material 42 are left undissolved.

  Next, a shape adjusting step is performed to remove an excess portion of the copper plating material 42, that is, in the present embodiment, a right angle or acute angle portion in the pattern upper end 51 exposed from the lower resin insulating layers 16 and 17. Adjust the shape. Specifically, quick etching is performed using an etchant that dissolves copper, and the copper plating material 42 is partially dissolved and removed. The excess plating part 42a shown in FIG. 10 is also removed through this process. As a result, inner layer wiring patterns 28 and 29 having a suitable cut surface shape are formed (see FIG. 13). As a result of such shape adjustment, in the inner layer wiring patterns 28 and 29, the maximum width portion 54 is disposed between the pattern upper end 51 and the pattern lower end 52. In addition, although the shape adjustment process is performed in this embodiment, this process can be omitted if unnecessary.

  Next, an embedding process is performed, and the above-mentioned epoxy resin insulating film is pasted on the lower resin insulation layers 16 and 17 to form the upper resin insulation layers 30 and 31, respectively. As a result, the inner wiring pattern 28 is embedded between the lower resin insulating layer 16 and the upper resin insulating layer 30, and the inner wiring pattern 29 is embedded between the lower resin insulating layer 17 and the upper resin insulating layer 31. (See FIG. 14). In order to improve the adhesion between the inner layer wiring patterns 28 and 29 and the upper surface side resin insulation layers 30 and 31, surface roughening treatment may be performed on the inner layer wiring patterns 28 and 29 before the embedding process. The surface roughening treatment is preferably performed after the shape adjustment step.

  Then, after forming the outer layer wiring patterns 34 and 35 by the semi-additive method, solder resists 32 and 33 each having a thickness of 25 μm are provided on the second resin insulating layers 30 and 31, respectively. Furthermore, after applying nickel-gold plating on the first main surface side land 34a exposed through the opening 36, a solder bump 38 is formed, and the second main surface side land 35a exposed through the opening 37 is formed. Is subjected to nickel-gold plating. As a result, the multilayer wiring board K1 having the build-up layers BU1 and BU2 on both the front and back surfaces as shown in FIG. 1 is completed.

Therefore, according to the present embodiment, the following effects can be obtained.
(1) In the manufacturing method of the multilayer wiring board K1 of the present embodiment, the barrier layer 61 is formed in advance on the lower resin insulating layers 16 and 17, and both layers are simultaneously laser processed, so that the opening 63 and the groove are formed. 62 is formed. Next, after filling the groove 62 and the opening 63 with the copper plating material 42 which is a conductive material, the barrier layer 61 is selectively removed. At this time, the copper plating material 42 is not formed directly on the lower resin insulation layers 16 and 17 but on the barrier layer 61. Therefore, by removing the barrier layer 61, the excess copper plating material 42 can be removed relatively easily without excess or deficiency. As described above, according to this manufacturing method, strictness is not required for the removal work of the copper plating material 42 at the time of pattern formation, and the risk of occurrence of wiring breakage or short circuit is low. In spite of this, the multilayer wiring board K1 having the inner layer wiring patterns 28 and 29 having a suitable shape can be manufactured relatively easily and with a high yield.

  (2) In the barrier layer forming step in this manufacturing method, a dry film photoresist made of a resin material is formed as the barrier layer 61 on the lower resin insulating layers 16 and 17. In this case, the opening 63 can be easily formed with a laser in the groove forming step. In addition, according to this manufacturing method, the copper plating material forming plating solution used in the filling step is not affected by the plating solution and is easily removed from the lower resin insulating layers 16 and 17 in the barrier layer removing step. be able to. In addition, since it is relatively inexpensive, cost reduction can be achieved.

  (3) In this manufacturing method, the thickness T2 of the barrier layer 61 is set within a preferable range of 5 μm or more and 30 μm or less, and the sum of the depth D2 of the groove 62 and the thickness T2 of the barrier layer 61 is determined. It is set within a suitable range of 10 μm or more and 60 μm or less. From the above, the time required for the filling process can be shortened. Further, strictness is not required for the operation of removing the copper plating material 42 during pattern formation.

  (4) In this manufacturing method, after the barrier layer removing step and before the embedding step, an excessive portion of the copper plating material 42 is removed by wet etching to adjust the shape, and the inner wiring pattern 28 having a suitable cut surface shape is obtained. , 29 are formed. That is, through this step, the maximum width portion 54 on the cut surface in the stacking direction of the inner layer wiring patterns 28 and 29 is arranged at a position between them instead of the positions of the pattern upper end 51 and the pattern lower end 52. For this reason, the pattern upper end 51 and the pattern lower end 52 no longer have a right-angle or acute-angle portion, but instead have an obtuse-angle portion that is unlikely to become a starting point of crack generation. In particular, the upper end 51 of the pattern has a rounded obtuse angle. Therefore, the occurrence of cracks in the resin insulating layers 16, 17, 30, and 31 is suppressed, and the reliability sufficient for the multilayer wiring board K1 can be improved. Further, according to the configuration of this embodiment, for example, even when the resin insulating layers 16, 17, 30, and 31 having a hard and brittle property are employed in order to pursue low thermal expansion, the generation of cracks is prevented. Therefore, it is possible to achieve both low thermal expansion and high reliability.

  (5) In the multilayer wiring board K1 of this embodiment, since the inner layer wiring patterns 28 and 29 are buried in both the lower layer side resin insulation layers 16 and 17 and the upper layer side resin insulation layers 30 and 31, A suitable close contact state is maintained. Therefore, even if it is the fine inner layer wiring patterns 28 and 29, it is difficult to cause a lateral fall or peeling, and sufficient adhesion can be imparted. In addition, since the lower side of the inner layer wiring patterns 28 and 29 is buried in the lower layer side resin insulation layers 16 and 17, the surface of the upper surface side resin insulation layers 30 and 31 is less likely to be uneven. Therefore, there is an advantage that the thickness variation of the upper surface side resin insulation layers 30 and 31 can be reduced. Therefore, the flatness of the IC chip mounting surface can be improved.

  In addition, you may change embodiment of this invention as follows.

  In the multilayer wiring board K1 of the above embodiment, the cut surfaces in the stacking direction of the inner layer wiring patterns 28 and 29 have a substantially hexagonal shape, but may be other than a substantially hexagonal shape (for example, a substantially pentagonal shape). Good. For example, such an inner layer wiring pattern can be formed by setting etching conditions stronger than in the embodiment and etching the upper surface side conductor portion 45 more.

  In the above embodiment, the present invention is embodied in the multilayer wiring substrate K1 having the core substrate 1, but may be embodied in a multilayer wiring substrate having no so-called core substrate.

  In the above embodiment, the protrusions 46 are provided to fill the grooves 51 when the inner layer wiring patterns 28 and 29 are fine patterns having a maximum width of 20 μm or less. However, even when the maximum width is more than 20 μm, A similar configuration may be adopted.

  In the above embodiment, the inner layer wiring patterns 28 and 29 are exemplified such that the height is h11 <h12. However, the height may be h11> h12, for example. However, even in this case, the height ratio (h11: h12) is preferably set within a preferable range of 1: 9 to 8: 2.

  In the above-described embodiment, an example in which the inner layer wiring pattern 28 is disposed between two adjacent resin insulating layers 16 and 30 of the same type has been described. However, for example, a similar structure is provided between two different types of resin insulating layers adjacent to each other. An inner layer wiring pattern may be arranged.

  In the filling process of the above embodiment, the groove 62 and the opening 63 are filled with the copper plating material 42 by performing the electrolytic copper plating after the electroless copper plating. Instead, only the electroless copper plating is performed. It is good.

  In the above embodiment, a dry film photoresist is used as the barrier layer 61, but the present invention is not limited to this, and for example, a resin barrier layer formed by applying and curing a liquid resin material may be used.

Next, the technical ideas grasped by the embodiment described above are listed below.
(1) In means 1, the inner layer wiring pattern is made of a metal plating material.
(2) In means 1, the inner layer wiring pattern is made of a copper plating material.
(3) In means 1 or ideas 1 or 2, the height of the upper conductor portion embedded in the upper resin insulation layer and the bottom surface buried in the lower resin insulation layer in the inner wiring pattern The ratio with the height of the side conductor portion is in the range of 1: 9 to 8: 2.
(4) In any one of means 1 and ideas 1 to 3, the inner layer wiring pattern is a fine pattern having a maximum width of 20 μm or less.
(5) In means 1, any one of thoughts 1 to 4, the lower resin insulation layer and the upper resin insulation layer are made of the same type of resin insulation layer having thermosetting properties.
(6) In the method 1, any one of the thoughts 1 to 4, the lower resin insulation layer and the upper resin insulation layer have the same thermal expansion coefficient and a thermosetting coefficient of 50 ppm / ° C. or less. It consists of a resin insulation layer.
(7) In means 1 or any one of ideas 1 to 6, the multilayer wiring board is a build-up multilayer wiring board having a build-up layer formed by alternately laminating resin insulating layers and conductor layers. .
(8) In any one of means 1 and ideas 1 to 7, a via hole forming hole is formed in the resin insulating layer in contact with the bottom surface side, and a filled via conductor is formed in the via hole forming hole. The height of the bottom-side conductor portion is set to be smaller than the depth of the via hole forming hole.
(9) In means 1, any one of ideas 1 to 8, the multilayer wiring board has a core substrate.
(10) In the means 1 and any one of the ideas 1 to 8, the multilayer wiring board does not have a core board.

DESCRIPTION OF SYMBOLS 16, 17 ... Lower layer side resin insulation layer 20 ... Board | substrate body 28, 29 ... Inner layer wiring pattern 30, 31 ... Upper layer side resin insulation layer 32a ... Substrate main surface 33a ... Substrate back surface 42 ... Metal plating material 43 ... (conductive material) Upper surface 44 of inner layer wiring pattern ... Bottom surface of inner layer wiring pattern 61 ... Barrier layer 62 ... Groove for forming inner layer wiring pattern 69 ... Recess D1 ... Depth of recess D2 ... Depth of groove K1 ... Multilayer wiring board T2 ... Barrier layer thickness

Claims (6)

A substrate body having a substrate main surface and a substrate back surface formed by laminating a plurality of resin insulation layers, an inner layer wiring pattern extending along a surface direction of the substrate body, and a lower layer side resin insulation in contact with the bottom surface side of the inner layer wiring pattern In a method for manufacturing a multilayer wiring board comprising a layer and an upper resin insulating layer adjacent to the lower resin insulating layer and in contact with the upper surface side of the inner wiring pattern,
A barrier layer forming step of forming a barrier layer on the lower resin insulating layer;
The barrier layer and the lower resin insulation layer are simultaneously laser processed to form an opening penetrating the barrier layer, and a groove for forming an inner wiring pattern that communicates with the opening is formed in the lower resin insulation layer A groove forming step,
A filling step of filling the groove and the opening with a conductive material to be the inner layer wiring pattern;
A barrier layer removing step of selectively removing the barrier layer after the filling step;
Forming an upper resin insulating layer on the lower resin insulating layer and embedding the inner wiring pattern between the lower resin insulating layer and the upper resin insulating layer. Method.   In the filling step, the groove and the opening are filled with a metal plating material that is the conductive material, and in the barrier layer forming step, a resin made of a resin material that is insoluble or hardly soluble in the plating solution for forming the metal plating material. The method for manufacturing a multilayer wiring board according to claim 1, wherein a barrier layer is formed.   After the barrier layer removing step and before the embedding step, the method further includes a shape adjusting step of adjusting the shape by removing excess portions of the conductive material by wet etching to form the inner layer wiring pattern. A method for manufacturing a multilayer wiring board according to claim 1 or 2.   4. The multilayer wiring board according to claim 1, wherein a depth of a concave portion generated on an upper surface of the conductive material at a time after the filling step is set to be equal to or less than a thickness of the barrier layer. Production method.   5. The method of manufacturing a multilayer wiring board according to claim 1, wherein the barrier layer has a thickness of 5 μm or more and 30 μm or less.   6. The method for manufacturing a multilayer wiring board according to claim 1, wherein the sum of the depth of the groove and the thickness of the barrier layer is 10 μm or more and 60 μm or less.

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