JP2013062292A - Multilayer wiring board and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer wiring board which makes cracks less likely to be caused in a resin insulation layer and is excellent in reliability.SOLUTION: A multilayer wiring board includes: a board body; an inner layer wiring pattern 28; a lower layer side resin insulation layer 16; and an upper layer side resin insulation layer 30. The inner layer wiring pattern 28 extends along the surface direction of the board body. The lower layer side resin insulation layer 16 contacts with the bottom surface 44 side of the inner layer wiring pattern 28. The upper layer side resin insulation layer 30 is located adjacent to the lower layer side resin insulation layer 16 and contacts with an upper surface 43 side of the inner layer wiring pattern 28. The inner layer wiring pattern 28 is buried in both the lower layer side resin insulation layer 16 and the upper layer side resin insulation layer 30. The largest width part 54 of a cross section surface, when viewed in the lamination direction of the inner layer wiring pattern 28, is disposed at a position between a pattern upper end 51 and a pattern lower end 52.

Description

  The present invention relates to a multilayer wiring board and a method for manufacturing the same, and more particularly to a multilayer wiring board having a structure in which a fine inner layer wiring pattern made of a plating layer is disposed between adjacent resin insulating layers and a method for manufacturing the same.

  In recent years, with the miniaturization and high performance of electronic devices, high-density mounting of electronic components is required. In achieving such high-density mounting, a multilayer circuit board technology for mounting an IC chip is regarded as important. As a concrete example using the multilayer technology, a multilayer wiring board (so-called build-up) having a build-up layer in which a resin insulating layer and a conductor layer are alternately laminated on one side or both sides of a core board provided with a through-hole portion or the like. Multilayer wiring boards) are well known.

  Conventionally, formation of such a fine inner layer wiring pattern is mainly performed by a semi-additive method. In the semi-additive method, via holes are formed in the lower resin insulation layer, electroless copper plating is applied to the entire surface of the resin insulation layer, plating resist is formed, electrolytic copper plating, unnecessary plating resist, and removal of the electroless copper plating layer are sequentially performed. The process of performing is employ | adopted (for example, refer patent document 1). As a result, an inner layer wiring pattern made of a copper plating layer is formed on the lower resin insulating layer.

  Apart from this, recently, a technique called a trench filling method has been proposed (see, for example, Patent Documents 2 to 4). In the trench filling method, a process of sequentially forming a groove (trench) in a lower resin insulating layer, filling a groove by electroless copper plating, and removing excess copper plating protruding from the groove is employed. As a result, an inner layer wiring pattern made of copper plating buried in the groove is formed.

JP 2000-188460 A JP-A-11-87276 JP 2007-84891 A JP 2009-132982 A

  By the way, the inner layer wiring pattern formed by the semi-additive method usually has a rectangular cut surface in the stacking direction. In addition, depending on the method and conditions for wiring drawing of the plating resist, there may be a reverse trapezoidal cut surface having a taper. Furthermore, depending on the etching conditions after removing the plating resist, the cut surface may be a semi-elliptical or triangular shape. On the other hand, in the trench filling method, although depending on the shape of the groove at the time of wiring drawing, since drawing is usually performed with a laser, a cut surface having an inverted trapezoidal shape having a taper is obtained. Further, depending on the laser irradiation conditions, a rectangular cut surface without a taper is obtained.

  As described above, in the conventional multilayer wiring board, in any case, the upper end of the pattern or the lower end of the pattern is the widest portion on the cut surface in the stacking direction of the inner layer wiring pattern. For this reason, there are right-angled and acute-angled portions on the cut surface in the stacking direction of the inner wiring pattern. Therefore, such right-angled or acute-angled portions play a role like a wedge, and cracks are likely to occur in the resin insulating layer starting from there. Therefore, sufficient reliability cannot be imparted to the multilayer wiring board. In particular, in the case of the semi-additive method, since the resin insulating layer plays a role of filling the unevenness of the inner wiring pattern, if the cutting surface in the stacking direction includes a right angle or an acute angle, the resin insulating layer is locally bent greatly. This also causes cracks.

  Conventionally, even if it is a pattern cut surface shape in which cracks are likely to occur, reliability is imparted to the multilayer wiring board by taking measures such as using a highly flexible resin insulating material. However, in the future, there is a possibility of shifting to a resin insulating layer having a hard and brittle property in order to pursue low thermal expansion. In such a case, it is expected that it is difficult to achieve both low thermal expansion and high reliability.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a multilayer wiring board that is less prone to cracks in a resin insulating layer and has excellent reliability.

  As means for solving the above problems (means 1), a plurality of resin insulation layers are laminated, a substrate body having a substrate main surface and a substrate back surface, and an inner layer wiring extending along the surface direction of the substrate body A lower layer side resin insulation layer in contact with the bottom surface side of the inner layer wiring pattern, and an upper layer side resin insulation layer adjacent to the lower layer side resin insulation layer and in contact with the upper surface side of the inner layer wiring pattern. In a multilayer wiring board in which a pattern is embedded in both the lower resin insulating layer and the upper resin insulating layer, the maximum width portion on the cut surface in the stacking direction of the inner wiring pattern is between the pattern upper end and the pattern lower end. There is a multilayer wiring board characterized by being arranged at the position of

  Therefore, according to the invention according to the above means, the maximum width portion of the inner-layer wiring pattern on the cut surface in the stacking direction is arranged not at the upper end of the pattern or at the lower end of the pattern but at a position between them. For this reason, there are no right-angle or acute-angle portions at the upper end or lower end of the pattern, and instead, there is an obtuse-angle portion that is unlikely to be a starting point of crack generation. Therefore, the generation of cracks in the resin insulating layer is suppressed, and the reliability sufficient for the multilayer wiring board can be improved. In addition, according to the present invention, for example, even when a resin insulating layer having a hard and brittle property is employed in order to pursue low thermal expansion, the generation of cracks is prevented, so that low thermal expansion and high reliability are achieved. It is possible to achieve compatibility with sex.

  In the multilayer wiring board, the plurality of resin insulating layers constituting the substrate body are formed using, for example, a thermosetting resin. Preferable examples of the thermosetting resin include EP resin (epoxy resin), PI resin (polyimide resin), BT resin (bismaleimide-triazine resin), phenol resin, xylene resin, polyester resin, silicon resin and the like. . Among these, it is preferable to select an EP resin, a PI resin, or a BT resin. For example, as the epoxy resin, a so-called BP (bisphenol) type, PN (phenol novolac) type, or CN (cresol novolac) type may be used. In particular, BP type is mainly used, and BPA (bisphenol A) type and BPF (bisphenol F) type are the best. Note that the plurality of resin insulating layers may be formed using a photocurable resin or the like.

  An inner layer wiring pattern is disposed between a plurality of adjacent resin insulation layers. The upper resin insulating layer in contact with the upper surface side of the inner wiring pattern and the lower resin insulating layer in contact with the bottom surface side may be formed using the same type of resin, or using different types of resins. It may be formed. As a suitable example of the lower layer side resin insulation layer and the upper layer side resin insulation layer, for example, the same kind of resin having a low coefficient of thermal expansion (CTE) (for example, 50 ppm / ° C. or less) and having thermosetting properties is used. Are formed. The inner layer wiring pattern is preferably a fine pattern having a maximum width of 20 μm or less, particularly a fine pattern having a maximum width of 10 μm or less.

  The inner layer wiring pattern extends along the surface direction of the substrate body, and is formed using a conductive material. Preferable examples of the conductive material include a plating material. The plating material is not particularly limited, and copper plating, nickel plating, gold plating, silver plating, aluminum plating, tin plating, cobalt plating, titanium plating, and the like can be employed. Considering conductivity, cost, workability, etc., the inner wiring pattern is preferably made of a copper plating material, and more preferably a structure in which an electrolytic copper plating layer is formed on an electroless copper plating layer. .

  When the inner layer wiring pattern is cut in the stacking direction, the maximum width portion on the cut surface is disposed at a position between the pattern upper end and the pattern lower end. That is, the maximum width portion is not arranged at the upper end of the pattern or the lower end of the pattern. The magnitude relationship between the width at the upper end of the pattern and the width at the lower end of the pattern is not particularly limited. Therefore, the former may be larger than the latter, the latter may be larger than the former, or both may be equal.

  Here, the maximum width portion is arranged at an arbitrary position between the upper end of the pattern and the lower end of the pattern, for example, the same as the virtual plane formed at the boundary between the lower resin insulating layer and the upper resin insulating layer. Arranged in a plane. The maximum width portion may be arranged at a position between the virtual plane and the upper end of the pattern.

  For example, the size (width) of the maximum width portion is preferably 1.1 times or more and 1.5 times or less that of the pattern upper end and pattern lower end having a relatively large width. The reason is that if it is less than 1.1 times, a right-angled or acute-angled portion tends to occur at the upper end of the pattern. Conversely, if it exceeds 1.5 times, there is a possibility that a right-angle or acute-angle portion may occur in the maximum width portion.

  The cut surface in the stacking direction of the inner layer wiring pattern preferably has a shape that does not have an acute angle or a right angle. In other words, all the angles in the cut surface are preferably obtuse. This is because all the corners on the cut surface are less likely to be the starting point of crack generation, and the generation of cracks in the resin insulating layer can be effectively suppressed. Moreover, it is preferable that the corner | angular part in a cut surface is round regardless of an acute angle, a right angle, and an obtuse angle. Also in this case, the corners are unlikely to become the starting point of cracks. Most preferably, the corner portion of the cut surface has a rounded obtuse angle.

  On the cut surface in the stacking direction of the inner layer wiring pattern, the ratio between the width of the maximum width portion and the width of the upper end of the pattern is not limited, but may be set within a range of 10: 1 to 10: 9, for example. Further, the ratio of the width of the maximum width portion to the width of the lower end of the pattern is not limited in the cut surface in the stacking direction of the inner layer wiring pattern, but it may be set within a range of 10: 5 to 10: 9, for example. . When the ratio of the widths is within these preferable ranges, the corners at the cut surface are unlikely to become the starting point of crack generation.

  The inner wiring pattern is preferably embedded in both the lower resin insulating layer and the upper resin insulating layer. In the case of this configuration, even if the inner layer wiring pattern is fine, it does not easily fall down or peel off, and sufficient adhesion can be imparted to the resin insulating layer. In the inner layer wiring pattern, a portion embedded in the upper resin insulating layer is defined as a top surface conductor portion, and a portion embedded in the lower resin insulating layer is defined as a bottom surface conductor portion. In this case, the ratio of the height of the upper surface side conductor portion and the height of the bottom surface side conductor portion is not limited, but is set within a range of, for example, 1: 9 to 8: 2. If the ratio of the height is within such a preferable range, it is possible to reliably maintain the close contact state between the inner wiring pattern and the upper and lower resin insulating layers. Specifically, the height of the bottom-side conductor portion is preferably 5 μm or more.

  As another means (means 2) for solving the above-mentioned problem, the multilayer wiring board manufacturing method according to means 1, wherein a groove for forming an inner layer wiring pattern is formed in the lower layer side resin insulation layer. A groove forming step, a conductive portion forming step for forming a conductive portion that fills the groove and protrudes above the groove, and adjusts the shape by removing an excess portion of the conductive portion; The shape adjustment step for forming the inner layer wiring pattern, the upper layer side resin insulating layer is formed on the lower layer side resin insulating layer, and the inner layer wiring is provided between the lower layer side resin insulating layer and the upper layer side resin insulating layer. There is a method for manufacturing a multilayer wiring board including a step of embedding a pattern.

  Therefore, according to the invention relating to the above means, after forming the groove for forming the inner layer wiring pattern in the lower resin insulating layer in the groove forming step, the conductive portion is filled and formed in the groove in the conductive portion forming step. In the subsequent shape adjustment step, the inner portion wiring pattern having a suitable cut surface shape is formed by adjusting the shape by removing the surplus portion of the conductive portion, that is, the right-angle or acute-angle portion at the upper end of the pattern. In the multilayer wiring board in which such an inner layer wiring pattern is embedded between the lower resin insulating layer and the upper resin insulating layer, the resin insulating layer is hardly cracked and has excellent reliability.

1 is a schematic sectional view showing a build-up multilayer wiring board according to an embodiment of the present invention. The expanded sectional view which similarly shows the inner layer wiring pattern in a multilayer wiring board. The schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The principal part schematic sectional drawing for demonstrating the manufacturing procedure of a multilayer wiring board similarly. The expanded sectional view which shows the inner layer wiring pattern of another embodiment. The expanded sectional view which shows the inner layer wiring pattern of another embodiment. The expanded sectional view which shows the inner layer wiring pattern of another embodiment. The expanded sectional view which shows the inner layer wiring pattern of another embodiment.

  Hereinafter, a multilayer wiring board K1 according to an embodiment of the present invention will be described in detail with reference to FIGS.

  As shown in FIG. 1, the multilayer wiring board K1 of the present embodiment is a so-called buildup multilayer wiring board having buildup layers BU1 and BU2 on both front and back surfaces. The multilayer wiring board K1 includes a substrate body 20 having a substrate main surface 32a and a substrate back surface 33a. The core substrate 1 that forms part of the substrate body 20 has a flat plate shape having a front surface 2 and a back surface 3. A resin insulating layer 12 is formed on the front surface 2 side of the core substrate 1, and a resin insulating layer 13 is formed on the back surface 3 side.

  The build-up layer BU1 disposed on the surface 2 side of the core substrate 1 has a structure in which resin insulating layers 16 and 30 and conductor layers (inner layer wiring patterns 10 and 28, outer layer wiring pattern 34) are alternately stacked. ing. A via hole forming hole 12 a is formed in the resin insulating layer 12, and a filled via conductor 14 that connects the inner wiring pattern 10 and the core substrate side conductor layer 4 is formed therein. A via hole forming hole 18 is formed in the resin insulating layer 16, and a filled via conductor 26 is formed in the resin insulating layer 16 to conduct between the inner layer wiring patterns 10 and 28.

  The build-up layer BU2 disposed on the back surface 3 side of the core substrate 1 has a structure in which resin insulating layers 17 and 31 and conductor layers (inner layer wiring patterns 11 and 29, outer layer wiring pattern 35) are alternately stacked. ing. A via-hole forming hole 13 a is formed in the resin insulating layer 13, and a filled via conductor 15 that connects the inner wiring pattern 11 and the core substrate side conductor layer 5 is formed therein. A via hole forming hole 19 is formed in the resin insulating layer 17, and a filled via conductor 27 is formed in the resin insulating layer 17 to conduct between the inner layer wiring patterns 11 and 29.

  The solder resist 32 entirely covers the outer layer wiring pattern 34 formed on the resin insulating layer 30. The solder resist 32 has openings 36 at predetermined locations, and these openings 36 expose a predetermined portion (that is, the first main surface side land 34a) in the outer layer wiring pattern 34 to the first main surface 32a side. ing. The solder resist 33 entirely covers the outer layer wiring pattern 35 formed on the resin insulating layer 31. The solder resist 33 has openings 37 at predetermined locations, and these openings 37 expose a predetermined portion (that is, the second main surface side land 35a) in the outer layer wiring pattern 35 to the second main surface 33a side. ing.

  A solder bump 38 protruding higher than the first main surface 32a is formed on the first main surface side land 34a. On these solder bumps 38, electronic components such as an IC chip (not shown) can be joined via solder. On the other hand, the second main surface side land 35 is electrically connected to a printed wiring board such as a mother board (not shown).

  As shown in FIG. 1, a through hole is provided inside the wiring board K1. The through hole of this embodiment deposits a cylindrical through hole conductor 7 on the inner wall surface of the through hole forming hole 6 that penetrates the core substrate 1 and the resin insulating layers 12 and 13, and the cavity of the through hole conductor 7. The portion is filled with the filling resin 9. The through-hole conductor 7 of the through-hole provides conduction between the conductor portion in the build-up layer BU1 on the front surface 2 side of the core substrate 1 and the conductor portion in the build-up layer BU2 on the back surface 3 side of the core substrate 1. It is illustrated.

  As shown in FIGS. 1 and 2, the inner layer wiring patterns 28 and 29 in the wiring board K <b> 1 of the present embodiment extend along the surface direction of the substrate body 20 and are formed by a copper plating layer 42. More specifically, the inner layer wiring patterns 28 and 29 have a layer structure in which an electrolytic copper plating layer is laminated on an electroless copper plating layer. The inner layer wiring patterns 28 and 29 are fine inner layer wiring patterns whose line width and line interval are both 15 μm or less. In the build-up layer BU1 on the surface 2 side, the upper resin insulating layer 30 is laminated on the lower resin insulating layer 16 so as to cover the inner wiring pattern layer 28. In the build-up layer BU2 on the back surface 3 side, the upper resin insulating layer 31 is laminated on the lower resin insulating layer 17 so as to cover the wiring pattern layer 29. In this embodiment, these resin insulating layers 16, 17, 30, and 31 are formed using a thermosetting epoxy resin having a CTE of 50 ppm / ° C. or less.

  As shown in FIG. 2, the inner layer wiring pattern 28 is arranged so as to be sandwiched between two resin insulating layers 16 and 30 adjacent on the surface 2 side. The upper resin insulating layer 30 is in contact with the upper surface 43 side of the inner wiring pattern 28, and the lower resin insulating layer 16 is in contact with the lower surface 44 side of the inner wiring pattern 28. The inner layer wiring pattern 28 is buried in both the resin insulating layers 16 and 30.

  The inner layer wiring pattern 29 is arranged so as to be sandwiched between two resin insulating layers 17 and 31 adjacent on the back surface 3 side. The upper resin insulating layer 31 is in contact with the upper surface 43 side of the inner wiring pattern 29, and the lower resin insulating layer 17 is in contact with the lower surface 44 side of the inner wiring pattern 29. The inner layer wiring pattern 29 is buried in both the resin insulating layers 17 and 31.

  As shown in FIG. 2 and the like, when the wiring board K1 is cut in the stacking direction, the inner layer wiring patterns 28 and 29 appearing on the cut surface have a substantially hexagonal cross section in this embodiment. For convenience of explanation, in the inner layer wiring patterns 28 and 29, the portion embedded in the upper resin insulating layers 30 and 31 is the upper surface side conductor portion 45, and the portion embedded in the lower resin insulating layers 16 and 17 is the bottom surface side conductor. Let it be a portion 46. The upper surface side conductor portion 45 has a tapered cross-sectional shape that becomes narrower as the distance from the core substrate 1 increases. The bottom-side conductor portion 46 has an inversely tapered cross-sectional shape that becomes narrower as it approaches the core substrate 1. In the same plane as the virtual plane 53 formed at the boundary between the lower layer side resin insulation layer 16 and the upper layer side resin insulation layer 30, the maximum width portion 54 (about 15 μm in this embodiment) of the inner layer wiring pattern 28 is formed. Has been placed. That is, in the present embodiment, the maximum width portion 54 is not disposed at the pattern upper end 51 or the pattern lower end 52 but is disposed at a position between them. Further, the cut surfaces in the stacking direction of the inner layer wiring patterns 28 and 29 have a shape that does not have an acute angle or a right angle, and all the angles are obtuse. In particular, the two corners positioned at the pattern upper end 51 are rounded obtuse angles.

  In the cut surfaces of the inner layer wiring patterns 28 and 29, the width W1 of the pattern upper end 51 is slightly larger than the width W2 of the pattern lower end 52. When the width W1 of the pattern upper end 51 is used as a reference, the size of the width W3 of the maximum width portion 54 is about 1.2 to 1.3 times that. Incidentally, the ratio (W3: W1) between the width W3 and the width W1 is set to about 10: 7 to 10: 8, and the ratio (W3: W2) between the width W3 and the width W2 is about 10: 5 to 10: 6. Is set to

  In the inner layer wiring patterns 28 and 29, the height of the upper surface side conductor portion 45 is “h11”, and the height of the bottom surface side conductor portion 46 is “h12”. In the present embodiment, the height h11 is about 5 μm, and the height h12 is about 15 μm. Therefore, the height ratio between the two (h11: h12) is 5:15, and is set to be within a preferable range (1: 9 to 8: 2).

  Next, the manufacturing method of the wiring board K1 of this embodiment is demonstrated based on FIGS.

  First, a core substrate 1 mainly composed of a bismaleimide triazine (BT) resin is prepared. Copper foil is attached in advance to the front surface 2 and the back surface 3 of the core substrate 1. The copper foil of the core substrate 1 is patterned by a conventionally known method (here, subtractive method) to form the core substrate side conductor layers 4 and 5 on the front surface 2 and the back surface 3. Next, the resin insulating layers 12 and 13 are formed on the front surface 2 and the back surface 3 of the core substrate 1, and via hole forming holes 12 a and 13 a are further formed. Here, the resin insulating layers 12 and 13 are formed using a thermosetting resin material for forming a buildup layer (so-called buildup material). In this embodiment, an insulating film in which an inorganic filler is dispersed in an epoxy resin is used as a buildup material. Next, after the through hole forming hole 6 penetrating the core substrate 1 and the resin insulating layers 12 and 13 is formed, electroless copper plating and electrolytic copper plating are performed to form the through hole conductor 7 and the filled via conductors 14 and 15. To do. Next, after filling the cavity of the through-hole conductor 7 with the paste of the filling resin 9, electrolytic copper plating is performed to further form a copper plating film on the copper plating film. At this time, both end surfaces of the filling resin 9 are covered with the cover platings 10a and 11a. Subsequently, these two copper plating films are etched by a conventionally known subtractive method to form inner wiring patterns 10 and 11 as shown in FIG. These inner layer wiring patterns 10 and 11 become the first conductor layer in the build-up layers BU1 and BU2.

  Next, as shown in FIG. 4, the epoxy resin-based insulating film is pasted on the resin insulating layer 12 on the core substrate 1 side and the first inner wiring pattern 10, and the first layer resin is bonded. An insulating layer 16 is formed. Similarly, the first insulating resin layer 17 is formed by pasting the insulating film on the resin insulating layer 13 on the core substrate 1 side and the first inner wiring pattern 11.

  Next, a barrier layer forming step is performed to form a barrier layer 61 on the lower resin insulating layers 16 and 17 (see FIG. 5). Here, the barrier layer 61 having a thickness of about 3 μm to 10 μm is formed by exposing the entire surface after attaching a dry film photoresist.

  Next, the barrier layer 61 and the lower resin insulating layers 16 and 17 are simultaneously laser processed (groove forming step). By this laser processing, an opening 63 penetrating the barrier layer 61 is formed, and the inner layer wiring pattern forming groove 62 and the via hole forming holes 18 and 19 communicating with the opening 63 are formed in the lower resin insulating layers 16 and 17. Form (see FIG. 6). In this embodiment, since the barrier layer 61 is made of a resin material, the opening 63 can be formed relatively easily by laser processing. In this case, since it is necessary to make processing depths different between the via hole forming holes 18 and 19 and the groove 62, for example, the laser output, the number of shots, the irradiation time, and the like are changed for irradiation.

  Next, a desmear process is performed to remove smears on the inner wall surfaces of the openings 63, the via hole forming holes 18 and 19 and the grooves 62, and the entire surfaces of the resin insulating layers 16 and 17 including these inner wall surfaces are roughened. (Surface roughness Ra is set to about 2 μm).

  Next, a conductive portion forming step is performed to form a conductive portion (copper plating layer 42) to be the inner layer wiring patterns 28 and 29 in the groove 62 and the opening 63. Specifically, after a plating catalyst is applied in advance, an electroless copper plating layer having a thickness of about 0.5 μm is formed on the entire surface by electroless copper plating. Further, an electrolytic copper plating layer having a thickness of about 15 μm to 20 μm is formed on the entire surface by electrolytic copper plating (see FIG. 7). Note that the copper plating layer 42 as the conductive portion is formed so as to protrude at least above the groove 62.

  Next, the copper plating layer 42 is mainly removed on the surface of the barrier layer 61 by etching the copper plating layer 42 using a predetermined etching solution that dissolves copper. As a result, filled via conductors 26 and 27 and inner layer wiring patterns 28 and 29 are formed (see FIGS. 8 to 10). FIG. 8 shows the state of the copper plating layer 42 when etching is performed without excess or deficiency. At this time, the height of the surface of the copper plating layer 42 is substantially the same as the height of the surface of the barrier layer 61, and the copper plating layer 42 is not placed on the surface of the barrier layer 61. FIG. 9 shows the state of the copper plating layer 42 when the etching is excessive. In this figure, the height of the surface of the copper plating layer 42 is lower than the height of the surface of the barrier layer 61. However, as long as the difference in height is smaller than the thickness of the barrier layer 61, there is no particular problem even in such excessive etching. FIG. 10 shows the state of the copper plating layer 42 when etching is insufficient. In this figure, the surplus plating portion 42a is placed around the groove 62 on the surface of the barrier layer 61, but the barrier layer 61 is exposed to the extent that it can be removed in a later step. Therefore, no problem arises even if such etching is insufficient.

  Next, a barrier layer removing step is performed to selectively remove the barrier layer 61 from the resin insulating layers 16 and 17 (see FIGS. 11 and 12). Specifically, the dry film photoresist is stripped using a dedicated stripping solution (for example, an alkaline aqueous solution). At this time, the lower resin insulation layers 16 and 17 and the required copper plating layer 42 are left undissolved.

  Next, a shape adjusting step is performed to remove an excess portion of the copper plating layer 42, that is, in the present embodiment, a right angle or acute angle portion in the pattern upper end 51 exposed from the lower resin insulating layers 16 and 17. Adjust the shape. Specifically, quick etching is performed using an etchant that dissolves copper, and the copper plating layer 42 is partially dissolved and removed. The excess plating part 42a shown in FIG. 10 is also removed through this process. As a result, inner layer wiring patterns 28 and 29 having a suitable cut surface shape are formed (see FIG. 13). As a result of the shape adjustment, in the inner layer wiring patterns 28 and 29, the maximum width portion 54 is disposed between the pattern upper end 51 and the pattern lower end 52.

  Next, an embedding process is performed, and the above-mentioned epoxy resin insulating film is pasted on the lower resin insulation layers 16 and 17 to form the upper resin insulation layers 30 and 31, respectively. As a result, the inner wiring pattern 28 is embedded between the lower resin insulating layer 16 and the upper resin insulating layer 30, and the inner wiring pattern 29 is embedded between the lower resin insulating layer 17 and the upper resin insulating layer 31. (See FIG. 14).

  Then, after forming the outer layer wiring patterns 34 and 35 by the semi-additive method, solder resists 32 and 33 each having a thickness of 25 μm are provided on the second resin insulating layers 30 and 31, respectively. Furthermore, after applying nickel-gold plating on the first main surface side land 34a exposed through the opening 36, a solder bump 38 is formed, and the second main surface side land 35a exposed through the opening 37 is formed. Is subjected to nickel-gold plating. As a result, the multilayer wiring board K1 having the build-up layers BU1 and BU2 on both the front and back surfaces as shown in FIG. 1 is completed.

Therefore, according to the present embodiment, the following effects can be obtained.
(1) In the multilayer wiring board K1 of the present embodiment, the maximum width portion 54 on the cut surface in the stacking direction of the inner layer wiring patterns 28 and 29 is not located at the pattern upper end 51 or the pattern lower end 52 but at a position between them. Has been. For this reason, the pattern upper end 51 and the pattern lower end 52 no longer have a right-angle or acute-angle portion, but instead have an obtuse-angle portion that is unlikely to become a starting point of crack generation. In particular, the upper end 51 of the pattern has a rounded obtuse angle. Therefore, the occurrence of cracks in the resin insulating layers 16, 17, 30, and 31 is suppressed, and the reliability sufficient for the multilayer wiring board K1 can be improved. Further, according to the configuration of this embodiment, for example, even when the resin insulating layers 16, 17, 30, and 31 having a hard and brittle property are employed in order to pursue low thermal expansion, the generation of cracks is prevented. Therefore, it is possible to achieve both low thermal expansion and high reliability.

  (2) In the multilayer wiring board K1 of the present embodiment, the inner layer wiring patterns 28 and 29 are buried in both the lower layer side resin insulation layers 16 and 17 and the upper layer side resin insulation layers 30 and 31. A suitable close contact state is maintained. Therefore, even if it is the fine inner layer wiring patterns 28 and 29, it is difficult to cause a lateral fall or peeling, and sufficient adhesion can be imparted. In addition, since the lower side of the inner layer wiring patterns 28 and 29 is buried in the lower layer side resin insulation layers 16 and 17, the surface of the upper surface side resin insulation layers 30 and 31 is less likely to be uneven. Therefore, there is an advantage that the thickness variation of the upper surface side resin insulation layers 30 and 31 can be reduced. Therefore, the flatness of the IC chip mounting surface can be improved.

  (3) A so-called trench filling method is conventionally known as a method for forming a groove in the lower resin insulating layer and filling the groove with a copper plating layer to form an inner wiring pattern. However, this method is difficult in the process because it is necessary to remove all of the copper plating layer protruding from the resin insulating layer while leaving the copper plating layer in the groove. There is a problem that occurs. In that respect, according to the manufacturing method of the multilayer wiring board K1 of the present embodiment, there is an advantage that strictness is not required when removing the copper plating layer. That is, even if there is some excess or deficiency in the etching of the copper plating layer, the inner layer wiring patterns 28 and 29 having a desired cut surface shape can be finally formed without causing the wiring to be cut or short-circuited. Therefore, the multilayer wiring board K1 can be manufactured relatively easily and with a high yield.

  (4) In the multilayer wiring board K1 of the present embodiment, the width W3 of the maximum width portion 54 is set within a preferable range of 1.1 to 1.5 times the width W1 of the pattern upper end 51. Further, the ratio between the width W3 and the W1 width is set within a preferable range of 10: 1 to 10: 9, and the ratio between the width W3 and the W1 width is set within a preferable range of 10: 5 to 10: 9. Has been. From the above, in the present embodiment, the pattern upper end 51, the pattern lower end 52, and the maximum width portion 54 are unlikely to form a right angle or an acute angle portion, and any corner on the cut surface is unlikely to be a starting point of crack generation. it can.

  In addition, you may change embodiment of this invention as follows.

  In the multilayer wiring board K1 of the above embodiment, the cut surfaces in the stacking direction of the inner layer wiring patterns 28 and 29 have a substantially hexagonal shape, but may be other than a substantially hexagonal shape. For example, in the inner layer wiring pattern 28A of another embodiment shown in FIG. 15, the cut surface in the stacking direction has a substantially pentagonal shape. Such an inner layer wiring pattern 28A can be formed by setting etching conditions stronger than in the embodiment and etching the upper surface side conductor portion 45 more. Alternatively, as in an inner layer wiring pattern 28B of another embodiment shown in FIG. 16, the upper-side conductor portion 45 may have a cupcake-like cut direction in the stacking direction having a convex curved surface. Such an inner layer wiring pattern 28B can be similarly formed by setting the etching conditions strongly.

  In addition, like the inner layer wiring pattern 28 </ b> C of another embodiment shown in FIG. 17, the lower conductor portion 46 can be rounder than the above embodiment. In other words, the corners of the lower end 52 of the pattern may be eliminated so that the bottom-side conductor portion 46 has a semi-elliptical shape as a whole. Such an inner layer wiring pattern 28 </ b> C can be formed, for example, by setting a weak laser processing condition when forming the opening 63 and the groove 62 and rounding the bottom of the groove 62.

  In the multilayer wiring board K1 of the above embodiment, the maximum width portion 54 on the cut surface in the stacking direction of the inner layer wiring patterns 28 and 29 is disposed in the same plane as the virtual plane 53, but is disposed at a different position. It may be. For example, the maximum width portion 54 may be arranged at a position between the virtual plane 53 and the pattern upper end 51 as in an inner layer wiring pattern 28D of another embodiment shown in FIG.

  In the above embodiment, the present invention is embodied in the multilayer wiring substrate K1 having the core substrate 1, but may be embodied in a multilayer wiring substrate having no so-called core substrate.

  In the above embodiment, the protrusions 46 are provided to fill the grooves 51 when the inner layer wiring patterns 28 and 29 are fine patterns having a maximum width of 20 μm or less. However, even when the maximum width is more than 20 μm, A similar configuration may be adopted.

  In the above embodiment, the inner layer wiring patterns 28 and 29 are exemplified such that the height is h11 <h12. However, the height may be h11> h12, for example. However, even in this case, the height ratio (h11: h12) is preferably set within a preferable range of 1: 9 to 8: 2.

  In the above-described embodiment, an example in which the inner layer wiring pattern 28 is disposed between two adjacent resin insulating layers 16 and 30 of the same type has been described. However, for example, a similar structure is provided between two different types of resin insulating layers adjacent to each other. An inner layer wiring pattern may be arranged.

Next, the technical ideas grasped by the embodiment described above are listed below.
(1) In means 1, the inner wiring pattern is made of a metal plating layer.
(2) In means 1, the inner layer wiring pattern is made of a copper plating layer.
(3) In means 1 or ideas 1 or 2, the height of the upper conductor portion embedded in the upper resin insulation layer and the bottom surface buried in the lower resin insulation layer in the inner wiring pattern The ratio with the height of the side conductor portion is in the range of 1: 9 to 8: 2.
(4) In any one of means 1 and ideas 1 to 3, the inner layer wiring pattern is a fine pattern having a maximum width of 20 μm or less.
(5) In means 1, any one of thoughts 1 to 4, the lower resin insulation layer and the upper resin insulation layer are made of the same type of resin insulation layer having thermosetting properties.
(6) In the method 1, any one of the thoughts 1 to 4, the lower resin insulation layer and the upper resin insulation layer have the same thermal expansion coefficient and a thermosetting coefficient of 50 ppm / ° C. or less. It consists of a resin insulation layer.
(7) In means 1, all the angles in the cut surface in the stacking direction of the inner layer wiring pattern are obtuse angles.
(8) In means 1, the inner layer wiring pattern has a substantially pentagonal or hexagonal cut surface in the stacking direction.
(9) In means 1, the inner layer wiring pattern has a cupcake-like stacking direction cut surface shape in which the upper end of the pattern is a convex curved surface.
(10) In any one of means 1 and ideas 1 to 9, the multilayer wiring board is a build-up multilayer wiring board having a build-up layer formed by alternately laminating resin insulating layers and conductor layers. A multilayer wiring board characterized in that there is.
(11) In any one of means 1 and ideas 1 to 10, a via hole forming hole is formed in the resin insulating layer in contact with the bottom surface side, and a filled via conductor is formed in the via hole forming hole. A multilayer wiring board, wherein a height of the bottom side conductor portion is set to be smaller than a depth of the via hole forming hole.
(12) The multilayer wiring board according to any one of means 1 and ideas 1 to 11, wherein the multilayer wiring board has a core substrate.
(13) The multilayer wiring board according to any one of means 1 and ideas 1 to 11, wherein the multilayer wiring board does not have a core substrate.

16, 17 ... Lower layer side resin insulation layer 20 ... Substrate body 28, 28A, 28B, 28C, 28D, 29 ... Inner layer wiring pattern 30, 31 ... Upper layer side resin insulation layer 32a ... Substrate main surface 33a ... Substrate back surface 43 ... (Inner layer) Upper surface 44 of wiring pattern (bottom of inner layer wiring pattern) 51 ... Pattern upper end 52 ... Pattern lower end 53 ... Virtual plane 54 ... Maximum width portion K1 ... Multi-layer wiring board W1 ... Pattern upper end width W2 ... Pattern lower end width W3 ... Width of maximum width part

Claims (8)

A substrate body having a substrate main surface and a substrate back surface formed by laminating a plurality of resin insulation layers, an inner layer wiring pattern extending along a surface direction of the substrate body, and a lower layer side resin insulation in contact with the bottom surface side of the inner layer wiring pattern And an upper resin insulating layer adjacent to the lower layer resin insulating layer and in contact with the upper surface side of the inner layer wiring pattern, the inner wiring pattern being formed of the lower layer resin insulating layer and the upper layer resin insulating layer. In the multilayer wiring board buried in both,
A multilayer wiring board, wherein the maximum width portion of the inner layer wiring pattern on the cut surface in the stacking direction is disposed at a position between the upper end of the pattern and the lower end of the pattern.   2. The multilayer wiring according to claim 1, wherein the maximum width portion is arranged in the same plane as a virtual plane formed at a boundary between the lower resin insulating layer and the upper resin insulating layer. substrate.   2. The maximum width portion is disposed at a position between a virtual plane formed at a boundary between the lower layer side resin insulation layer and the upper layer side resin insulation layer and an upper end of the pattern. A multilayer wiring board according to 1.   4. The multilayer wiring board according to claim 1, wherein a cut surface in the stacking direction of the inner layer wiring pattern has a shape that does not have an acute angle or a right angle. 5.   5. The corner according to any one of claims 1 to 4, wherein a corner of the inner layer wiring pattern cut in a stacking direction is rounded with respect to the upper resin insulating layer. Multilayer wiring board.   The ratio between the width of the maximum width portion and the width of the upper end of the pattern is within a range of 10: 1 to 10: 9 on the cut surface in the stacking direction of the inner layer wiring pattern. The multilayer wiring board according to any one of the above.   The ratio between the width of the maximum width portion and the width of the lower end of the pattern in the cut surface in the stacking direction of the inner layer wiring pattern is in the range of 10: 5 to 10: 9. The multilayer wiring board according to any one of the above. A method for manufacturing a multilayer wiring board according to any one of claims 1 to 7,
A groove forming step of forming a groove for forming an inner layer wiring pattern in the lower layer side resin insulation layer;
A conductive part forming step of forming a conductive part that is filled in the groove and is raised above the groove;
A shape adjusting step of adjusting the shape by removing an excess portion of the conductive portion, and forming the inner layer wiring pattern;
Forming the upper resin insulating layer on the lower resin insulating layer, and embedding the inner wiring pattern between the lower resin insulating layer and the upper resin insulating layer. A method for manufacturing a multilayer wiring board.

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