CN110381675B - Circuit board structure and manufacturing method thereof - Google Patents
Circuit board structure and manufacturing method thereof Download PDFInfo
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- CN110381675B CN110381675B CN201810327449.7A CN201810327449A CN110381675B CN 110381675 B CN110381675 B CN 110381675B CN 201810327449 A CN201810327449 A CN 201810327449A CN 110381675 B CN110381675 B CN 110381675B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09045—Locally raised area or protrusion of insulating substrate
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Abstract
The invention provides a circuit board structure and a manufacturing method thereof.A copper plate layer of a copper plate layer is provided with upper lugs and lower lugs on the opposite surfaces, the upper lugs and the lower lugs are arranged in an array mode, the upper lugs and the lower lugs are respectively embedded into a dielectric layer contacted with the copper plate layer, the binding force between the dielectric layers contacted with the copper plate layer is enhanced through the upper lugs and the lower lugs, the phenomenon that the copper plate layer is laminated due to poor binding force between the copper plate layer and the dielectric layer when the copper plate layer is too thick is avoided, meanwhile, the copper plate layer is still in a full-area copper-coated structure, and the current carrying capacity of the copper plate layer is ensured.
Description
Technical Field
The present invention relates to the field of integrated circuit technology, and more particularly, to a circuit board structure and a method for manufacturing the same.
Background
The ultra-thick copper circuit board is a circuit board integrated with copper with larger thickness and larger area, and is mainly applied to devices with larger current-carrying capacity or large-area copper-clad power supply or ground planes.
The thickness of copper in ultra-thick copper circuit boards is usually over 100um, so that the problem of easy delamination between a large area of thick copper plate and a dielectric layer due to poor bonding force is solved. At present, in order to solve the problem of poor bonding force of the thick copper plate, a grid treatment method is generally adopted, that is, a grid-formed thick copper plate is formed. This method, although improving the bonding force, affects the current carrying capacity of the thick copper plate.
Disclosure of Invention
Accordingly, the present invention is directed to a circuit board structure and a method for manufacturing the same, which can ensure the bonding capability and current carrying capability of copper layers.
In order to achieve the purpose, the invention has the following technical scheme:
a circuit board structure comprising:
a circuit board core board;
the copper plate layer is positioned on the circuit board core plate, the opposite surfaces of the copper plate layer are respectively provided with an upper lug and a lower lug, and the upper lug and the lower lug are arranged in an array and are integrated with the copper plate layer;
the copper plate layer is positioned between an upper dielectric layer and a lower dielectric layer, the upper lug and the lower lug are respectively embedded into the upper dielectric layer and the lower dielectric layer, and the lower dielectric layer is a circuit board core board or an interlayer dielectric layer.
Optionally, the lower dielectric layer is a circuit board core board, and the copper plate layer is disposed on one surface or two opposite surfaces of the circuit board core board.
Optionally, the copper plate layers are disposed on two surfaces of the circuit board core board, and when the lower dielectric layer is an interlayer dielectric layer, the circuit board core board further includes: the interconnection layer is positioned between the interlayer dielectric layer and the circuit board core board; an interconnect via in the circuit board core, the interconnect via electrically connected with the interconnect layer.
Optionally, the copper plate layer has a thickness greater than 100 um.
Optionally, the upper bumps and the lower bumps have the same size and the same arrangement pitch.
Optionally, the thickness of the upper bump is 5-25% of the thickness of the upper dielectric layer; and/or the thickness of the lower bump is 5-25% of the thickness of the lower medium layer.
A method of manufacturing a circuit-board structure, comprising:
providing a circuit board core board;
forming blind holes in the circuit board core plate, wherein the blind holes are arranged in an array and are formed in one or two opposite surfaces of the circuit chip;
carrying out copper filling to form a lower bump in the blind hole and a copper plate layer on the lower bump;
etching the copper plate layer to form upper bumps, wherein the upper bumps are arranged in an array;
and forming an upper dielectric layer on the copper plate layer and the upper bump.
Optionally, the copper plate layer has a thickness greater than 100 um.
A method of manufacturing a circuit-board structure, comprising:
providing a circuit board core board;
forming a through hole in the circuit core board, and filling to form an interconnection through hole;
forming an interconnection layer on both sides of the interconnection via respectively;
forming an interlayer dielectric layer on the interconnection layer;
forming blind holes in the interlayer dielectric layer, wherein the blind holes are arranged in an array;
carrying out copper filling to form a lower bump in the blind hole and a copper plate layer on the lower bump;
etching the copper plate layer to form upper bumps, wherein the upper bumps are arranged in an array;
and forming an upper dielectric layer on the copper plate layer and the upper bump.
Optionally, the copper plate layer has a thickness greater than 100 um.
The circuit board structure and the manufacturing method thereof provided by the embodiment of the invention have the advantages that the upper convex blocks and the lower convex blocks are respectively arranged on the opposite surfaces of the copper board layer and are arranged in an array mode, the upper convex blocks and the lower convex blocks are respectively embedded into the dielectric layers contacted with the copper board layer, the binding force between the dielectric layers contacted with the copper board layer is enhanced through the upper convex blocks and the lower convex blocks, the layering caused by poor binding force between the copper board layer and the dielectric layers when the copper board layer is too thick is avoided, meanwhile, the copper board layer is still in a full-area copper-coated structure, and the current carrying capacity of the copper board layer is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic cross-sectional view of a circuit board structure according to a first embodiment of the present invention;
2-8 are schematic cross-sectional views illustrating a circuit board structure formed by a first manufacturing method according to an embodiment of the invention;
fig. 9 is a schematic cross-sectional view of a circuit board structure according to a second embodiment of the invention;
fig. 10 to 19 are schematic cross-sectional views illustrating the formation of a circuit board structure according to a second embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
Next, the present invention will be described in detail with reference to the drawings, wherein the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration when describing the embodiments of the present invention, and the drawings are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As described in the background art, when forming an ultra-thick circuit board, a large area of thick copper plate and a dielectric layer may be easily layered due to a difference in bonding force, and at present, in order to improve the bonding force between the thick copper plate and the dielectric layer, a grid processing method is usually adopted for the thick copper plate, but this may affect the current carrying capacity of the thick copper.
To this end, the present application provides a circuit board structure comprising:
a circuit board core board;
the copper plate layer is positioned on the circuit board core plate, the opposite surfaces of the copper plate layer are respectively provided with an upper lug and a lower lug, and the upper lug and the lower lug are arranged in an array and are integrated with the copper plate layer;
the copper plate layer is positioned between an upper dielectric layer and a lower dielectric layer, the upper lug and the lower lug are respectively embedded into the upper dielectric layer and the lower dielectric layer, and the lower dielectric layer is a circuit board core board or an interlayer dielectric layer.
The Circuit board core board is a pcb (printed Circuit board) core board, and the core board is usually formed of a dielectric material of an organic material.
The copper plate layer is a thick copper layer, and in a typical circuit board structure, the thickness of the thick copper layer is more than 100 um.
It should be noted that, in the present application, the upper and lower are relative to the circuit board core, wherein the lower dielectric layer and the lower bump are located on the side of the copper plate closer to the circuit board core, and the upper dielectric layer and the upper bump are located on the side of the copper plate farther from the circuit board core.
In the embodiment of the application, the upper convex blocks and the lower convex blocks are respectively arranged on the opposite surfaces of the copper plate layer, the upper convex blocks and the lower convex blocks are arranged in an array mode, and the upper convex blocks and the lower convex blocks are respectively embedded into the dielectric layers in contact with the copper plate layer to form the blind pin structure, so that the binding force between the dielectric layers in contact with the copper plate layer is enhanced through the upper convex blocks and the lower convex blocks, the layering caused by poor binding force between the copper plate layer and the dielectric layers when the copper plate layer is too thick is avoided, meanwhile, the copper plate layer is still in a full-area copper-coated structure, and the current carrying capacity of the copper plate.
In the present application, the copper plate layer may be formed between the circuit board core and the dielectric layer, or between two interlayer dielectric layers, and in order to better understand the technical solution and the technical effect of the present application, the structure and the manufacturing process of different embodiments will be described in detail below.
Example one
In this embodiment, a thick copper plate is formed between the circuit board core and the dielectric layer.
Referring to fig. 1, in the present embodiment, the circuit board structure includes:
a circuit board core 100;
the circuit board comprises a copper board layer 106 on one side or two opposite sides of a circuit board core board 100, wherein upper bumps 108 and lower bumps 104 are arranged on the opposite surfaces of the copper board layer 106, and the upper bumps 108 and the lower bumps 104 are arranged in an array and integrated with the copper board layer 106;
the copper plate layer 106 is located between the upper dielectric layer 112 and the circuit board core 100, and the upper bump 108 and the lower bump 104 are embedded in the upper dielectric layer 112 and the circuit board core 100, respectively.
In the present embodiment, the copper plate layer 106 is generally a large-area copper material layer and has a relatively thick thickness, for example, a thickness of over 100um, and the copper plate layer 106 is generally used as a power supply or a ground plane, and can also be used for heat dissipation. The copper plate layers 106 may be formed on one of the surfaces of the circuit board core or on both of the opposing surfaces of the circuit board core, with the upper and lower bumps 108 and 104 being formed on both of the opposing surfaces of each copper plate layer 106 when formed on the opposing surfaces of the circuit board core.
The upper bump 108 and the lower bump 104 are respectively embedded in the upper dielectric layer 112 and the circuit board core board 100, that is, the upper bump 108 does not penetrate through the upper dielectric layer 112 above the upper bump, and the lower bump 104 does not penetrate through the circuit board core board below the lower bump, and are respectively embedded in the dielectric layer 112 and the circuit board core board 100, so that a blind pin structure is formed, and the blind pin structure and the copper plate layer 106 are integrated into a whole, thereby, the copper plate layer is fixed to the upper dielectric layer and the lower dielectric layer, and simultaneously, the copper coating amount of the copper plate layer is not lost, the copper plate layer is still in a full-area copper coating structure, and the current carrying capacity of the copper plate.
In a specific application, the thickness of the upper bump 108, i.e., the depth of embedding into the upper dielectric layer 112, may be 5-25% of the thickness of the upper dielectric layer; likewise, the thickness of the underbump 104, i.e. the depth of embedding into the circuit board core 100, may be 5-25% of the thickness of the circuit board core. In one specific application, the thickness of the upper dielectric layer is 150um, the thickness of the upper bump 108 can be 5-20um, the thickness of the circuit board core is usually greater than 100um, and the thickness of the lower bump can be, for example, 10-20 um.
The size and distribution of the upper bumps 108 and the lower bumps 104 can be determined according to the area of the copper plate layer, the upper bumps and the lower bumps can have the same or different sizes and arrangement, and in some applications, the upper bumps 108 and the lower bumps 104 have the same size and the same arrangement spacing, and it is understood that the identity is substantially the same here and is approximately the same within the allowable range of manufacturing errors. In other applications, the upper bumps and the lower bumps may have different arrangements and/or arrangement pitches according to different requirements, for example, the upper bumps 108 and the lower bumps 104 may be arranged oppositely or in a staggered manner, where the relative arrangement refers to the arrangement of the upper bumps 108 and the lower bumps 104 at corresponding positions, and the staggered arrangement refers to the formation of the upper bumps at the positions of the pitches of the lower bumps.
It will be appreciated that other structures may be included in the circuit board structure, as desired, and in some applications, for example, other interconnect layers or heat sink layers may be included on top of the upper dielectric layer 112, and in other applications, for example, when copper board layers are formed on both sides of the circuit board core, the interconnect via 1021 may be included between the copper board layers.
The circuit board structure according to the embodiment of the present application is described in detail above, and the manufacturing method of the embodiment will be described in detail below with reference to the drawings, in which the formation of the copper board layers on both sides of the circuit board core is taken as an example.
In step S10, a circuit board core board 100 is provided, as shown with reference to fig. 2.
The circuit board core board 100 is a central board of the PCB, and the circuit board is processed by using the core board as a center. Typically, the core is usually formed of a dielectric material of an organic material, thin copper plating layers 1001 are usually formed on the upper and lower surfaces of the circuit board core 100, and the copper plating layers 1001 are retained, partially retained, or removed as necessary in the subsequent processing.
At step S11, blind vias 103 are formed in the circuit board core board 100, the blind vias 103 are arranged in an array, and the blind vias 103 are formed in one or two opposite surfaces of the circuit board core board 100, as shown with reference to fig. 4.
The blind hole 103 may be formed in one of the surfaces of the circuit board core board 100, or may be formed in both surfaces of the circuit board core board, according to various needs.
Specifically, first, openings 101 may be formed in the copper clad layers 1001 on both surfaces of the circuit board core board 100 by a laser process, respectively, and as shown with reference to fig. 3, the positions of the openings 101 of the copper clad layers 1001 correspond to the positions of the blind holes 103 to be formed.
Then, the laser process may be continued to form blind vias 103 under the openings 101, respectively, as shown in fig. 4, the positions of the blind vias 103 are the areas of the large-area copper plate layer to be formed, and the blind vias 103 are arranged in an array, and the depth of the blind vias is controlled during the processing process to avoid interconnection caused by excessive depth, and typically, the depth of the blind vias 103 may be, for example, 10-20 um. The blind hole may be, for example, a square or circular hole.
In step S12, copper filling is performed to form lower bumps 104 in the blind vias 103 and to form copper plate layers 106 on the lower bumps 104, as shown in fig. 6.
Specifically, first, copper filling may be performed by an electroplating copper process, and after the copper filling, an interconnect via 1021 of copper will be formed in the via hole 102, an under bump 104 of copper will be formed in the blind via 103, and a copper cap layer 105 will be formed over the blind via 103, as shown with reference to fig. 5. Preferably, when copper filling is performed, the thick copper covering layer can be formed by electroplating copper on the front side and the back side for multiple times, the thickness of the copper covering layer can be larger than 100um, and high-temperature annealing is performed, so that the internal stress of the thick copper covering layer is released.
Then, the copper capping layer 105 may be patterned through an etching process, thereby forming a copper plate layer 106 on the lower bumps 104 in a desired area, as shown with reference to fig. 6.
In this step, the lower convex block 104 embedded in the circuit board core 100 is formed by copper filling, and is formed together with the copper plate layer 106 by copper filling to be an integral structure, and the lower convex block is a copper pin structure embedded in the circuit board core 100, so that the bonding force between the copper plate layer and the circuit board core is enhanced.
In step S13, the copper plate layer 106 is etched to form upper bumps 108, and the upper bumps 108 are arranged in an array, as shown in fig. 7.
The upper bump 108 integrated with the copper plate layer 106 may be formed by forming a mask pattern on the copper plate layer and then etching the copper plate layer 106 through an etching process, as shown in fig. 7, the thickness of the upper bump 108 may be, for example, 10-20um, and the upper bump 108 is used to enhance the bonding force with the dielectric layer on the copper plate layer.
In step S14, an upper dielectric layer 112 is formed on the copper layer 106 and the upper bumps 108, as shown in fig. 8.
The upper dielectric layer 112 may be formed by a lamination process, and after laminating the dielectric materials, on one hand, the upper bumps 108 on the copper plate layers 106 are embedded into the upper dielectric layer 112, and on the other hand, the gaps between the copper plate layers 106 are filled, and preferably, the upper dielectric layer 112 may be selected from a semi-cured material with good fluidity and better filling performance.
Further, other desired structures may be further formed on the upper dielectric layer 112, such as further forming other interconnect layers 114, etc., as shown with reference to fig. 8.
Thus, the copper plate layer 106 with the integrally formed upper convex blocks 108 and lower convex blocks 104 is formed on the circuit board core board, and the upper convex blocks 108 and the lower convex blocks 104 are respectively embedded into the circuit board core board 100 and the upper dielectric layer 112, so that the bonding force between the copper plate layer 106 and the upper, lower and dielectric layers is improved, and meanwhile, the copper plate layer is still in a full-area copper-clad structure, and the current carrying capacity of the copper plate layer is ensured.
Example two
In contrast to the first embodiment, in this embodiment, another interconnect layer is formed between the circuit board core and the copper plate layer, and the bumps of the copper plate layer are embedded in the interlayer dielectric layer on the interconnect layer.
Referring to fig. 9, in the present embodiment, the circuit board structure includes:
a circuit board core board 200, the circuit board core board 200 having an interconnect via 202 disposed therein;
an interconnect layer 204 on opposing surfaces of circuit board core 200, said interconnect vias 202 electrically connecting said interconnect layer 204;
an interlevel dielectric layer 206 over the interconnect layer 204;
the copper plate layer 212 on the interlayer dielectric layer 206 and the upper dielectric layer 220 on the copper plate layer 212, wherein an upper bump 214 and a lower bump 210 are arranged on the surface of the copper plate layer 212 opposite to each other, the upper bump 214 and the lower bump 210 are arranged in an array and integrated with the copper plate layer 212, and the upper bump 214 and the lower bump 210 are respectively embedded into the upper dielectric layer 220 and the interlayer dielectric layer 206.
In this embodiment, before the copper board layer is formed, an interconnect layer 204 is formed, and the interconnect layer 204 may be one or more layers, and the electrical connection of the interconnect layer 204 on the two surfaces of the circuit board core board 200 is realized through the interconnect via 202 provided in the circuit board core board. The interlayer dielectric layer is a dielectric material layer between the interconnection layer and the copper plate layer.
In the present embodiment, the copper plate layer 212 is generally a large-area copper material layer and has a relatively thick thickness, for example, a thickness of more than 100um, and the copper plate layer 212 is generally used as a power supply or a ground plane, and can also be used for heat dissipation. Copper plate layers 212 are simultaneously formed on opposite surfaces of the circuit board core, and upper and lower bumps 214 and 210 are formed on opposite surfaces of each copper plate layer 212, respectively, on both opposite surfaces of the circuit board core.
The upper bump 214 and the lower bump 210 are respectively embedded in the upper dielectric layer 220 and the interlayer dielectric layer 206, that is, the upper bump 214 does not penetrate through the upper dielectric layer 112 above the upper bump, and the lower bump 210 does not penetrate through the interlayer dielectric layer 206 below the lower bump, and are respectively embedded in the upper dielectric layer 220 and the interlayer dielectric layer 206, so that a blind pin structure is formed, and the structure is integrated with the copper plate layer 212, thereby fixing the copper plate layer to the upper dielectric layer and the lower dielectric layer above the copper plate layer, and simultaneously, the copper coating amount of the copper plate layer is not lost, the copper plate layer is still in a full-area copper coating structure, and the current carrying capacity of the copper plate layer is ensured.
In a specific application, the thickness of the upper bump 214, i.e., the depth embedded into the upper dielectric layer 220, may be 5-25% of the thickness of the upper dielectric layer; similarly, the thickness of the under bump 210, i.e., the depth of embedding into the interlayer dielectric layer 206, may be 5-25% of the thickness of the interlayer dielectric layer 206. In one specific application, the thickness of the upper dielectric layer may be 100um, the thickness of the upper bump 214 may be 10-20um, the thickness of the interlayer dielectric layer may be 80um, and the thickness of the lower bump 210 may be 10-20um, for example.
The sizes and the distribution manners of the upper bumps 214 and the lower bumps 210 may be determined according to the areas of the copper plate layers, the upper bumps and the lower bumps may have the same or different sizes and arrangement manners, in some applications, the upper bumps 214 and the lower bumps 210 have the same size and the same arrangement spacing, further, the upper bumps 214 and the lower bumps 210 may be arranged oppositely or in a staggered manner, the relative arrangement means that the upper bumps 214 and the lower bumps 210 are arranged at corresponding positions, and the staggered arrangement means that the upper bumps are formed at positions of the spacing of the lower bumps.
It is understood that other structures may be included in the circuit board structure, and in some applications, other interconnect layers or heat dissipation layers may be included on the upper dielectric layer 220, for example.
The circuit board structure of the embodiment of the present application is described in detail above, and the manufacturing method of the embodiment is described in detail below with reference to the drawings.
In step S20, the circuit board core board 200 is provided, as shown with reference to fig. 10.
The circuit board core board 200 is a central board of the PCB, and the circuit board is processed by using the core board as a center. Typically, the core is formed of a dielectric material, typically an organic material, and the circuit board core 200 is typically formed with thin copper metallization layers (not shown) on both its upper and lower surfaces, which are retained, partially retained, or removed as needed during subsequent processing.
At step S21, vias 201 are formed in the circuit core board 200 and filled to form interconnect vias 202, as shown with reference to fig. 11-12.
Specifically, the through-hole 201 may be formed on a desired area through a mechanical drilling process, as shown with reference to fig. 11.
Then, an interconnection via may be formed in the via 201, and when the interconnection via 202 is formed, a metal layer, for example, a metal copper layer, may be formed on the sidewall of the via 201 by using an electroplating process to form the interconnection via 202, and then, a resin material is filled in the via to realize a via hole of the via, as shown with reference to fig. 12.
In step S22, interconnect layers 204 are formed on both sides of the interconnect via 202, respectively, as shown with reference to fig. 13.
The interconnect layer 204 is typically a higher density interconnect layer than a copper layer to achieve interconnection between circuits, the interconnect layer 204 may be one or more layers, and the interconnect layer 204 may be formed by electroplating or other suitable processes, as shown in fig. 13.
In step S23, an interlayer dielectric layer 206 is formed on the interconnect layer 204, as shown with reference to fig. 14.
The interlevel dielectric layer 206 may be formed by a lamination process or other deposition process of dielectric materials.
In step S24, blind vias 209 are formed in the interlayer dielectric layer 206, and the blind vias 209 are arranged in an array, as shown in fig. 15.
At the same time, a via 207 may also be formed by a laser process, which via 207 is used for further interconnection of the interconnect layer 204.
In step S25, copper filling is performed to form an under bump 210 in the blind via and a copper plate layer 212 on the under bump 210, as shown in fig. 17.
Specifically, first, copper filling may be performed through an electroplating copper process, and after the copper filling, an interconnect via 208 of copper will be formed in the via 207, an under bump 210 of copper will be formed in the blind via 209, and a copper cap layer 211 will be formed over the blind via 209, as shown with reference to fig. 16. Preferably, when copper filling is performed, the thick copper covering layer can be formed by electroplating copper on the front side and the back side for multiple times, the thickness of the copper covering layer can be larger than 100um, and high-temperature annealing is performed, so that the internal stress of the thick copper covering layer is released.
Then, the copper cap layer 211 may be patterned through an etching process, thereby forming a copper plate layer 212 on the lower bumps 210 in a desired area, as shown with reference to fig. 17.
In step S26, the copper plate layer 212 is etched to form upper bumps 214, and the upper bumps 214 are arranged in an array, as shown in fig. 18.
The upper bumps 214 may be formed integrally with the copper plate layer 212 by forming a mask pattern on the copper plate layer and then etching the copper plate layer 212 through an etching process, as shown in fig. 18, the thickness of the upper bumps 214 may be, for example, 10-20um, and the upper bumps 214 are used to enhance the bonding force with the upper dielectric layer on the copper plate layer.
In step S27, an upper dielectric layer 220 is formed on the copper plate layer 212 and the upper bumps 214, as shown in fig. 19.
The upper dielectric layer 220 may be formed by a lamination process, and after laminating the dielectric materials, on one hand, the upper bumps 214 on the copper plate layers 212 are embedded into the upper dielectric layer 220, and on the other hand, the gaps between the copper plate layers 212 are filled, and preferably, the upper dielectric layer 220 may be selected from a semi-cured material with good fluidity and better filling performance.
Further, other desired structures may be further formed on the upper dielectric layer 220, such as further forming other interconnect layers 230, etc., as shown in fig. 19.
Therefore, the copper plate layer 212 with the integrally formed upper convex blocks 214 and lower convex blocks 210 is formed on the circuit board core board, the upper convex blocks 214 and the lower convex blocks 210 are respectively embedded into the interlayer dielectric layer 206 and the upper dielectric layer 220, the bonding force between the copper plate layer 212 and the upper, lower and dielectric layers is improved, meanwhile, the copper plate layer is still in a full-area copper-clad structure, and the current carrying capacity of the copper plate layer is ensured.
The foregoing is only a preferred embodiment of the present invention, and although the present invention has been disclosed in the preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (10)
1. A circuit board structure, comprising:
a circuit board core board;
the copper plate layer is positioned on the circuit board core plate, the opposite surfaces of the copper plate layer are respectively provided with an upper lug and a lower lug, and the upper lug and the lower lug are arranged in an array and are integrated with the copper plate layer;
the copper plate layer is positioned between an upper dielectric layer and a lower dielectric layer, the upper lug and the lower lug are respectively embedded into the upper dielectric layer and the lower dielectric layer, and the lower dielectric layer is a circuit board core board or an interlayer dielectric layer;
the lower bump and the copper plate layer on the lower bump are formed together through copper filling;
the upper bump is formed by etching the copper plate layer.
2. The structure of claim 1, wherein the lower dielectric layer is a circuit board core having the copper plate layer disposed on one surface or both opposing surfaces of the circuit board core.
3. The structure of claim 1, wherein the copper plate layers are disposed on both surfaces of the circuit board core, and when the lower dielectric layer is an interlayer dielectric layer, the structure further comprises: the interconnection layer is positioned between the interlayer dielectric layer and the circuit board core board; an interconnect via in the circuit board core, the interconnect via electrically connected with the interconnect layer.
4. The structure of claim 1, wherein the copper plate layer has a thickness greater than 100 um.
5. The structure according to any one of claims 1 to 4, wherein the upper bumps and the lower bumps have the same size and the same arrangement pitch.
6. The structure of any one of claims 1-4, wherein the upper bump has a thickness of 5-25% of the thickness of the upper dielectric layer; and/or the thickness of the lower bump is 5-25% of the thickness of the lower medium layer.
7. A method of manufacturing a circuit-board structure, comprising:
providing a circuit board core board;
forming blind holes in the circuit board core plate, wherein the blind holes are arranged in an array and are formed in one or two opposite surfaces of the circuit chip;
carrying out copper filling to form a lower bump in the blind hole and a copper plate layer on the lower bump;
etching the copper plate layer to form upper bumps, wherein the upper bumps are arranged in an array;
and forming an upper dielectric layer on the copper plate layer and the upper bump.
8. The method of manufacturing of claim 7, wherein the copper plate layer has a thickness greater than 100 um.
9. A method of manufacturing a circuit-board structure, comprising:
providing a circuit board core board;
forming a through hole in the circuit core board, and filling to form an interconnection through hole;
forming an interconnection layer on both sides of the interconnection via respectively;
forming an interlayer dielectric layer on the interconnection layer;
forming blind holes in the interlayer dielectric layer, wherein the blind holes are arranged in an array;
carrying out copper filling to form a lower bump in the blind hole and a copper plate layer on the lower bump;
etching the copper plate layer to form upper bumps, wherein the upper bumps are arranged in an array;
and forming an upper dielectric layer on the copper plate layer and the upper bump.
10. The method of claim 9, wherein the copper plate layer has a thickness greater than 100 um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810327449.7A CN110381675B (en) | 2018-04-12 | 2018-04-12 | Circuit board structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810327449.7A CN110381675B (en) | 2018-04-12 | 2018-04-12 | Circuit board structure and manufacturing method thereof |
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| Publication Number | Publication Date |
|---|---|
| CN110381675A CN110381675A (en) | 2019-10-25 |
| CN110381675B true CN110381675B (en) | 2021-02-12 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203057685U (en) * | 2013-01-16 | 2013-07-10 | 深圳市牧泰莱电路技术有限公司 | Printed circuit board of super thick copper layer |
| CN104684257A (en) * | 2013-11-29 | 2015-06-03 | 深南电路有限公司 | Processing method of thick copper circuit board |
| CN105188269A (en) * | 2015-10-28 | 2015-12-23 | 广州杰赛科技股份有限公司 | Ultra-thick copper circuit board and manufacturing method thereof |
| CN105575474A (en) * | 2014-10-16 | 2016-05-11 | 扬州俊飞铜业科技有限公司 | Slippage-proof copper-plastic composite band |
| CN206465565U (en) * | 2017-02-08 | 2017-09-05 | 珠海市横琴新区贝格特实业有限公司 | It is a kind of to improve the aluminum-based copper-clad plate for pasting power |
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2018
- 2018-04-12 CN CN201810327449.7A patent/CN110381675B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203057685U (en) * | 2013-01-16 | 2013-07-10 | 深圳市牧泰莱电路技术有限公司 | Printed circuit board of super thick copper layer |
| CN104684257A (en) * | 2013-11-29 | 2015-06-03 | 深南电路有限公司 | Processing method of thick copper circuit board |
| CN105575474A (en) * | 2014-10-16 | 2016-05-11 | 扬州俊飞铜业科技有限公司 | Slippage-proof copper-plastic composite band |
| CN105188269A (en) * | 2015-10-28 | 2015-12-23 | 广州杰赛科技股份有限公司 | Ultra-thick copper circuit board and manufacturing method thereof |
| CN206465565U (en) * | 2017-02-08 | 2017-09-05 | 珠海市横琴新区贝格特实业有限公司 | It is a kind of to improve the aluminum-based copper-clad plate for pasting power |
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| CN110381675A (en) | 2019-10-25 |
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