KR20130016100A - Method for manufacturing wiring board - Google Patents

Abstract

PURPOSE: A wiring board manufacturing method is provided to form a conductive layer using electroplating having a high speed of growth by performing electroless plating. CONSTITUTION: A first process forms a wiring groove in an insulation layer(33). A second process forms a conductive layer(21,22) being a wiring layer. Some of the conductive layer is buried in the wiring groove. The surface of the conductive layer is cut using a cutting tool. A wiring layer(32, 34) is formed.

Description

Manufacturing Method for Wiring Boards {Method For Manufacturing Wiring Board}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a wiring board, and more particularly, to a method of manufacturing a wiring board in which wiring grooves for wiring are formed in an insulating layer and a conductor layer is formed in the wiring grooves.

As a manufacturing method of a wiring board, the semiadditive process is known conventionally, for example. In the semi-additive process, a laminate obtained by stacking a film-shaped insulating resin material containing epoxy resin as a main component on a core substrate is press-heated by a vacuum compression heat press to press the film-shaped insulating resin material to be thermally cured. After the via hole is formed in the insulating resin material of the via hole by laser irradiation or the like, an electroless plating layer is formed on the film-shaped insulating resin material including the inner wall of the via hole. Thereafter, a plating resist is formed on the electroless plating layer in a desired shape, and a wiring pattern having a desired shape is obtained by electroplating using this plating resist as a mask.

However, in recent years, miniaturization of wiring patterns is progressing, and it is difficult to cope with this miniaturization by the semi-additive method. In the semi-additive process, a wiring pattern is formed on a film-shaped insulating resin material. In this case, only the lower surface of the wiring comes into contact with the film-shaped insulating resin material. Therefore, as the wiring pattern becomes finer, the contact area with the film-shaped insulating resin material decreases, so that the adhesive strength becomes weaker, and there is a fear that the wiring pattern is peeled off in the middle of the manufacturing process. Also, as the wiring pattern becomes finer, the contact area with the film-shaped insulating resin material decreases as the wiring pattern decreases, so that the adhesive force is weakened.

Then, as a method of solving the said problem, it is proposed to form wiring by the damascene process (also called a "trench filling process") (for example, refer patent document 1). In the damascene method of patent document 1, the wiring groove which becomes a desired shape by photolithography and an etching is formed in the film-shaped insulating resin material, and a conductor layer is formed in the wiring groove and the film-shaped insulating resin material surface by plating. After the film was formed, the surface of the film-shaped insulating resin material was polished by CMP (Chemical Mechanical Polishing) to remove excess conductor layers other than the inside of the wiring groove.

According to the damascene method as described above, since the wiring is formed in the wiring groove, the lower surface and both side surfaces of the wiring are in contact with the inner wall of the groove formed in the film-shaped insulating resin material, that is, the wiring is formed in the embedded state. Therefore, it is possible to reduce the risk that the wiring or plating resist is peeled off during the manufacturing process.

Patent Document 1: Japanese Patent Application Laid-Open No. 2008-85373

As described above, according to the damascene method, the wiring pattern can be miniaturized. However, since CMP is affected by the shape of the polished surface, some areas of the conductor layer are excessively polished or conversely, the polishing layer is insufficient. In addition, even when the excess conductor layer is removed by a method other than CMP, for example, wet etching, the same problem occurs because the thickness of the plated film formed is not uniform.

In the case where the conductor layer is excessively polished, there is a fear that a problem arises in that the wiring thickness becomes thin and a specified current cannot flow. On the other hand, when polishing of a conductor layer is insufficient, there exists a possibility that the problem of electrically shorting through the remaining conductor layer may arise by the lack of polishing between wiring.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a wiring board which can suppress excessive cutting and short cutting of the conductor layer serving as the wiring layer.

The present invention for achieving the above object is a manufacturing method of a wiring board each having at least one insulating layer and a wiring layer, the first step of forming a wiring groove in the insulating layer, and at least a portion of the wiring groove is embedded And a third step of forming the wiring layer by cutting the surface of the conductor layer with a cutting tool, thereby forming a conductor layer serving as the wiring layer.

According to this invention, the conductor layer used as a wiring layer is formed by making at least one part embed | buried in the wiring groove formed in the insulating layer, and the surface of this conductor layer is cut using a cutting tool. Therefore, when cutting the surface of a conductor layer, since it is hard to be influenced by the shape of an insulating layer and a conductor layer (for example, unevenness | corrugation), cutting shortage of an conductor layer and overcut can be suppressed. Moreover, since it processes by cutting, it is hard to produce the corner slope which can be seen at the time of grinding | polishing to the metal material of a conductor layer. Moreover, since it is hard to be influenced by the shape (for example, unevenness | corrugation) of an insulating layer or a conductor layer, a cutting surface becomes flat. Therefore, even when a plurality of insulating layers and wiring layers are laminated, the surface of the substrate is flat, and generation of defocus during exposure can be suppressed.

In addition, a diamond bite can be used as a cutting tool. Diamond bites have a very high wear resistance and can be used for a long time. Moreover, since the surface roughness after cutting is low, the unevenness | corrugation which arises in the wiring layer surface can be suppressed. Therefore, electrical noise generated in the wiring layer can be reduced. In addition, since the hardness is high, high-speed cutting can be performed, and productivity is improved.

In one embodiment of the present invention, in the third step, a roughened surface can be formed on the insulating layer by cutting the surface of the conductor layer and cutting the surface of the insulating layer. By forming a rough surface in an insulating layer, adhesiveness with the insulating layer laminated | stacked on a cutting surface improves. In addition, since the surface of the insulating layer is cut, it is not necessary to remove the wiring material attached to the surface of the insulating layer by etching when the wiring layer is formed. Therefore, the manufacturing process of the wiring board can be simplified.

In another embodiment of the present invention, the cutting can be performed by dividing a plurality of circuits. By dividing the cutting into multiple circuits, precise cutting is possible. Moreover, even when a conductor layer is thick, it can cut.

In still another aspect of the present invention, the second step is a step of forming a first conductor layer in a wiring groove by electroless plating and a step of forming a second conductor layer on the first conductor layer by electrolytic plating. Can be divided. By carrying out electroless plating on an insulating layer, a conductor layer can be formed by electrolytic plating with a fast film-forming rate. Thus, the productivity of the wiring board is improved.

As explained above, according to this invention, the manufacturing method of the wiring board which can suppress the excessive cutting of the conductor layer used as a wiring layer, or a lack of cutting can be provided.

1 is a cross-sectional view of a wiring board according to an embodiment.
2 is a manufacturing process diagram of a wiring board according to the embodiment (core board process).
3 is a manufacturing process diagram of the wiring board according to the embodiment (build-up process)
4 is a manufacturing process diagram of the wiring board according to the embodiment (build-up process)
5 is a manufacturing process diagram of the wiring board according to the embodiment (build-up process)
6 is a manufacturing process chart of the wiring board according to the embodiment (solder resist layer step).
7 is a manufacturing process diagram (back end process) of the wiring board according to the embodiment;
8 shows an example of polishing by CMP.
9 is a SEM photograph of a cutting surface according to an embodiment

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail, referring drawings. In the following description, the embodiment of the present invention will be described with reference to a wiring board having a buildup layer formed on the core board as an example. However, the wiring board having no core board may be used.

`` Embodiment ''

1 is a cross-sectional view of a wiring board 1 according to the embodiment. The wiring board 1 includes the core board 2, the build-up layer 3 (surface side) and the build-up layer 13 (rear side) formed on both surfaces of the core board 2, and the build-up layer 3, respectively. Formed on the solder resist layer 4 (surface side), the solder resist layer 14 (back side) formed on the buildup layer 13, and the solder bumps formed on the connection terminal T1 of the buildup layer 3. (5) (surface side) and the solder ball 15 (rear side) formed on the connection terminal T11 of the buildup layer 13 are provided.

The core board | substrate 2 is a plate-shaped resin board comprised from a heat resistant resin board (for example, bismaleimide triazine resin board), a fiber reinforced resin board (for example, glass fiber reinforced epoxy resin), etc. The core conductor layers 21 and 22 which form the metal wiring L1 and L11 are formed in the surface and the back surface of the core board | substrate 2, respectively. In addition, through-holes 23 drilled by a drill or the like are formed in the core substrate 2, and through-hole conductors 24 which conduct the core conductor layers 21 and 22 to each other are formed in the inner wall surface thereof. In addition, the through hole 23 is filled with the resin hole filling material 25 such as an epoxy resin.

<Constitution of the surface side>

The buildup layer 3 consists of the resin insulating layers 31 and 33 laminated on the surface side of the core substrate 2 and the wiring layers 32 and 34 formed on the resin insulating layers 31 and 33, respectively. The resin insulating layer 31 is made of a thermosetting resin composition. The wiring groove 31a and the via hole 31b are formed in the resin insulating layer 31 in a desired shape, and the wiring layer 32 forming the metal wiring L2 is formed in the wiring groove 31a and the via hole 31b. ) And via conductors 35 which electrically connect the wiring layer 32 and the core conductor layer 21 to each other are formed by the plating method.

The resin insulating layer 33 consists of a thermosetting resin composition. A wiring groove 33a and a via hole 33b are formed in the resin insulating layer 33 in a desired shape, and the wiring layer 34 having the connection terminal T1 is formed in the wiring groove 33a and the via hole 33b. ) And via conductors 36 which electrically connect the wiring layer 34 and the wiring layer 32 to each other are formed by the plating method. The connection terminal T1 is, for example, a connection terminal for connecting with a semiconductor chip. Further, nickel (Ni) is plated on the surface of the connection terminal T1 by electroless plating, and gold (Au) is further plated on the nickel (Ni) by electroless plating.

The soldering resist layer 4 is formed by laminating a film or liquid solder resist on the surface of the buildup layer 3. In the soldering resist layer 4, the opening 4a which exposes a part of the surface of each connection terminal T1 is formed. Therefore, each connection terminal T1 is in a state where a part of its surface is exposed in the soldering resist layer 4 by the opening 4a. That is, the opening 4a of the solder resist layer 4 has a SMD (Solder Mask Defined) shape in which a part of the surface of each connection terminal T1 is exposed.

In the opening 4a, solder bumps 5 made of solder substantially free of Pb, such as, for example, Sn-Ag, Sn-Cu, Sn-Ag-Cu, and Sn-Sb, are connected to the connection terminal T1. It is formed so as to be electrically connected. In addition, when mounting a semiconductor chip or the like on the surface of the wiring board 1, the solder bumps 5 of the wiring board 1 are reflowed so that the connection terminal T1 of the wiring board 1 and the connection terminal of the semiconductor chip, etc. Is electrically connected.

<Constitution of the back side>

The buildup layer 13 is composed of the resin insulating layers 131 and 133 laminated on the back surface side of the core substrate 2 and the wiring layers 132 and 134 formed on the resin insulating layers 131 and 133, respectively. The resin insulating layer 131 is made of a thermosetting resin composition. A wiring groove 131a and a via hole 131b are formed in the resin insulating layer 131 in a desired shape, and the wiring layer 132 forming the metal wiring L12 is formed in the wiring groove 131a and the via hole 131b. ) And a via conductor 135 that electrically connects the wiring layer 132 and the core conductor layer 22 are formed by the plating method.

The resin insulating layer 133 is made of a thermosetting resin composition. A wiring groove 133a and a via hole 133b are formed in the resin insulating layer 133 in a desired shape, and a wiring layer 134 having a connection terminal T11 in the wiring groove 133a and the via hole 133b. ) And a via conductor 136 which electrically connects the wiring layer 134 and the wiring layer 132 with the plating method. The connection terminal T11 is a connection terminal which connects with a main board, a socket, etc. (henceforth "main board etc."), for example. Further, nickel (Ni) is plated on the surface of the connection terminal T11 by electroless plating, and gold (Au) is further plated on the nickel (Ni) by electroless plating.

The solder resist layer 14 is formed by laminating a film-like or liquid solder resist on the surface of the buildup layer 13. The solder resist layer 14 is formed with an opening 14a exposing a part of the surface of each connection terminal T11. Therefore, each connection terminal T11 is in a state in which a part of its surface is exposed in the solder resist layer 14 by the opening 14a. That is, the opening 14a of the soldering resist layer 14 is a SMD shape which exposed a part of surface of each connection terminal T11.

In the opening 14a, solder balls 15 made of solder substantially free of Pb, such as Sn-Ag, Sn-Cu, Sn-Ag-Cu, Sn-Sb, and the like, are connected to the connection terminal T11. It is formed so as to be electrically connected. When the main board or the like is mounted on the back surface of the wiring board 1, the solder balls 15 of the wiring board 1 are reflowed to connect the terminal T11 of the wiring board 1 with the connection terminal of the main board or the like. Is electrically connected.

<Method of manufacturing wiring board 1>

2 to 4 are diagrams for explaining the manufacturing process of the wiring board 1 described with reference to FIG. Hereinafter, the manufacturing method of the wiring board 1 is demonstrated with reference to FIGS.

(Core substrate process: Fig. 2)

The copper clad laminated board which copper foil adhered to the surface and back surface of a plate-shaped resin substrate is prepared. Further, punching processing is performed on the copper clad laminate using a drill to form through holes serving as through holes 23 at predetermined positions. And through-hole electroplating and electrolytic copper plating are performed according to the conventional well-known method, the through-hole conductor 24 is formed in the inside wall of the through-hole 23, and the copper plating layer is formed in both surfaces of a copper clad laminated board (FIG. 2 ( a) reference}.

Thereafter, the inside of the through hole conductor 24 is filled with a hole filling material 25 made of resin such as an epoxy resin. In addition, the core substrate is formed by etching the copper plating layers formed on the copper foils on both sides of the copper clad laminate in a desired shape to form the core conductor layers 21 and 22, respectively, on the front and back surfaces of the copper clad laminate to form the metal wirings L1 and L11. (2) is obtained (see Fig. 2 (b)). In addition, after forming the through hole 23, it is preferable to perform the desmear process which removes the smear of a process part.

(Build-up process: FIGS. 3-5)

On the front and back surfaces of the core substrate 2, film-shaped insulating resin materials containing epoxy resins serving as the resin insulating layers 31 and 131 as main components are arranged to overlap each other. Then, the laminate is pressurized with a vacuum press hot press to press the film while insulating a film-shaped insulating resin material. Subsequently, laser irradiation is performed using a conventionally known laser processing apparatus to form wiring grooves 31a and 131a and via holes 31b and 131b in the resin insulating layers 31 and 131, respectively (Fig. 3 (a)). Reference}. After the wiring grooves 31a and 131a and the via holes 31b and 131b are formed, a process of roughening the surfaces of the wiring grooves 31a and 131a and the via holes 31b and 131b is performed. In addition, the wiring grooves 31a and 131a and the via holes 31b and 131b may be formed by exposure and development.

Subsequently, electroless plating is performed on the surfaces of the resin insulating layers 31 and 131 including the wiring grooves 31a and 131a and the via holes 31b and 131b, respectively, to form the wiring grooves 31a and 131a and the via holes 31b, respectively. An electroless copper plating layer (first conductor layer) C1 is formed on the surfaces of the resin insulating layers 31 and 131 including the inside of 131b). Next, electrolytic plating is performed to form an electrolytic copper plating layer (second conductor layer) C2 on the electroless copper plating layer C1 (see Fig. 3 (b)).

Then, the conductor layer composed of the electroless copper plating layer (C1) and the electrolytic copper plating layer (C2) is cut into a plurality of circuits in the thickness direction by using a diamond bite, so that the extra electroless copper plating layer (C1) and the electrolytic copper plating layer are cut. (C2) is removed (see FIG. 4 (a)) to obtain wiring layers 32 and 132 and via conductors 35 and 135 (see FIG. 4 (b)). In addition, after FIG.4 (a), the electroless copper plating layer (C1) and the electrolytic copper plating layer (C2) are described as one layer.

In Fig. 4 (a), the extra electroless copper plating layer C1 and the electrolytic copper plating layer C2 are cut by the predetermined thickness from the surface side until the cutting surfaces A1 to A3 are positioned in three times. . In the third cutting process, when the surfaces of the electroless copper plating layer C1 and the electrolytic copper plating layer C2 are cut, the surfaces of the resin insulating layers 31 and 131, which are insulating layers, are also cut to the surfaces of the resin insulating layers 31 and 131. A rough surface is formed.

By cutting a plurality of circuits, more precise cutting is possible. Moreover, by dividing into multiple circuits, it can cut also when the electroless copper plating layer C1 and the electrolytic copper plating layer C2 are thick. In addition, by forming a roughened surface on the surfaces of the resin insulating layers 31 and 131, the adhesion to the resin insulating layers 33 and 133 laminated on the resin insulating layers 31 and 131 is improved. In addition, since the surfaces of the resin insulating layers 31 and 131 are cut, the step of removing the wiring material (copper) adhered to the surfaces of the resin insulating layers 31 and 131 by etching can be omitted, thereby producing the wiring board 1. The process can be simplified. In addition, cutting of an electroless copper plating layer C1 and an electrolytic copper plating layer C2 can be performed using a commercially available cutting device, for example, FS8910 by DISCO.

On the resin insulating layers 31 and 131 whose surface is roughened, the film-shaped insulating resin material which has the epoxy resin used as the resin insulating layers 33 and 133 as a main component is respectively overlapped. Then, the laminate is pressurized and heated with a vacuum press heat press to press the film while insulating the insulating resin material in a thermosetting manner. Subsequently, laser irradiation is performed using a conventionally known laser processing apparatus to form wiring grooves 33a and 133a and via holes 33b and 133b in the resin insulating layers 33 and 133, respectively (Fig. 5 (a)). Reference}. After the wiring grooves 33a and 133a and the via holes 33b and 133b are formed, a process of matching the surfaces of the wiring grooves 33a and 133a and the via holes 33b and 133b is performed. Further, the wiring grooves 33a and 133a and the via holes 33b and 133b may be formed by exposure and development.

Subsequently, in the same manner as when the wiring layers 32 and 132 and the via conductors 35 and 135 are obtained, the surfaces of the resin insulating layers 33 and 133 including the wiring grooves 33a and 133a and the via holes 33b and 133b are electrically charged. The plating is carried out, and electroplating is performed thereon. Thereafter, the electroless copper plating layer and the electrolytic copper plating layer are cut using the diamond bite, thereby removing the extra electroless copper plating layer and the electrolytic copper plating layer to obtain the wiring layers 34 and 134 and the via conductors 36 and 136 (Fig. 5 (b). ) Reference}.

In this case as well, the electroless copper plating layer (C1) and the electrolytic copper plating layer (C2) are preferably divided into a plurality of circuits as in the case of cutting. In addition, it is preferable that the surfaces of the resin insulating layers 33 and 133 serving as the insulating layers are also cut to form a roughened surface. By forming a rough surface on the surfaces of the resin insulating layers 33 and 133, the adhesion to the solder resist layers 4 and 14 is improved.

Solder Resist Layer Process: FIG. 6

The film-type soldering resist is pressed and laminated on the buildup layers 3 and 13 having the connecting terminals T1 and T11 respectively at the surface layer. A solder resist layer having SMD-shaped openings 4a and 14a for exposing and developing a film-shaped solder resist laminated on the buildup layers 3 and 13 to expose a part of the connection terminals T1 and T11, respectively. 4,14). Then, nickel (Ni) and gold (Au) are plated on the surfaces of the connection terminals T1 and T11 by electroless plating.

(Back end process: FIG. 7)

Solder paste is applied to the surfaces of the connection terminals T1 and T11 exposed at the openings 4a and 14a formed in the solder resist layers 4 and 14 by solder printing, and then reflowed at a predetermined temperature and time. The solder bumps 5 and the solder balls 15 electrically connected to the connection terminals T1 and T11 are formed.

As mentioned above, since the wiring board 1 which concerns on embodiment cuts the copper plating layer (conductor layer) used as the wiring layers 32, 34, 132, and 134 using a diamond bite, the wiring layers 32, 34, 132, 134 and resin insulation which are the cutting objects are cut. The shape (for example, irregularities) of the layers 31, 33, 131, 133 is hardly affected. Therefore, the cutting shortage and excess cutting of the conductor layer used as the wiring layers 32, 34, 132, and 134 can be suppressed.

In particular, in the case of polishing by CMP, when removing the conductor layer formed on the groove having a rectangular bottom surface area having a dimension in the planar direction of 7 mm x 5 mm or more, a recess is likely to occur on the wiring layer upper surface after polishing. . This is because, as shown in Fig. 8A, the conductor layer 203 formed on the groove 202 having the rectangular bottom surface area 201 having a dimension in the planar direction of 7 mm x 5 mm or more is formed on the upper surface thereof. This is because the concave portion 204 is often formed and the concave portion 204 cannot be removed because the shape of the conductor layer 203 before polishing is affected by polishing by CMP. ) Itself becomes smaller but cannot be removed}. Therefore, as shown in Fig. 8B, in the polishing by CMP, the recess 204 remains on the upper surface of the wiring layer 205 after polishing. Further, the recess 204 remains even if the groove 202 has at least the bottom area of the above-described dimensions, even if the planar shape of the groove 202 is circular or elliptical other than rectangular.

On the other hand, when cutting using a diamond bite like the wiring board 1 of this embodiment, it is hard to be influenced by the shape (for example, unevenness | corrugation) of the conductor layer 203 which is a cutting object as mentioned above. Therefore, as shown in Fig. 8C, even if there is little concave portion 204 or the concave portion 204 is formed on the upper surface after cutting, the wiring layer 205 having a depth of 0.5 mu m or less can be obtained. .

Moreover, since it processes by cutting, it is hard to produce the corner slope which can be seen at the time of grinding | polishing to the metal material of a conductor layer. In addition, since the shape of the conductor layer and the resin insulating layers 31, 33, 131, and 133, which are the wiring layers 32, 34, 132, and 134 to be cut, is hardly affected, the cutting surface becomes flat. Therefore, even when a plurality of resin insulating layers and wiring layers are laminated, the surface of the substrate becomes flat, and defocus during exposure is unlikely to occur.

Moreover, since a diamond bite is used as a cutting tool, it can be used for a long time. Moreover, since the surface roughness after cutting is low, the unevenness | corrugation which arises in the surface of the wiring layer 32, 34, 132, 134 can be suppressed. Therefore, electrical noise generated in the wiring layers 32, 34, 132, and 134 can be reduced. In addition, since the hardness is high, high-speed cutting can be performed, and productivity is improved.

When cutting the surface of the conductor layer serving as the wiring layers 32, 34, 132 and 134, the surface of the resin insulating layers 31, 33, 131 and 133 is also cut to form roughened surfaces on the resin insulating layers 31, 33, 131 and 133. Therefore, adhesiveness with the resin insulating layers 33 and 133 and the soldering resist layers 4 and 14 laminated | stacked improves. In addition, since the surfaces of the resin insulating layers 31, 33, 131, 133 are cut, it is not necessary to remove the wiring material (copper plating layer) adhered to the surfaces of the resin insulating layers 31, 33, 131, 133 by etching. Therefore, the manufacturing process of the wiring board 1 can be simplified.

In addition, since the cutting is performed by dividing a plurality of circuits, precise cutting is possible. Moreover, even when the copper plating layer (conductor layer) formed by plating is thick, it can cut. Furthermore, after electroless copper plating is formed by electroless plating, an electrolytic copper plating layer is formed by electrolytic plating with a fast film formation rate. Therefore, the productivity of the wiring board 1 is improved.

[Example 1]

Next, an Example is described.

In this embodiment, a sample obtained by cutting a diamond bite into a copper plated layer formed to be embedded in a wiring groove of a resin insulating layer is prepared according to the above-described manufacturing method, and the cutting surface of the sample is observed with a scanning electron microscope (SEM) apparatus. It was.

<Making of sample>

MEANS TO SOLVE THE PROBLEM The present inventors arrange | positions the film-shaped insulated resin material which has an epoxy resin as a main component laminated | stacked on the surface of the plate-shaped resin substrate used as a core board | substrate, and pressurizes and heats this laminated body with a vacuum compression hot press, and the film-shaped insulated resin is carried out. The material was pressed while thermosetting. Thereafter, laser irradiation is performed using a laser processing apparatus to form wiring grooves in the thermosetting insulating resin material, and electroless plating and electrolytic plating are performed to form a copper plating layer on the surface of the insulating resin material including the wiring grooves. Formed. Then, the wiring layer was formed in the wiring groove by cutting the copper plating layer using FS8910 by DISCO Corporation. In addition, the cutting used the diamond bite.

<Cutting surface of sample>

9 is an SEM photograph of a cutting surface. As shown in FIG. 9, it is understood that the cutting surface (in particular, the boundary between the copper plating layer X and the insulating resin material Y having different materials) does not show irregularities and is in a good state. Moreover, what is called a grinding | polishing corner slope also did not arise. As mentioned above, according to the manufacturing method of the wiring board 1 which concerns on embodiment, it is hard to be influenced by the shape (for example, unevenness | corrugation) of the conductor layer and resin insulating layer which are cutting objects, and the favorable cutting surface without unevenness is obtained. I could see.

<Other embodiment>

As mentioned above, although this invention was demonstrated in detail, giving a specific example, this invention is not limited to the above-mentioned content, A various deformation | transformation and a change are possible as long as it does not deviate from the range of this invention. For example, in the above-described embodiment, the form in which the wiring board 1 is a BGA substrate connected to the main board or the like through the solder ball 15 has been described, but a so-called pin or land is formed instead of the solder ball 15. The wiring board 1 as a PGA (Pin Grid Array) substrate or a LGA Array board may be connected to a main board or the like.

In the above embodiment, the solder resist opening has a so-called SMD (Solder Mask Defined) shape in which a part of the surface of the connection terminal is exposed, but a so-called non-solder mask in which all of the surface of the connection terminal is exposed. The shape may be defined. In the above embodiment, the conductor layer is cut in three times, but the number of cuttings is not limited to three times but can be set to an optimum number of cuttings.

1-Wiring Board 2-Core Board
3-buildup layer 4-solder resist layer
4a-opening 5-solder ball
13-Buildup Layer 14-Solder Resist Layer
14a-opening 15-solder balls
21,22-Core Conductor Layer 23-Through Hole
24-Through Hole Conductor 25-Resin Landfill
31,33-Resin Insulation Layer 31a, 33a-Wiring Groove
32,34-Wiring Layer 35,36-Via Conductor
131,133-Resin Insulation Layer 131a, 133a-Wiring Groove
132,134-Wiring Layer 135, 136-Via Conductor
201-Bottom Area 202-Home
203-Conductor layer 204-Recess
205-Wiring Layer L1, L2-Metal Wiring
L11, L12-Metal Wiring T1, T11-Connection Terminal

Claims (6)

As a manufacturing method of a wiring board which has one or more insulating layers and wiring layers, respectively,
A first step of forming a wiring groove in the insulating layer,
A second step of forming a conductor layer serving as the wiring layer by embedding at least a portion in the wiring groove;
And a third step of forming the wiring layer by cutting the surface of the conductor layer with a cutting tool.
The method according to claim 1,
And said third step uses a diamond bite as said cutting tool.
The method according to claim 1,
And wherein said third step cuts the surface of said conductor layer and simultaneously cuts the surface of said insulating layer to form a roughened surface on said insulating layer.
The method according to claim 2,
And wherein said third step cuts the surface of said conductor layer and simultaneously cuts the surface of said insulating layer to form a roughened surface on said insulating layer.
The method according to any one of claims 1 to 4,
And the third step is to cut a plurality of circuits.
The method according to claim 1,
The second step includes a step of forming a first conductor layer in the wiring groove by electroless plating, and a step of forming a second conductor layer on the first conductor layer by electrolytic plating. Method of manufacturing a substrate.

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