KR100771293B1 - Printed circuit board and method for manufacturing the same - Google Patents

Abstract

A printed circuit board and a manufacturing method thereof are provided to form easily a micro circuit pattern by minimizing an amount of etching on a plating layer, when an unnecessary seed layer is removed. A printed circuit board includes a base substrate, an outerlayer circuit pattern(180), and a solder resist pattern(190). At least one inner circuit pattern is formed inside an insulation layer in the base substrate. The outerlayer circuit pattern is formed on at least one surface of the base substrate and electrically connected to the innerlayer circuit pattern. The outerlayer circuit pattern includes a metal layer and a metal protective layer which is formed on the metal layer. The solder resist pattern is formed on the outerlayer circuit pattern such that at least a portion of the outerlayer circuit pattern is exposed. Different etching conditions are applied on the metal protective layer and the metal layer.

Description

Printed Circuit Board and Method for manufacturing the same

1A to 1E are process diagrams illustrating a method of manufacturing a printed circuit board according to a conventional example.

2A is a cross-sectional view illustrating a printed circuit board in which a failure of an outer layer circuit pattern occurs in a conventional printed circuit board.

2B is a plan view illustrating a printed circuit board in which a failure of an outer layer circuit pattern occurs in a conventional printed circuit board.

3 is a cross-sectional view illustrating a printed circuit board according to an exemplary embodiment of the present invention.

4 is a flowchart illustrating a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention.

5A to 5M are process diagrams illustrating a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: copper foil laminated plate 110, 130: insulating layer

112: copper foil layer 114: internal via hole

116 plating layer 120 inner circuit pattern

132: blind via hole 140: seed layer

150: outer layer resist pattern 160: copper plating layer

170: metal protective layer 180: outer circuit pattern

190: solder resist pattern 200: printed circuit board

The present invention relates to a printed circuit board and a method of manufacturing the same, and more particularly, to a printed circuit board and a method of manufacturing a metal protective layer on the upper surface of the plating layer for forming the outer circuit pattern.

Printed Circuit Board (PCB) is a printed wiring board that forms conductors on insulating boards based on circuit design. The electrical wiring between electronic components is called a PCB board, printed circuit board, or printed wiring board. . In general, a printed circuit board is formed by attaching a copper thin plate to a surface of a phenol resin insulator or an epoxy resin insulator, and then etching it according to the wiring pattern of the circuit to form a necessary circuit, and various electrical and electronic devices such as IC, capacitor, and resistor thereon. It is an insulating flat plate that allows compact mounting of parts. That is, a circuit for connecting the electronic components with each other is formed in the shape of a wiring diagram on the surface of the insulating plate. Printed circuit boards are classified into single-sided boards, double-sided boards, and multi-layered boards according to the number of wiring circuit boards. The more layers, the better the mounting force of the parts and they are used for high precision products.

Single-sided printed circuit boards mainly use phenolic discs as substrates, and are used in products such as TVs, radios, audios, telephones, and other simple household electronics and instruments, which are relatively intricate in circuit configuration. The double-sided printed circuit board mainly uses a plate made of epoxy resin and is used for relatively complicated circuits such as color TV, VTR, and facsimile. In addition, multilayer printed circuit boards are used in high-precision devices, such as 32-bit or more computers, electronic switchgear, high-performance communication equipment.

On the other hand, electronic devices are becoming smaller and more versatile, and the types of resistors and capacitors mounted on the boards are also manufactured in very small sizes and are used as elements of multilayer printed circuit boards. For this reason, it is becoming thinner and more precise, and thus requires various technologies.

1A to 1E are process diagrams illustrating a method of manufacturing a printed circuit board according to a conventional example, which will be described with reference to the drawings.

First, as shown in FIG. 1A, circuit patterns 2 electrically connected to each other are formed on both surfaces of the insulating layer 1, and the insulating layers 3 are stacked.

Thereafter, as shown in FIG. 1B, the blind via hole 4 is formed in the insulating layer 3 and the seed layer 5 is formed by performing electroless copper plating.

Next, as shown in FIG. 1C, the resist pattern 6 is formed on the top surface of the seed layer 5, and the plating layer 7 is formed by performing electrolytic copper plating.

At this time, since the plating layer 7 is later etched together during the etching process of the seed layer 5 corresponding to the resist pattern 6, the plating layer 7 is formed to have a sufficient height in consideration of the height to be removed during the etching process.

Thereafter, as shown in FIG. 1D, the resist pattern 6 is removed and the exposed seed layer 5 is etched to form the outer circuit pattern 8.

Next, as shown in FIG. 1E, by forming a solder resist pattern 9 for protecting the remaining outer circuit pattern 8 except for a region connected to an external terminal among the outer circuit patterns 8, a printed circuit The substrate 10 is completed.

As described above, in the conventional method of manufacturing a printed circuit board, in order to form a high-density outer circuit pattern 8, the seed layer 5 is formed on the upper surface of the insulating layer 3, and the resist pattern 6 is formed. After the formation, the plating layer 7 is formed by electrolytic copper plating, and the resist pattern 6 and the seed layer 5 corresponding to the resist pattern 6 are removed. At this time, since the seed layer 5 and the plating layer 7 are all formed of copper, when the etching process is performed to remove the seed layer 5 corresponding to the resist pattern 6, the plating layer 7 is partially removed. Removed. Therefore, when the plating layer 7 is formed, there is a problem in that it must be further formed by a height to be removed by an etching process performed to remove the seed layer 5 corresponding to the resist pattern 6.

In addition, if the plating layer 7 is further formed at the desired height by the height to be removed at the maximum during the etching process, the surface area of the plating layer 7 exposed to the etching solution becomes wide when the etching process is performed, and thus the attack of the etching solution ( Since a large number of attacks were received, there was a problem of causing a failure of the outer circuit pattern 8.

2A and 2B illustrate a cross-sectional view and a plan view of a printed circuit board on which a failure of an outer layer circuit pattern occurs in a conventional printed circuit board. Referring to FIG. 2A, a circuit pattern is formed when a seed layer 5 is laminated. A circuit pattern 8 in which an undercut is formed by overetching the side surface of the plating layer 7 is illustrated, and FIG. 2B shows the interlayer delamination between the outer circuit pattern 8 and the insulating layer 3 due to the undercut. This has occurred and shows that the outer circuit pattern 8 is separated.

As described above, the plating layer 7 must be formed larger than the desired plating layer in consideration of the etching amount of the plating layer 7 generated during the etching of the seed layer 5, thereby limiting the implementation of high density and miniaturization of a printed circuit board. In the case where the size of the plating layer 7 is made small to form a fine circuit pattern, defects such as short circuits occur between wires, which greatly reduces the reliability of the printed circuit board.

In order to solve the above problems, the present invention minimizes the attack of the etchant applied to the plating layer in the seed layer etching process for forming the outer layer circuit pattern, thereby reducing the defect of the circuit pattern, thereby improving reliability of the printed circuit board. Provided are a printed circuit board and a method of manufacturing the same.

The present invention also provides a printed circuit board and a method of manufacturing the same to form a fine circuit pattern by forming a plating layer only to a desired size irrespective of the attack of the etching liquid generated during the seed layer etching process in order to solve the problems described above. to provide.

In order to solve the above technical problem, the present invention, the base substrate formed with at least one inner circuit pattern in the insulating layer; An outer circuit pattern formed on at least one surface of the base substrate and electrically connected to the inner circuit pattern and including a metal layer and a metal protective layer formed on an upper surface of the metal layer; And a solder resist pattern formed to expose at least a portion of the outer circuit pattern on an upper surface of the outer circuit pattern, wherein the metal protective layer has different etching requirements from the metal layer.

In the printed circuit board according to the present invention, the metal protective layer is characterized by different etching requirements from the metal layer.

In the printed circuit board according to the present invention, the metal protective layer is thinner than the metal layer.

In addition, in the printed circuit board according to the present invention, the metal layer is characterized in that the copper layer.

In addition, in the printed circuit board according to the present invention, the metal layer is characterized by consisting of a seed layer and a plating layer.

In the printed circuit board according to the present invention, the solder resist pattern is formed of an insulating material.

In order to solve the above technical problem, the present invention, (A) at least one inner layer circuit pattern to form a via hole in the insulating layer formed therein to provide a base substrate, (B) a seed layer on at least one surface of the base substrate Forming a plating layer by (C) forming an outer layer resist pattern on an upper surface of the seed layer and performing electroplating, (D) forming a metal protective layer on an upper surface of the plating layer, and (E) forming an outer layer resist pattern Removing and removing the exposed seed layer to form an outer circuit pattern electrically connected to the inner circuit pattern, and (F) forming a solder resist pattern to expose some outer circuit patterns on the upper surface of the outer circuit pattern. It includes, and provides a method of manufacturing a printed circuit board, characterized in that the metal protective layer is not removed in step (E).

In the method of manufacturing a printed circuit board according to the present invention, the metal protective layer is characterized in that the seed layer and the etching requirements are different.

In the method of manufacturing a printed circuit board according to the present invention, the seed layer and the plating layer are formed of the same metal layer.

In the method of manufacturing a printed circuit board according to the present invention, the seed layer and the plating layer are formed of copper.

In the method of manufacturing a printed circuit board according to the present invention, the metal protective layer is formed of at least one of nickel, tin, gold, platinum, and zinc.

In addition, in the method of manufacturing a printed circuit board according to the present invention, after the step (E), (G) further comprises the step of forming an outer circuit pattern consisting of a seed layer and a plating layer by removing the metal protective layer. It is done.

EMBODIMENT OF THE INVENTION Hereinafter, preferred embodiment of this invention is described with reference to an accompanying drawing.

3 is a cross-sectional view of a printed circuit board according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the printed circuit board 200 according to the exemplary embodiment of the present invention is formed on a base substrate and an upper surface of the base substrate on which at least one inner layer circuit pattern 120 is formed in the insulating layer 130. An outer circuit pattern 180 electrically connected to the inner circuit pattern 120 of the base substrate and including the metal layers 140 and 160 and the metal protective layer 170, and an outer circuit pattern on the upper surface of the outer circuit pattern 180. The solder resist pattern 190 is formed to expose at least a portion of the 180.

Here, since the insulating layer 110 is formed between the internal circuit patterns 120 formed in the insulating layer 130 of the base substrate, the via holes 114 are formed in the internal circuit patterns 120 to be electrically connected to each other. do.

The metal layers 140 and 160 forming the outer circuit pattern 180 may be formed of the seed layer 140 and the copper plating layer 160. In this case, the seed layer 140 and the copper plating layer 160 may be formed of the same metal, for example, copper. It is preferable to form. In addition, the metal protective layer 170 is formed of a metal having a different etching requirement from the seed layer 140 and the copper plating layer 160 to a thickness thinner than the metal layers 140 and 160. For example, it may be formed of nickel, tin, gold, platinum, zinc, or the like.

The solder resist pattern 190 is formed to protect the remaining outer circuit pattern 180 except for a part of the outer circuit pattern 180 connected to the external terminal, and is formed of an insulating material.

4 to 5 are views illustrating a method of manufacturing a printed circuit board according to an embodiment of the present invention.

4 is a flowchart illustrating a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention, and FIGS. 5A to 5M are detailed flowcharts illustrating a method of manufacturing a printed circuit board according to FIG. 4.

First, a manufacturing method of a printed circuit board according to an exemplary embodiment of the present invention will be described with reference to FIG. 4.

A base substrate is provided (S100).

The base substrate may be formed by forming an inner circuit pattern on at least one surface of a copper foil laminated plate having a copper foil layer formed thereon, stacking an insulating layer in a semi-cured state, and forming a via hole corresponding to the circuit pattern.

Here, the via hole may include a through hole penetrating the base substrate using a mechanical drill such as a Computer Numerical Control Drill, and a blind via hole formed in an insulating layer corresponding to a circuit pattern using a laser drill.

Thereafter, a seed layer is formed on at least one surface of the base substrate (S200).

The seed layer is a pretreatment for forming an outer circuit pattern in the insulating layer and a plating layer in the via hole, and may be formed of electroless copper plating to impart conductivity to the surface of the insulating layer.

Next, an outer layer resist pattern is formed on the seed layer upper surface and a plating layer is formed (S300).

The outer layer resist pattern is formed with a pattern corresponding to the outer layer circuit pattern. For example, the outer layer resist pattern may be formed by a photolithography method using a photosensitive material. When electrolytic copper plating is performed on the outer layer resist pattern thus formed, a copper plating layer is formed between the outer layer resist patterns, thereby forming a copper metal layer together with the seed layer.

After that, a metal protective layer is formed on the plating layer (S400).

The metal protective layer formed on the upper surface of the plating layer is for protecting the plating layer when the seed layer is removed, and is formed of a metal different from the metal constituting the seed layer and the plating layer. For example, when the seed layer and the plating layer are formed of electroless copper plating and electrolytic copper plating, the metal protective layer may be formed of nickel plating to protect the plating layer.

If the metal protective layer having a different metal layer from the plating layer is formed on the upper surface of the plating layer, the surface area of the plating layer exposed by the metal protective layer is small even if an etching process is performed to remove a part of the seed layer where the plating layer and the metal component are the same. Therefore, the defect of the plating layer due to overetching can be minimized. Therefore, it is possible to bring about an effect of forming a desired fine outer layer circuit pattern without further forming a margin of the plating layer which is etched together when removing the seed layer.

At this time, the metal protective layer may be formed by electroless plating, but it is preferable that the metal protective layer is formed by electroplating and formed only on the upper surface of the plating layer.

Next, the outer layer resist pattern is removed and the exposed seed layer is removed to form an outer layer circuit pattern electrically connected to the circuit pattern of the base substrate (S500).

After removing the outer layer resist pattern, the exposed seed layer is removed by etching to form an outer layer circuit pattern including a copper metal layer and a metal protective layer formed of the seed layer and the plating layer. At this time, when the exposed seed layer is removed, the plating layer may be exposed to only a minimum portion by the metal protective layer, thereby forming a desired fine outer circuit pattern without defects due to overetching.

The outer circuit pattern may be electrically connected to the inner circuit pattern formed in the insulating layer by the via hole.

Thereafter, a solder resist pattern is formed on the upper surface of the outer circuit pattern to expose a portion of the outer circuit pattern to form a printed circuit board (S600).

The solder resist pattern is intended to protect the remaining outer circuit pattern except for some outer circuit patterns in which components are mounted in the outer circuit pattern, and then, the solder resist pattern is preferably formed of a heat resistant resin that can sufficiently withstand the melting temperature of the connection terminal.

At this time, according to the embodiment, after removing the metal protective layer may form a solder resist pattern.

As described above, in the method of manufacturing a printed circuit board according to the present invention, in order to form an outer circuit pattern on the upper surface of the insulating layer, a seed layer is formed of electroless copper plating, and after forming an outer layer resist pattern, the copper plating layer In addition, by forming a metal protective layer on the upper surface of the copper plating layer, even if the etching process for removing the seed layer exposed during the removal of the outer layer resist pattern is carried out, the copper plating layer is protected by the metal protective layer so that it is desired without defects on overetching. Only the copper plating layer may be formed to bring about an effect of forming a fine outer circuit pattern.

5A to 5M are process diagrams illustrating a method of manufacturing a printed circuit board according to an exemplary embodiment of the present invention.

First, as shown in FIG. 5A, the copper foil laminated plate 100 having the copper foil layer 112 interposed on both surfaces of the insulating layer 110 is provided.

Here, it is preferable to use the resin layer including the reinforcing base material such that the insulating layer 110 has sufficient mechanical strength as well as electrical characteristics and small dimensional change due to temperature.

Thereafter, as illustrated in FIG. 5B, an inner via hole 114 is formed in the copper-clad laminate 100.

The inner via hole 114 is for electrically connecting the inner circuit patterns to be formed on both sides of the insulating layer 110 to each other. For example, the inner via hole 114 may be formed by mechanical drilling such as a CNC drill.

Next, as shown in FIG. 5C, the plating layer 116 is formed on the copper-clad laminate 100 having the inner via hole 114 formed thereon.

Since the inner via hole 114 includes the insulating layer 110 on the inner wall, electrolytic plating and electrolytic plating may be performed to form the plating layer 116 to impart conductivity to the inner via hole 114.

Here, the electrolytic copper plating after electroless copper plating is performed because electrolytic copper plating by electrolysis cannot be directly performed on the insulating layer 110. Therefore, after performing electroless copper plating, which is chemical copper plating, electrolytic copper plating may be performed to form the plating layer 116. In addition, electroless copper plating alone makes it difficult to thicken the plating film, and it is preferable that the electrolytic copper plating is performed together since the physical properties thereof do not reach the electrolytic copper plating.

Thereafter, as illustrated in FIG. 5D, the inner circuit pattern 120 is formed on the copper foil layer 112 on which the plating layer 116 is formed.

For example, the inner circuit pattern 120 may be formed by applying a photosensitive material (not shown) to the upper surface of the copper foil layer 112 on which the plating layer 116 is formed, adhering the artwork film on which the pattern is formed, and then performing exposure and development processes. By forming an etching resist pattern may be formed by a photolithography method that performs an etching process.

In this case, the inner circuit patterns 120 formed on both surfaces of the insulating layer 110 may be electrically connected to each other by the inner via hole 114 in which the plating layer 116 is formed.

Next, as shown in FIG. 5E, the insulating layer 130 is stacked on the upper surface of the inner circuit pattern 120.

In this case, the insulating layer 130 is preferably a prepreg made by penetrating the thermosetting resin into the glass fiber and made into a semi-cured state. ) It can be easily stacked on the upper surface.

Subsequently, as illustrated in FIG. 5F, a blind via hole 132 corresponding to the inner circuit pattern 120 is formed in the insulating layer 130 to form the base substrate 135.

The blind via hole 132 is for electrically connecting the inner circuit pattern 120 and the outer circuit pattern to be formed later. The blind via hole 132 may be formed using a laser drill such as a co2 laser drill in a portion corresponding to the inner circuit pattern 120. Can be.

According to an embodiment, through holes (not shown) penetrating the base substrate 135 may be further formed in the base substrate 135 using a mechanical drill.

Next, as shown in FIG. 5G, the seed layer 140 is formed on both surfaces of the base substrate 135.

The seed layer 140 is a pretreatment process for forming a plating layer for forming an outer circuit pattern. Since the plating layer by electrolysis cannot be directly performed on the upper surface of the insulating layer 130, the seed layer is formed by performing electroless plating. 140 is first formed.

Here, the seed layer 140 is preferably formed of an electroless copper plating using copper (Cu).

Subsequently, as shown in FIG. 5H, an outer layer resist pattern 150 for an outer layer circuit pattern is formed on the seed layer 140.

The outer layer resist pattern 150 may be formed using, for example, a photosensitive material so that a portion corresponding to the outer layer circuit pattern is opened.

Next, as shown in FIG. 5I, a copper plating layer 160 is formed on the top surface of the seed layer 140 on which the outer layer resist pattern 150 is formed.

The copper plating layer 160 is formed on the top surface of the seed layer 140 in an open space in the outer layer resist pattern 150 to form an outer layer circuit pattern.

Here, the copper plating layer 160 is preferably formed by electrolytic copper plating using copper (Cu) to form a copper metal layer together with the seed layer 140.

Thereafter, as shown in FIG. 5J, the metal protective layer 170 is formed on the upper surface of the copper plating layer 160.

The metal protective layer 170 is for protecting the copper plating layer 160 when the etching process for removing the seed layer 140 is performed, and the metal protective layer 170 is the seed layer 140 and the copper plating layer 160. ) And other metal layers. For example, the metal protective layer 170 may be formed of nickel, tin, gold, platinum, zinc, or the like, rather than copper (Cu) forming the seed layer 140 and the copper plating layer 160.

If the seed layer 140 and the copper plating layer 160 and the metal protective layer 170 different from the metal component is formed on the upper surface of the copper plating layer 160, the seed layer 140 having the same metal component as the copper plating layer 160 is formed. Even if the etching process is performed to remove a portion of the metal sheet), since the surface area of the copper plating layer 160 exposed by the metal protective layer 170 is small, defects of the plating layer due to overetching may be minimized. Therefore, even when the seed layer 140 is removed, an additional portion of the copper plating layer 160 which is etched together may not be further formed, thereby forming the desired fine outer circuit pattern.

In this case, the metal protective layer 170 may be formed by electroless plating, but preferably, the metal protective layer 170 is formed by electroplating and formed only on the upper surface of the copper plating layer 160.

Next, as shown in FIG. 5K, the outer layer resist pattern 150 is removed to expose the seed layer 140.

That is, after the metal protective layer 170 is formed, the seed layer 140 corresponding to the outer layer resist pattern 150 is exposed by peeling off the outer layer resist pattern 150 that is no longer needed.

Thereafter, as illustrated in FIG. 5L, the exposed seed layer 140 is removed to complete the outer circuit pattern 180.

When the exposed seed layer 140 is removed by performing an etching process, an outer circuit pattern 180 including not only the seed layer 140 and the copper plating layer 160 but also the metal protective layer 170 may be formed. . Here, when removing the exposed seed layer 140, the copper plating layer 160 is exposed only a minimum portion by the metal protective layer 170 does not cause a defect such as undercut due to over-etching.

The outer circuit pattern 180 may be electrically connected to the inner circuit pattern 120 formed in the insulating layer 130 by the blind via hole 132.

Next, as shown in FIG. 5M, the solder resist pattern 190 is formed on the upper surface of the outer circuit pattern 180, thereby forming the printed circuit board 200.

The solder resist pattern 190 is formed to protect the remaining outer circuit patterns 180 except for some outer circuit patterns 180 connected to the outside, thereby preventing short circuits and incorrect connections between wirings. To prevent unwanted connection and the like when mounting electronic components. As the solder resist pattern, for example, it is preferable to use an ink for solder resist, such as a photo imageable solder resist ink (PSR) made of a heat resistant resin that can sufficiently withstand the melting temperature of the connection terminal.

In this case, after removing the metal protective layer 170 formed on the outer circuit pattern 180, the solder resist pattern 190 may be formed.

In the conventional method of manufacturing a printed circuit board, since the plating layer 7 is formed of the same metal as the seed layer 5, the plating layer together with the seed layer 5 during the etching process to remove the unnecessary seed layer 5. Since (7) is etched, in consideration of this point in forming the plating layer 7, there is a problem in that a plating layer 7 larger than a desired size is formed to bring a limitation to the implementation of a fine circuit pattern. In addition, in the case of forming the plating layer 7 larger than the desired size, when the etching process is performed together with the unnecessary seed layer 5, the surface area where the plating layer 5 meets the etching solution becomes wider and the attack of the etching solution is performed. Since receiving a lot of the undercut to form an undercut at the bottom of the plating layer 5 has caused a problem of causing the interlayer lifting phenomenon.

However, as described above, in the method of manufacturing the printed circuit board 200 according to the present invention, the metal protective layer formed of a metal different from the seed layer 140 and the copper plating layer 160 on the copper plating layer 160 ( 170 to minimize the surface area where the copper plating layer 160 and the etching liquid meet during the etching process for removing the unnecessary seed layer 140, thereby reducing the etching amount of the copper plating layer 160 more than the desired size Even if a large plating layer is not formed, defects such as short circuits or lifting of layers are not generated, resulting in an effect of implementing a fine circuit pattern.

As described above, the present invention has been described through specific embodiments, but the scope of the present invention is not limited to the above embodiments, and various modifications are possible within the scope of the present invention. It is intended that the scope of the invention only be limited by the following claims.

According to the printed circuit board and the manufacturing method of the present invention, after forming the seed layer and the plating layer for forming the outer layer circuit pattern, by forming a metal protective layer different from the seed layer and the plating layer and the metal component on the plating layer, unnecessary seed When removing the layer, it is possible to easily implement a fine circuit pattern by minimizing the amount of etching of the plating layer.

Claims (12)

A base substrate having at least one inner layer circuit pattern formed in the insulating layer; An outer circuit pattern formed on at least one surface of the base substrate and electrically connected to the inner circuit pattern and including a metal layer and a metal protective layer formed on an upper surface of the metal layer; And A solder resist pattern formed on an upper surface of the outer circuit pattern to expose at least a portion of the outer circuit pattern; Including, And the metal protective layer has different etching requirements from the metal layer. delete The printed circuit board of claim 1, wherein the metal protective layer is thinner than the metal layer. The printed circuit board of claim 1, wherein the metal layer is a copper layer. The printed circuit board of claim 1, wherein the metal layer comprises a seed layer and a plating layer. The printed circuit board of claim 1, wherein the solder resist pattern is formed of an insulating material. (A) forming a via hole in an insulating layer having at least one inner circuit pattern formed therein to provide a base substrate; (B) forming a seed layer on at least one surface of the base substrate; (C) forming an outer layer resist pattern on the seed layer and performing electrolytic plating to form a plating layer; (D) forming a metal protective layer on an upper surface of the plating layer; (E) removing the outer layer resist pattern and removing an exposed seed layer to form an outer circuit pattern electrically connected to the inner circuit pattern; And (F) forming a solder resist pattern on the upper surface of the outer layer circuit pattern to expose a portion of the outer layer circuit pattern; Including, The manufacturing method of the printed circuit board, characterized in that the metal protective layer is not removed in the step (E). 8. The method of claim 7, wherein the metal protective layer has different etching requirements from the seed layer. The method of claim 7, wherein the seed layer and the plating layer are formed of the same metal layer. The method of claim 7, wherein the seed layer and the plating layer are formed of copper. The method of claim 7, wherein the metal protective layer is formed of at least one of nickel, tin, gold, platinum, and zinc. The method of claim 7, wherein after step (E), (G) removing the metal protective layer to form an outer circuit pattern composed of the seed layer and the plating layer; Method of manufacturing a printed circuit board further comprising a.

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