JP2005322868A - Method for electrolytic gold plating of printed circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for electrolytic gold plating of a printed circuit board which does not require a lead-in wire. <P>SOLUTION: The method comprises a step (A) of forming an electrolytic copper plate layer corresponding to a prescribed copper plate resist pattern to a negative plate; a step (B) of forming an electrolytic gold plate layer corresponding to a prescribed gold plate resist pattern to the negative plate using the outer layer of the negative plate as the electrolytic lead-in wire; and (C) a step of removing the outer layer of the negative plate where the electrolytic copper plate layer is not formed at the step (A). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for electrolytic gold plating of a printed circuit board, and more particularly to an electrolytic gold plating method for a printed circuit board in which an electrolytic gold plating layer is formed using an outer layer of a copper foil original plate or an electroless copper plating layer as a plating lead-in line.

  Electrolytic gold-plating and electroless gold plating are the surface treatment processes for mounting passive components and active integrated circuits on printed circuit boards by wire bonding. (Electroless gold-plating).

  Here, the electroless gold plating mainly uses electrolytic gold plating because there is a high risk of occurrence of a peeling phenomenon at the interface between gold and nickel during wire bonding. Unlike other surface treatments that do not use electricity, such electrolytic gold plating is a surface treatment process that increases the thickness of the gold plating, has high productivity, and has high peel strength reliability.

  Typical electrolytic gold plating methods include electrolytic soft gold-plating and electrolytic hard gold-plating. Electrolytic soft gold plating is used for wire bonding of ordinary semiconductor package products because the plated gold particles are large, form a porous structure, and have a low density. On the other hand, electrolytic hard gold plating is used for contact terminals such as mobile phone battery contact terminals because gold particles are dense, dense, and excellent in mechanical strength.

  1A to 1K are cross-sectional views illustrating a flow of a conventional printed circuit board manufacturing method. FIG. 2 is a plan view of a conventional printed circuit board manufactured by the method of FIGS. 1a to 1k. Here, the manufacturing method of FIGS. 1a to 1k is shown for the cross section a-a 'of FIG.

  As shown in FIG. 1a, a copper clad laminate 11 is prepared in which an insulating resin layer 11a is covered with a copper foil layer 11b.

  As shown in FIG. 1b, a via hole b is formed for circuit connection between the upper and lower copper foil layers 11b.

  As shown in FIG. 1c, in order to electrically connect the formed via hole b, electroless copper plating is performed on the copper foil laminate 11, the lower copper foil layer 11b, and the side wall of the via hole b by electroless copper plating. Layer 12 is formed.

  As shown in FIG. 1d, an electrolytic copper plating layer 13 having excellent physical properties is formed on the copper foil laminate 11 subjected to electroless copper plating and on the side walls of the lower copper foil layer 11b and the via hole b.

  As shown in FIG. 1e, after the dry film 20 is applied to the copper foil laminate 11, the dry film 20 is exposed and developed using an artwork film on which a predetermined pattern is printed, A predetermined pattern is formed on the dry film 20. The predetermined pattern includes a circuit pattern, a land of a via hole b, a wire bonding terminal pattern, a plated lead-in line pattern, and the like.

  As shown in FIG. 1f, the copper foil laminate 11 is immersed in an etching solution using a dry film 20 having a predetermined pattern formed as an etching resist, and the remaining portion excluding the predetermined pattern formation portion is immersed. The copper foil layer 11b, the electroless copper plating layer 12, and the electrolytic copper plating layer 13 are removed.

  As shown in FIG. 1g, the dry film 20 applied to the copper foil laminate 11 on which the predetermined pattern is formed is peeled off and removed.

  As shown in FIG. 1 h, a solder resist 14 is applied to the copper foil laminate 11 and then temporarily dried.

  As shown in FIG. 1i, after the artwork film 30 including the light-shielding portion 30a on which the solder resist pattern is printed is brought into close contact with the copper foil laminate 11, it is exposed and developed, thereby corresponding to the solder resist pattern. The solder resist 14 is cured.

  As shown in FIG. 1j, after the artwork film 30 is removed, the uncured portion of the solder resist 14 is removed to form a solder resist pattern.

  As shown in FIG. 1k, the electroless gold plating layer 15 is formed by performing electrolytic gold plating on the wire bonding terminal which is the opening c of the solder resist pattern of the copper foil laminate 11.

  Thereafter, when the outer shape of the copper foil laminate 11 is formed using a router or a power press, the printed circuit board 10 is formed as shown in FIG.

  The conventional printed circuit board manufacturing method described above is disclosed in Patent Document 1 and Patent Document 2.

  As in the portion indicated by the dotted ellipse in FIG. 2, the conventional printed circuit board 10 is manufactured by applying the electrolytic gold plating to the copper foil laminate 11 with a lead-in line 16 that is not related to the circuit pattern. Must be formed.

  Such a plating lead-in line 16 is almost removed in the outline forming process using a router or a power press. However, a part of the plating lead-in line 16 remains on the printed circuit board 10 and depending on the design method, a large amount of the plating lead-in line 16 may be printed circuit. It may remain on the substrate 10.

  Currently, there is a demand for miniaturization and high integration of the circuit pattern of the printed circuit board 10 by increasing the functionality and size of electronic products. However, the plated lead-in wire 16 remaining on the printed circuit board 10 is not related to the circuit pattern, and there is a problem that the degree of design freedom is limited.

  On the other hand, the plated lead-in wire 16 remaining on the printed circuit board 10 serves as a kind of conductor in a high-frequency environment due to high-speed data communication, and thus acts as an antenna to generate parasitic inductance. .

  Such a parasitic inductance causes an interference interaction with an electrical signal on the circuit and induces impedance mismatching, thereby degrading the electrical performance of the final electronic product. .

  In addition, there is a problem that the signal to noise ratio of the final electronic product is deteriorated due to parasitic inductance, and the reliability of the product is lowered due to a sudden malfunction of the final electronic product.

Republic of Korea Patent Application Publication No. 1999-47463 Korean Patent Publication No. 2003-39553

  The present invention has been made to solve the conventional problems, and an object of the present invention is to provide a method for electrolytic gold plating of a printed circuit board that does not require a lead-in wire.

  In order to achieve the above object, an electrolytic gold plating method for a printed circuit board according to the present invention includes (A) a step of forming an electrolytic copper plating layer corresponding to a predetermined copper plating resist pattern on an original plate, and (B) electrolytic gold plating. A step of forming an electrolytic gold plating layer corresponding to a predetermined gold plating resist pattern on the original plate using an outer layer of the original plate as a lead-in line; and (C) the electrolytic copper plating layer in the step (A) is not formed. Removing an outer layer portion of the original plate.

  The method for electrolytic gold plating of a printed circuit board according to the present invention includes: (D) a step of processing a via hole in the original plate before the step (A); and (E) an electroless coating on the outer layer of the original plate and the sidewall of the via hole. The method further includes the step of forming a copper plating layer, wherein the step (B) further includes the electroless copper plating layer as the electrolytic gold plating lead-in wire.

  The step (A) of the electrolytic gold plating method for a printed circuit board according to the present invention includes: (A-1) applying a copper plating resist to the original plate, and then exposing and developing the copper plating resist to obtain a predetermined copper plating resist. And (A-2) electrolytic copper plating using the outer layer of the original plate and the electroless copper plating layer as an electrolytic copper plating lead-in line, and electrolysis corresponding to the copper plating resist pattern on the original plate It is preferable to include a process of forming a copper plating layer and (A-3) a process of removing the copper plating resist.

  The electrolytic gold plating method for a printed circuit board according to the present invention is characterized by further comprising (D) a step of thinly processing the outer layer of the original plate before the step (A).

  The copper plating resist in the electrolytic gold plating method for a printed circuit board according to the present invention is preferably a photosensitive material.

  The step (B) of the electrolytic gold plating method for a printed circuit board according to the present invention includes (B-1) applying a gold plating resist to the original plate, and then exposing and developing the gold plating resist to form a predetermined gold plating resist pattern. And (B-2) a process of applying electrolytic gold plating using the outer layer of the original plate and the electroless copper plating layer as an electrolytic gold plating lead-in line to form an electrolytic gold plating layer corresponding to the gold plating resist pattern on the original plate And (B-3) a step of removing the gold plating resist.

  After the step (B-1) of the electrolytic gold plating method for a printed circuit board according to the present invention, (B-4) electrolytic nickel plating using the electroless copper plating layer as an electrolytic nickel plating lead-in line is performed, and the gold plating Preferably, the method further includes a step of forming an electrolytic nickel plating layer corresponding to the resist pattern.

  The gold plating resist of the method for electrolytic gold plating of a printed circuit board according to the present invention is preferably a photosensitive material.

  An electroless copper plating layer in which the electrolytic copper plating layer in the step (C) of the electrolytic copper plating method for a printed circuit board according to the present invention is not formed, and an outer layer portion of the original plate adjacent to the electroless copper plating layer. The removing process is performed by depositing the original plate in an etching solution that etches copper without etching gold, thereby adjacent to the electroless copper plating layer on which the electrolytic copper plating layer is not formed and the electroless copper plating layer. It is preferable to remove the outer layer portion of the original plate.

  The step (C) of the electrolytic gold plating method for a printed circuit board according to the present invention includes (C-1) applying an etching resist to the original plate, exposing and developing the etching resist, and forming the electrolytic copper plating layer. A process of forming a predetermined etching resist pattern which is not a part, and (C-2) the electroless copper plating layer corresponding to the etching resist pattern and the outer layer portion of the original plate adjacent to the electroless copper plating layer Preferably, the method includes a step of etching and removing (C-3) a step of removing the etching resist.

  The etching resist of the method for electrolytic gold plating of a printed circuit board according to the present invention is preferably a photosensitive material.

  The process of etching the electroless copper plating layer and the outer layer portion of the original plate adjacent to the electroless copper plating layer in the step (C-2) of the electrolytic gold plating method for a printed circuit board according to the present invention includes: It is preferable to etch the electroless copper plating layer and the outer layer portion of the original plate adjacent to the electroless copper plating layer by depositing in an etching solution.

  The process of etching the electroless copper plating layer and the outer layer portion of the original plate adjacent to the electroless copper plating layer in the step (C-2) of the electrolytic gold plating method for a printed circuit board according to the present invention includes a plasma etching method. It is preferable to etch the electroless copper plating layer and the outer layer portion of the original plate adjacent to the electroless copper plating layer.

  The method for electrolytic gold plating of a printed circuit board according to the present invention further comprises (D) after applying the solder resist on the original plate and then forming a predetermined solder resist pattern after the step (C). Features.

  The present invention provides a method for electrolytic gold plating of a printed circuit board that does not require a lead-in wire.

  Therefore, the electrolytic gold plating method for a printed circuit board according to the present invention can form a circuit pattern even in a portion where the design could not be performed due to an interruption of the plating lead-in line, thereby improving the degree of freedom in design. There is.

  Further, the electrolytic gold plating method for a printed circuit board according to the present invention has an effect that a parasitic inductance due to the plated lead-in does not occur because the finished product of the printed circuit board has no plated lead-in line.

  Moreover, the electrolytic gold plating method of the printed circuit board according to the present invention has no parasitic inductance due to the lead-in wire, so that the signal-to-noise ratio is improved in a high frequency environment, impedance matching is easy, and sudden malfunction is prevented. There is also an effect that the electrical performance and reliability of the printed circuit board are improved.

  Hereinafter, a method for electrolytic gold plating of a printed circuit board according to the present invention will be described in detail.

  3A to 3K are cross-sectional views illustrating a flow of a method of manufacturing a printed circuit board using an electrolytic gold plating method according to an embodiment of the present invention, and FIG. 4 is a printed circuit according to the present invention manufactured by the method of FIG. It is a top view of a board | substrate. Here, the manufacturing method of FIGS. 3A to 3K is shown for the cross section A-A ′ of FIG. 4.

  As shown in FIG. 3 a, an original plate 110 is prepared as a copper foil laminate in which an insulating resin layer 111 is coated with a copper foil layer 112. Here, in consideration of the fact that the copper foil layer 112 is removed by etching in the subsequent steps, it is preferable to thinly process the copper foil layer 112 in the pretreatment process.

  The copper foil laminate used as such an original plate 110 is a glass / epoxy copper foil laminate, a heat-resistant resin copper foil laminate, a paper / phenol copper foil laminate, a high-frequency copper foil laminate, depending on the application. There are various types such as flexible copper clad laminate and composite copper foil laminate. However, for the production of double-sided printed circuit boards and multilayer printed circuit boards, it is preferable to use a glass / epoxy copper foil laminate in which an insulating resin layer 111 used mainly is coated with a copper foil layer 112.

  As shown in FIG. 3 b, a via hole B is formed for circuit connection between the upper and lower copper foil layers 112.

  Here, in the process of forming the via hole B, it is preferable to use a method of forming the via hole B based on a preset position using a CNC drill (Computer Numerical Control Drill) or a laser.

  The method using a CNC drill is suitable for forming a via hole B of a double-sided printed circuit board or a through hole of a multilayer printed circuit board. After processing the via hole B or the through hole by using such a CNC drill, deburring for removing copper bar (burr), dust on the inner wall of the via hole B, and dust on the surface of the copper foil layer 112 generated during drilling is performed. ) Step is preferably performed. In this case, the roughness of the surface of the copper foil layer 112 is given, so that there is an advantage that adhesion with copper is improved in the subsequent copper plating process.

  The method using a laser is suitable for forming a micro via hole in a multilayer printed circuit board. As a method using such a laser, the copper foil layer 112 and the insulating resin layer 111 can be simultaneously processed using a YAG (Yttrium Aluminum Garnet) laser. After etching the copper foil layer 112 in the via hole B forming portion, the carbon dioxide layer 112 is etched. The insulating resin layer 111 can also be processed using a carbon laser.

  On the other hand, after forming the via hole B, it is preferable to perform a desmear process in which the insulating resin layer 111 of the original plate 110 is melted by the heat generated at the time of formation to remove smear generated on the side wall of the via hole B. .

  As shown in FIG. 3C, an electroless copper plating layer 120 is formed on the original plate 110 on the lower copper foil layer 112 and the sidewalls of the via hole B by electroless copper plating.

  Here, since the sidewall of the via hole B of the original plate 110 is the insulating resin layer 111, electrolytic copper plating cannot be performed immediately after the formation of the via hole B. Therefore, electroless copper plating is performed in order to electrically connect the formed via hole B and to perform electrolytic copper plating. Since the electroless copper plating is plating on an insulator, a reaction due to charged ions cannot be expected. Electroless copper plating is performed by a precipitation reaction, which is promoted by a catalyst. In order for copper to deposit from the plating solution, a catalyst must adhere to the surface of the material to be plated. This indicates that electroless copper plating requires a lot of pretreatment.

  As one example, the electroless copper plating process includes a degreasing process, a soft etching process, a pre-catalyst process, a catalyst process, an activation process, an electroless copper plating process, and Includes antioxidant process.

  In the degreasing process, oxides or foreign matters, particularly oils and fats, etc. present on the surface of the copper foil layer 112 are removed with a chemical containing an acid or alkaline surfactant, and then the surfactant is thoroughly washed with water.

  In the soft corrosion process, a fine roughness (for example, about 1 μm to 2 μm) is formed on the surface of the copper foil layer 112 so that the copper particles are uniformly adhered in the plating stage, and contaminants that are not treated in the degreasing process are removed. Remove.

  In the pre-catalyst treatment process, the original plate 110 is immersed in a low concentration catalyst chemical to prevent contamination or concentration change of the chemical used in the catalyst treatment stage. Moreover, since the original plate 110 is previously immersed in the chemical tank of the same component, there is an effect that the catalyst treatment is more activated. Such a pre-catalyst treatment process preferably uses a catalyst chemical diluted to 1% to 3%.

In the catalyst treatment process, the catalyst particles are coated on the surfaces of the copper foil layer 112 and the insulating resin layer 111 of the original plate 110 (for example, the side wall of the via hole B). The catalyst particles preferably use a Pd—Sn compound, and the Pd—Sn compound serves to promote plating by bonding particles to be plated, that is, Cu ₂ ⁺ and Pd ₂ ⁻ .

In the electroless copper plating process, the plating solution is preferably made of CuSO ₄ , HCHO, NaOH and other stabilizers. In order for the plating reaction to continue, the chemical reaction must be balanced, and for this purpose, it is important to control the composition of the plating solution. In order to maintain the composition, appropriate supply of insufficient components, mechanical stirring, a plating solution circulation system, etc. must be well operated. A filtration device for the by-product generated as a result of the reaction is required, and the use time of the plating solution can be extended by utilizing this.

  In the oxidation treatment process, an antioxidant film is coated on the entire surface in order to prevent the plating film from being oxidized by the alkali component remaining after electroless copper plating.

  However, the electroless copper plating process described above is generally formed thinner because physical properties are lower than that of electrolytic copper plating.

  As shown in FIG. 3d, after the dry film 200 is applied to the original plate 110, the dry film 200 is exposed and developed using an artwork film on which the predetermined pattern is printed, thereby forming the predetermined pattern on the dry film 200. Form. The predetermined pattern includes a circuit pattern, a land of a via hole B, a wire bonding terminal pattern, and the like.

  The dry film 200 includes a cover film, a photoresist film, and a transparent film (Mylar film), and a layer that substantially serves as a resist is a photoresist film.

In the exposure and development process of the dry film 200, an artwork film on which a predetermined pattern is printed is brought into close contact with the dry film and then irradiated with ultraviolet rays. At this time, the black portion on which the artwork film pattern is printed does not transmit ultraviolet light, and the unprinted portion transmits ultraviolet light to cure the dry film 200 under the artwork film. When the copper foil laminate having the cured dry film 200 is immersed in the developer as described above, the uncured dry film 200 portion is removed by the developer, and only the cured dry film 200 portion remains to form a resist pattern. . Here, as the developer, an aqueous solution of sodium carbonate (Na ₂ CO ₃ ) or potassium carbonate (K ₂ CO ₃ ) is used.

  As shown in FIG. 3e, the dry film 200 on which a predetermined pattern is formed is used as a plating resist, and the lower copper foil layer 112 and the electroless copper plating layer 120 are used as an electrolytic copper plating lead-in line on the original plate 110, Electrolytic copper plating is applied to the lower copper foil layer 112, the electroless copper plating layer 120, and the sidewalls of the via hole B on the original plate 110 to form the electrolytic copper plating layer 130.

  Here, after the original plate 110 is deposited on a copper-plated work cylinder, electrolytic copper plating is performed using a DC rectifier, the plating area is calculated, and a current suitable for the DC rectifier is passed to deposit copper. Is preferably used.

  Such electrolytic copper plating has the advantage that the rational characteristics are superior to the electroless copper plating layer 120 and that a thick copper plating layer 130 can be easily formed.

  As shown in FIG. 3f, the dry film 200 applied to the original plate 110 subjected to electrolytic copper plating is peeled off and removed.

  Here, the dry film 200 is removed using a stripping solution such as sodium hydroxide NaOH or potassium hydroxide KOH.

  In the process of FIGS. 3d to 3f described above, the dry film 200 is used as the plating resist, but a liquid photosensitive material can be used as the plating resist. In this case, a liquid photosensitive material that is exposed to ultraviolet rays is applied to the original plate 110 on which electroless copper plating has been applied and then dried. Next, a predetermined pattern is formed on the photosensitive material by exposing and developing the photosensitive material using the artwork film 300 on which the predetermined pattern is formed. Thereafter, a photosensitive material having a predetermined pattern is used as a plating resist, the original plate 110 is deposited on a copper plating work tube, and then a direct current rectifier is used to form the lower copper foil layer 112, electroless on the original plate 110. Electrolytic copper plating is applied to the copper plating layer 120 and the sidewalls of the via hole B to form the electrolytic copper plating layer 130. Thereafter, the photosensitive material is removed. Here, methods for coating a photosensitive material in a liquid state include a dip coating method, a roll coating method, and an electro-deposition method.

  As shown in FIG. 3g, after the gold plating resist 300 is applied to the original plate 110, the gold plating resist 300 is exposed and developed using an artwork film on which the electrolytic gold plating pattern is printed, thereby forming the electrolytic gold plating pattern on the gold plating resist 300. Form.

  As shown in FIG. 3h, an electrolytic gold plating layer 150 is formed by applying electrolytic gold plating to the original plate 110 using a gold plating resist 300 on which an electrolytic gold plating pattern is formed. Similar to the copper plating process of FIG. 3e, the electrolytic gold plating method according to the present invention uses the copper foil layer 112 and the electroless copper plating layer 120 of the original plate 110 as electrolytic gold plating lead lines, so that a separate plating lead line is unnecessary. is there.

  Here, after depositing the original plate 110 on a gold-plated working cylinder, electrolytic gold plating is performed using a DC rectifier, and the plating area is calculated, and a current suitable for the DC rectifier is supplied to deposit gold. It is preferable.

  On the other hand, in order to improve adhesion with gold, electrolytic gold plating can be applied after thinly plating nickel.

  As shown in FIG. 3i, the gold plating resist 300 applied to the original plate 110 subjected to electrolytic gold plating is removed.

  As the gold plating resist 300 used in the process of FIGS. 3g to 3i described above, the dry film 200 described in the process of FIGS. 3d to 3f or the photosensitive material in a liquid state can be used.

  As shown in FIG. 3j, by removing the electroless copper plating layer 120 and the copper foil layer 112 of the original plate 110 that has not been subjected to electrolytic copper plating, the circuit pattern, the land of the via hole B, the wire bonding terminal pattern are formed on the original plate 110. A predetermined pattern including the above is formed.

  Here, various methods can be used for removing the electroless copper plating layer 120 and the copper foil layer 112 of the original plate 110.

  One method is to deposit the electroless copper plating layer 120 and the copper foil layer 112 in an etching solution without etching the electrolytic gold plating layer 150. In this case, in FIG. 3a, a pretreatment step for thinly processing the copper foil layer 112 of the original plate 110 is performed, and the electroless copper plating layer 120 is generally formed thin, and thus can be easily removed. However, the circuit pattern, the land and sidewall of the via hole B, the wire bonding terminal, and the like are formed with a thick electrolytic copper plating layer 130 having excellent physical characteristics in addition to the copper foil layer 112 or the electroless copper plating layer 120. Therefore, although most of the copper foil layer 112 or the copper plating layers 120 and 130 are left, they are partially etched.

  As another method, after an etching resist such as a dry film 200 is applied to the original plate 110, a pattern for protecting the circuit pattern, the land of the via hole B, the wire bonding terminal, and the like is formed. Then, the unnecessary electroless copper plating layer 120 and the copper foil layer 112 of the original plate 110 can be removed by depositing the original plate 110 in an etching solution.

  As another method, after applying an etching resist such as a dry film 200 to the original plate 110, a pattern for protecting the circuit pattern, the land of the via hole B, the wire bonding terminal, and the like is formed. Thereafter, unnecessary electroless copper plating layer 120 and copper foil layer 112 of original plate 110 can be removed using plasma or the like. In this case, there is an advantage that the side wall of the circuit pattern is precisely processed by directional etching which is an advantage of the plasma etching method.

  As shown in FIG. 3k, after applying the solder resist 140 to the original plate 110 on which a predetermined pattern is formed, a solder resist pattern is formed.

  Considering in more detail the process of forming such a solder resist pattern, the solder resist 140 is applied to the original plate 110 and then temporarily dried. Here, as a method of applying the solder resist 140, a screen printing method, a roller coating method, a curtain coating method, a spray coating method, or the like may be used. it can.

  Next, after the artwork film on which the solder resist pattern of the original plate 110 is printed is adhered, the solder resist 140 corresponding to the solder resist pattern is cured by exposure and development. Next, the artwork film is removed, and the solder resist 140 of the uncured portion is removed to form a solder resist pattern. Thereafter, the solder resist 140 is completely cured using ultraviolet rays and a dryer, and the solder resist 140 remaining on the portion of the original plate 110 where the solder resist 140 has been removed, foreign matters, and the like are removed using plasma or the like.

  Thereafter, when a copper foil laminate is formed using a router or a power press, a printed circuit board 100 as shown in FIG. 4 is formed.

  The printed circuit board 100 manufactured by the manufacturing method according to the present invention does not have a plating lead-in line, as indicated by the dotted ellipse in FIG. This is because the electroless copper plating layer 120 of the original plate 110 is used as an electrolytic gold plating lead-in wire for performing electrolytic gold plating and is removed after electrolytic gold plating.

  On the other hand, in FIGS. 3 and 4, a double-sided printed circuit board using a copper foil laminate as the original plate 110 is shown. However, the single-sided printed circuit board and the multilayer printed circuit board are also described above depending on the purpose or application. Depending on the method, a single-sided printed circuit board and a multilayer printed circuit board can be formed by an electrolytic gold plating method that does not require a plated lead-in wire.

  Here, when manufacturing a multilayer printed circuit board, a pattern including a ground circuit and a signal processing circuit is formed on the inner layer, and copper foil is attached to such an inner layer using an insulating adhesive resin such as a prepreg. Alternatively, an outer layer in which RCC (Resin Coated Copper) is laminated is formed. A multilayer printed circuit board is formed on this outer layer by the electrolytic gold plating method described in the explanation of FIG.

  FIG. 5 is a plan view of a printed circuit board manufactured according to another embodiment of the present invention. As shown in FIG. 5, the printed circuit board 200 according to the present invention does not require a separate plating lead-in line at the time of design, so the portion where the conventional plating lead-in line is formed (the dotted oval in FIG. 5). A circuit pattern can also be formed on a portion indicated by. Therefore, since the degree of freedom in design is improved, there is an advantage that the circuit pattern on the printed circuit board 200 can be highly integrated.

  Although the present invention has been described above, this is merely an example, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the technical idea of the present invention. . Also, it will be clear from the claims that these belong to the scope of the present invention.

It is sectional drawing which shows the flow of the printed circuit board manufacturing method which concerns on a prior art. It is sectional drawing which shows the flow of the printed circuit board manufacturing method which concerns on a prior art. It is sectional drawing which shows the flow of the printed circuit board manufacturing method which concerns on a prior art. It is sectional drawing which shows the flow of the printed circuit board manufacturing method which concerns on a prior art. It is sectional drawing which shows the flow of the printed circuit board manufacturing method which concerns on a prior art. It is sectional drawing which shows the flow of the printed circuit board manufacturing method which concerns on a prior art. It is sectional drawing which shows the flow of the printed circuit board manufacturing method which concerns on a prior art. It is sectional drawing which shows the flow of the printed circuit board manufacturing method which concerns on a prior art. It is sectional drawing which shows the flow of the printed circuit board manufacturing method which concerns on a prior art. It is sectional drawing which shows the flow of the printed circuit board manufacturing method which concerns on a prior art. It is sectional drawing which shows the flow of the printed circuit board manufacturing method which concerns on a prior art. FIG. 2 is a plan view of a conventional printed circuit board manufactured by the method of FIGS. 1a to 1k. It is sectional drawing which shows the flow of the printed circuit board manufacturing method using the electrolytic gold plating method which concerns on one Example of this invention. It is sectional drawing which shows the flow of the printed circuit board manufacturing method using the electrolytic gold plating method which concerns on one Example of this invention. It is sectional drawing which shows the flow of the printed circuit board manufacturing method using the electrolytic gold plating method which concerns on one Example of this invention. It is sectional drawing which shows the flow of the printed circuit board manufacturing method using the electrolytic gold plating method which concerns on one Example of this invention. It is sectional drawing which shows the flow of the printed circuit board manufacturing method using the electrolytic gold plating method which concerns on one Example of this invention. It is sectional drawing which shows the flow of the printed circuit board manufacturing method using the electrolytic gold plating method which concerns on one Example of this invention. It is sectional drawing which shows the flow of the printed circuit board manufacturing method using the electrolytic gold plating method which concerns on one Example of this invention. It is sectional drawing which shows the flow of the printed circuit board manufacturing method using the electrolytic gold plating method which concerns on one Example of this invention. It is sectional drawing which shows the flow of the printed circuit board manufacturing method using the electrolytic gold plating method which concerns on one Example of this invention. It is sectional drawing which shows the flow of the printed circuit board manufacturing method using the electrolytic gold plating method which concerns on one Example of this invention. It is sectional drawing which shows the flow of the printed circuit board manufacturing method using the electrolytic gold plating method which concerns on one Example of this invention. FIG. 3 is a plan view of a printed circuit board according to an embodiment of the present invention manufactured by the method of FIGS. 3a to 3k. FIG. 6 is a plan view of a printed circuit board according to another embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Printed circuit board 110 Original board 111 Insulation resin layer of original board 112 Copper foil layer of original board 120 Electroless copper plating layer 130 Electrolytic copper plating layer 140 Solder resist 150 Electrolytic gold plating layer 200 Dry film 300 Gold plating resist B Via hole

Claims (14)

(A) forming an electrolytic copper plating layer corresponding to a predetermined copper plating resist pattern on the original plate;
(B) forming an electrolytic gold plating layer corresponding to a predetermined gold plating resist pattern on the original plate using the outer layer of the original plate as an electrolytic gold plating lead-in line;
(C) A step of removing an outer layer portion of the original plate from which the electrolytic copper plating layer is not formed in the step (A). Before step (A),
(D) processing a via hole in the original plate;
(E) further comprising the step of forming an electroless copper plating layer on the outer layer of the original plate and the side wall of the via hole;
2. The method according to claim 1, further comprising the electroless copper plating layer as the electrolytic gold plating lead-in line in the step (B). In step (A),
(A-1) After applying a copper plating resist to the original plate, exposing and developing the copper plating resist to form a predetermined copper plating resist pattern;
(A-2) Process of performing electrolytic copper plating using the outer layer of the original plate and the electroless copper plating layer as an electrolytic copper plating lead-in line, and forming an electrolytic copper plating layer corresponding to the copper plating resist pattern on the original plate When,
(A-3) The process for removing the copper plating resist, wherein the electrolytic gold plating method for a printed circuit board according to claim 2. Before step (A),
3. The method according to claim 2, further comprising the step of thinly processing the outer layer of the original plate. 4. The method for electrolytic gold plating of a printed circuit board according to claim 3, wherein the copper plating resist is a photosensitive material. In step (B),
(B-1) After applying a gold plating resist to the original plate, exposing and developing the gold plating resist to form a predetermined gold plating resist pattern;
(B-2) applying electrolytic gold plating using the outer layer of the original plate and the electroless copper plating layer as an electrolytic gold plating lead-in line, and forming an electrolytic gold plating layer corresponding to the gold plating resist pattern on the original plate;
(B-3) The method according to claim 2, further comprising the step of removing the gold plating resist. After the step (B-1),
(B-4) further comprising a process of performing electrolytic nickel plating using the electroless copper plating layer as an electrolytic nickel plating lead-in line to form an electrolytic nickel plating layer corresponding to the gold plating resist pattern. The method for electrolytic gold plating of a printed circuit board according to claim 6. 7. The electrolytic gold plating method for a printed circuit board according to claim 6, wherein the gold plating resist is a photosensitive material. In the step (C), the process of removing the electroless copper plating layer in which the electrolytic copper plating layer is not formed and the outer layer portion of the original plate adjacent to the electroless copper plating layer is performed without etching the gold. By depositing the original plate in an etching solution to be etched, the electroless copper plating layer on which the electrolytic copper plating layer is not formed, and the outer layer portion of the original plate adjacent to the electroless copper plating layer are removed. The method for electrolytic gold plating of a printed circuit board according to claim 2. In step (C),
(C-1) After applying an etching resist to the original plate, exposing and developing the etching resist to form a predetermined etching resist pattern which is a portion where the electrolytic copper plating layer is not formed;
(C-2) etching and removing the electroless copper plating layer corresponding to the etching resist pattern and the outer layer portion of the original plate adjacent to the electroless copper plating layer;
(C-3) A method for electrolytic gold plating of a printed circuit board according to claim 2, comprising the step of removing the etching resist. The method for electrolytic gold plating of a printed circuit board according to claim 10, wherein the etching resist is a photosensitive material. In the process (C-2), the electroless copper plating layer and the process of etching the outer layer portion of the original plate adjacent to the electroless copper plating layer are performed by depositing the original plate in an etchant. 11. The method for electrolytic gold plating of a printed circuit board according to claim 10, wherein an outer layer portion of the original plate adjacent to the copper plating layer and the electroless copper plating layer is etched. The process of etching the electroless copper plating layer in the step (C-2) and the outer layer portion of the original plate adjacent to the electroless copper plating layer is performed using a plasma etching method, and the electroless copper plating layer and 11. The method for electrolytic gold plating of a printed circuit board according to claim 10, wherein an outer layer portion of the original plate adjacent to the electroless copper plating layer is etched. After step (C),
3. The method according to claim 2, further comprising the step of forming a predetermined solder resist pattern after applying a solder resist to the original plate.

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