JPWO2008093626A1 - Chip element and manufacturing method thereof - Google Patents

Chip element and manufacturing method thereof Download PDF

Info

Publication number
JPWO2008093626A1
JPWO2008093626A1 JP2008556079A JP2008556079A JPWO2008093626A1 JP WO2008093626 A1 JPWO2008093626 A1 JP WO2008093626A1 JP 2008556079 A JP2008556079 A JP 2008556079A JP 2008556079 A JP2008556079 A JP 2008556079A JP WO2008093626 A1 JPWO2008093626 A1 JP WO2008093626A1
Authority
JP
Japan
Prior art keywords
electrode
plating
insulating film
base
chip element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008556079A
Other languages
Japanese (ja)
Other versions
JP4935828B2 (en
Inventor
達也 辻口
達也 辻口
修祥 本田
修祥 本田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2008556079A priority Critical patent/JP4935828B2/en
Publication of JPWO2008093626A1 publication Critical patent/JPWO2008093626A1/en
Application granted granted Critical
Publication of JP4935828B2 publication Critical patent/JP4935828B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P11/00—Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1903—Structure including wave guides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

絶縁性材であるケイ酸系ガラスを主成分とし感光性材を添加したガラスペーストを親基板に塗布する。次に、フォトマスクを用いてガラスペーストを感光させて固化する。次に、固化していないガラスペーストを除去して開口を設ける。次に、ガラスペーストを焼成してガラス層を形成する。以上の一連の工程に続いて、ガラス層の形成の後、ガラス層の開口の底面の銀電極上に、複数のメッキ層を形成してボンディング用電極を形成する。以上の工程により、ワイヤボンディングに用いる電極における金属材使用量を低減しながら、また、電極形成に係るレジストを不要にしてチップ素子を製造し、製造コストの抑制と高性能化とを図る。A glass paste containing a silicate glass as an insulating material as a main component and a photosensitive material added is applied to the parent substrate. Next, the glass paste is exposed and solidified using a photomask. Next, the glass paste which is not solidified is removed to provide an opening. Next, the glass paste is baked to form a glass layer. Subsequent to the series of steps described above, after the formation of the glass layer, a plurality of plating layers are formed on the silver electrode on the bottom surface of the opening of the glass layer to form a bonding electrode. Through the above steps, a chip element is manufactured while reducing the amount of metal material used in the electrode used for wire bonding, and without using a resist for electrode formation, thereby reducing manufacturing cost and improving performance.

Description

この発明は、ワイヤボンディングによって実装基板やパッケージ基板などに実装されるチップ素子に関する。   The present invention relates to a chip element mounted on a mounting substrate, a package substrate or the like by wire bonding.

従来のチップ素子の構成例を図１に示す。   A configuration example of a conventional chip element is shown in FIG.

図１（Ａ）は特許文献１に開示されたチップ素子の平面図である。このチップ素子は、矩形平板状の誘電体基板１１０に、２つのマイクロストリップ線路１１２Ａ，１１２Ｂを設けてフィルタを構成している。マイクロストリップ線路１１２Ａ，１１２Ｂの短絡端は共通のスルーホール１１１により、裏主面の接地電極（不図示）に導通させている。また、各マイクロストリップ線路１１２Ａ，１１２Ｂには、ワイヤボンディングによりワイヤ１５０Ａ，１５０Ｂが接続され、実装基板（不図示）の入出力電極に導通させている。   FIG. 1A is a plan view of the chip element disclosed in Patent Document 1. FIG. In this chip element, a filter is configured by providing two microstrip lines 112A and 112B on a rectangular flat dielectric substrate 110. The short-circuit ends of the microstrip lines 112A and 112B are electrically connected to a ground electrode (not shown) on the back main surface through a common through hole 111. Further, the wires 150A and 150B are connected to the microstrip lines 112A and 112B by wire bonding, and are connected to input / output electrodes of a mounting substrate (not shown).

図１（Ｂ）は特許文献２に開示されたチップ素子の斜視図である。このチップ素子は、ローパスフィルタが設けられた回路チップ２１０をパッケージ基板２５０に載置する構成である。なお、このパッケージ基板２５０上には回路チップ２１０を覆うように、図示していないカバーが設けられる。回路チップ２１０の表主面にはローパスフィルタを構成する線路２１２が形成されている。また、パッケージ基板２５０には入出力パッド２５１Ａ，２５１Ｂが形成されている。回路チップ２１０の線路２１２とパッケージ基板２５０の入出力パッド２５１Ａ，２５１Ｂはワイヤ２８０Ａ，２８０Ｂにより接続されている。   FIG. 1B is a perspective view of the chip element disclosed in Patent Document 2. FIG. This chip element has a configuration in which a circuit chip 210 provided with a low-pass filter is placed on a package substrate 250. A cover (not shown) is provided on the package substrate 250 so as to cover the circuit chip 210. A line 212 constituting a low-pass filter is formed on the front main surface of the circuit chip 210. In addition, input / output pads 251A and 251B are formed on the package substrate 250. The line 212 of the circuit chip 210 and the input / output pads 251A and 251B of the package substrate 250 are connected by wires 280A and 280B.

また、特許文献３には、チップ素子に対する金ワイヤのボンディングを行う場合に、ボンディング性の観点から、金ワイヤを接続する電極として金電極を形成することが開示されている。   Further, Patent Document 3 discloses forming a gold electrode as an electrode for connecting a gold wire from the viewpoint of bondability when bonding a gold wire to a chip element.

金電極を形成する場合、第１の方法としては、金を含有するペースト状の電極材をスクリーン印刷等によりパターン形成したのち焼成する方法がある。   In the case of forming a gold electrode, as a first method, there is a method in which a paste-like electrode material containing gold is subjected to pattern formation by screen printing or the like and then fired.

また、第２の方法としては、蒸着、スパッタリング、またはメッキ等により、金の電極膜を全面に形成したのち、フォトリソグラフィプロセスでレジストを形成し、不要な金の電極膜をエッチングにより除去する方法がある。   As a second method, a gold electrode film is formed on the entire surface by vapor deposition, sputtering, plating, or the like, a resist is formed by a photolithography process, and unnecessary gold electrode films are removed by etching. There is.

また、第３の方法としては、フォトリソグラフィプロセスによりレジストのパターンを形成したのち、蒸着、スパッタリング、またはメッキ等により、金の電極膜をレジストの非形成部分に形成し、最後にレジスト膜を剥離する方法がある。
特開２００２−１５１９０８号公報 特開２００３−１３３８８１号公報 特開平０７−０４５４６８号公報 As a third method, after forming a resist pattern by a photolithography process, a gold electrode film is formed on a non-resist formation portion by vapor deposition, sputtering, plating, or the like, and finally the resist film is peeled off. There is a way to do it.
JP 2002-151908 A JP 2003-133881 A Japanese Patent Application Laid-Open No. 07-045468

近年の金属材の原価の高騰により、上記した各種方法により金電極を形成したチップ素子は、その原料コストが増大する傾向にある。また、近年の環境対策の厳格化により、レジスト等の化学物質の使用量は減少させる必要がある。その一方、チップ素子自体の高性能化への要望は大きい。   Due to the recent rise in the cost of metal materials, chip elements having gold electrodes formed by the various methods described above tend to increase in raw material costs. In addition, due to recent strict environmental measures, the amount of chemical substances such as resists must be reduced. On the other hand, there is a great demand for higher performance of the chip element itself.

そこで本発明の目的は、ワイヤボンディングに用いる電極における金属材使用量を低減するとともに、その電極形成に係るレジストを不要にでき、製造コストの抑制と高性能化とを図ることができるチップ素子および、その製造方法の提供にある。   Accordingly, an object of the present invention is to provide a chip element that can reduce the amount of metal material used in an electrode used for wire bonding, eliminate the need for a resist for forming the electrode, reduce manufacturing costs, and improve performance. And providing a manufacturing method thereof.

チップ素子において、基体の表主面に絶縁膜を形成する。絶縁膜にはボンディング用電極を構成する複数のメッキ層に対しての非メッキ性を持たせておく。さらに、電極パターン上の絶縁膜に開口を形成しておく。そして、絶縁膜に設けた開口内に露出する電極パターンを下地電極として、下地電極上に表層に金メッキ層を含む複数のメッキ層をメッキし、ボンディング用電極を形成する。   In the chip element, an insulating film is formed on the front main surface of the substrate. The insulating film has a non-plating property with respect to a plurality of plating layers constituting the bonding electrode. Further, an opening is formed in the insulating film on the electrode pattern. Then, using the electrode pattern exposed in the opening provided in the insulating film as a base electrode, a plurality of plating layers including a gold plating layer as a surface layer are plated on the base electrode to form a bonding electrode.

これにより、ボンディング用電極の製造工程において、基体の表主面全面にメッキ浴を施すようにしても、絶縁膜上にはメッキ層が形成されず、開口内に露出する電極パターン上にメッキ層が形成される。したがってメッキ層の形成面積及び含有金属の使用量を低減でき、メッキ層形成のための原料コストを低減できる。また、絶縁膜に設ける開口がマスクパターンの代わりとなり、メッキ層形成にレジスト処理を用いる必要が無くなる。したがって、レジスト処理に係るレジスト材自体、および、レジスト材の剥離、回収、再生、廃棄等の処理コストを不要にできる。このようにして形成するメッキ層のパターン精度は、絶縁膜の開口のパターン精度に従って定まるので、絶縁膜の開口のパターン精度を高めることで、チップ素子の高性能化が望める。   As a result, in the manufacturing process of the bonding electrode, even if the plating bath is applied to the entire front main surface of the substrate, the plating layer is not formed on the insulating film, but the plating layer is formed on the electrode pattern exposed in the opening. Is formed. Therefore, the formation area of the plating layer and the amount of contained metal can be reduced, and the raw material cost for forming the plating layer can be reduced. In addition, the opening provided in the insulating film replaces the mask pattern, and it is not necessary to use a resist process for forming the plating layer. Accordingly, it is possible to eliminate the processing cost for the resist material itself and the resist material peeling, recovery, regeneration, disposal, etc. related to the resist processing. Since the pattern accuracy of the plated layer formed in this way is determined according to the pattern accuracy of the opening of the insulating film, it is possible to improve the performance of the chip element by increasing the pattern accuracy of the opening of the insulating film.

また、チップ素子において、基体の表主面に絶縁膜を形成する。絶縁膜にはボンディング用電極を構成する複数のメッキ層に対しての非メッキ性を持たせておく。さらに、電極パターン上の絶縁膜に開口を形成しておく。そして、絶縁膜の開口に設けた導体を介して基体の電極パターンに導通する下地電極を絶縁膜上に形成する。そして、下地電極上に金メッキ層を含む複数のメッキ層をメッキし、ボンディング用電極を形成する。   In the chip element, an insulating film is formed on the front main surface of the substrate. The insulating film has a non-plating property with respect to a plurality of plating layers constituting the bonding electrode. Further, an opening is formed in the insulating film on the electrode pattern. Then, a base electrode that is electrically connected to the electrode pattern of the base is formed on the insulating film through a conductor provided in the opening of the insulating film. Then, a plurality of plating layers including a gold plating layer are plated on the base electrode to form a bonding electrode.

これにより、ボンディング用電極の製造工程において、基体の表主面全面にメッキ浴を施すようにしても、絶縁膜上にはメッキ層が形成されず、絶縁膜上に設けた下地電極上にメッキ層が形成される。したがってメッキ層の形成面積及び含有金属の使用量を低減でき、メッキ層形成のための原料コストを低減できる。また、絶縁膜上に設ける下地電極がマスクパターンの代わりとなり、メッキ層形成にレジスト処理を用いる必要が無くなる。したがって、レジスト処理に係るレジスト材自体、および、レジスト材の剥離、回収、再生、廃棄等の処理コストを不要にできる。このようにして形成するメッキ層のパターン精度は、下地電極のパターン精度に従って定まるので、下地電極のパターン精度を高めることで、チップ素子の高性能化が望める。   As a result, even if a plating bath is applied to the entire surface of the main surface of the substrate in the manufacturing process of the bonding electrode, no plating layer is formed on the insulating film, and plating is performed on the base electrode provided on the insulating film. A layer is formed. Therefore, the formation area of the plating layer and the amount of contained metal can be reduced, and the raw material cost for forming the plating layer can be reduced. Further, the base electrode provided on the insulating film replaces the mask pattern, and it is not necessary to use a resist process for forming the plating layer. Accordingly, it is possible to eliminate the processing cost for the resist material itself and the resist material peeling, recovery, regeneration, disposal, etc. related to the resist processing. Since the pattern accuracy of the plating layer formed in this way is determined according to the pattern accuracy of the base electrode, it is possible to improve the performance of the chip element by increasing the pattern accuracy of the base electrode.

基体は、複数の絶縁層を積層して、絶縁層間にも電極パターンを設けた構成であってもよい。   The substrate may have a configuration in which a plurality of insulating layers are stacked and an electrode pattern is provided between the insulating layers.

また、チップ素子において、基体の表主面に第１の絶縁膜を形成し、第１の絶縁膜の表主面に第２の絶縁膜を形成する。電極パターン上の第１の絶縁膜に開口を形成しておく。第１の絶縁膜上に絶縁膜上電極パターンを形成する。絶縁膜上電極パターンは、第１の絶縁膜の開口に設けた導体を介して基体の電極パターンに導通させる。絶縁膜上電極パターン上の第２の絶縁膜に開口を形成しておく。第２の絶縁膜上に下地電極を形成する。下地電極は、第２の絶縁膜の開口に設けた導体を介して絶縁膜上電極パターンに導通させる。ここで、第２の絶縁膜には、ボンディング用電極を構成する複数のメッキ層に対しての非メッキ性を持たせておく。そして、下地電極上に金メッキ層を含む複数のメッキ層をメッキし、ボンディング用電極を形成する。これにより、ボンディング用電極を、基体上の電極パターンの形成位置の上からずらして形成することができる。   In the chip element, a first insulating film is formed on the front main surface of the substrate, and a second insulating film is formed on the front main surface of the first insulating film. An opening is formed in the first insulating film on the electrode pattern. An electrode pattern on the insulating film is formed on the first insulating film. The electrode pattern on the insulating film is electrically connected to the electrode pattern on the base via a conductor provided in the opening of the first insulating film. An opening is formed in the second insulating film on the electrode pattern on the insulating film. A base electrode is formed on the second insulating film. The base electrode is electrically connected to the electrode pattern on the insulating film through a conductor provided in the opening of the second insulating film. Here, the second insulating film has non-plating properties with respect to a plurality of plating layers constituting the bonding electrode. Then, a plurality of plating layers including a gold plating layer are plated on the base electrode to form a bonding electrode. As a result, the bonding electrode can be formed shifted from the position where the electrode pattern is formed on the substrate.

また、ボンディング用電極の金メッキ層下に、金メッキ層よりも下地電極に対しての接着性が高い下地メッキ層を設けてもよい。これにより下地電極との接着性を高めながら金ワイヤとの接続性を高めることができる。   A base plating layer having higher adhesion to the base electrode than the gold plating layer may be provided under the gold plating layer of the bonding electrode. Thereby, the connectivity with the gold wire can be enhanced while enhancing the adhesion with the base electrode.

また、下地電極は銀を主成分とすれば高い導電性が望める。また、絶縁膜がケイ酸系ガラスを主成分とすれば、各種メッキ液との撥液性や、形成後の耐候性、絶縁膜下の回路パターンの機械的保護能力が望める。下地メッキ層はニッケルを主成分とすれば、銀を主成分とする下地電極との高い接着性が望める。   Further, if the base electrode is mainly composed of silver, high conductivity can be expected. Further, if the insulating film is mainly composed of silicate glass, liquid repellency with various plating solutions, weather resistance after formation, and mechanical protection ability of the circuit pattern under the insulating film can be expected. If the base plating layer contains nickel as a main component, high adhesion to a base electrode containing silver as a main component can be expected.

また、絶縁膜の形成に、フォトリソグラフィプロセスを採用することにより、極めて高精度なパターン形成が可能となる。   Further, by adopting a photolithography process for forming the insulating film, it is possible to form a pattern with extremely high accuracy.

また、電極パターンを伝送線路としてマイクロストリップ線路フィルタを構成してもよい。従来構成では、電極パターンを伝送線路としてマイクロストリップ線路フィルタを構成した場合、ワイヤのボンディング誤差によって伝送線路におけるインダクタンス成分が影響を受けていた。しかしながら、本発明のように絶縁膜に設けた開口を介して、ボンディング用電極を伝送線路に導通させる構成では、開口の形成位置が安定することによって伝送線路のインダクタンス成分が安定し、ワイヤのボンディング誤差による影響を低減させることができる。したがってマイクロストリップ線路フィルタのフィルタ特性を安定化できる。   Moreover, you may comprise a microstrip line filter by making an electrode pattern into a transmission line. In the conventional configuration, when a microstrip line filter is configured using an electrode pattern as a transmission line, an inductance component in the transmission line is affected by a wire bonding error. However, in the configuration in which the bonding electrode is electrically connected to the transmission line through the opening provided in the insulating film as in the present invention, the inductance position of the transmission line is stabilized by stabilizing the formation position of the opening, and the wire bonding is performed. The influence of errors can be reduced. Therefore, the filter characteristics of the microstrip line filter can be stabilized.

この発明によれば、メッキ層の形成工程がレジスト処理を伴わず簡易化する。さらに、メッキ層の形成面積や金属使用量、特に金メッキ層の形成面積や金使用量が低減する。したがってチップ素子の製造コストが抑制できる。また、チップ素子を高性能化、安定化できる。   According to the present invention, the plating layer forming process is simplified without the resist process. Furthermore, the formation area and metal usage of the plating layer, particularly the formation area and gold usage of the gold plating layer are reduced. Therefore, the manufacturing cost of the chip element can be suppressed. In addition, the chip element can be improved in performance and stabilized.

チップ素子の従来構成を説明する図である。It is a figure explaining the conventional structure of a chip element. 本発明に係るチップ素子の構成例を示す展開図である。It is an expanded view which shows the structural example of the chip element which concerns on this invention. 上記構成例の製造工程を説明するフローである。It is a flow explaining the manufacturing process of the said structural example. 本発明に係るチップ素子の他の構成例を示す展開図である。It is an expanded view which shows the other structural example of the chip element which concerns on this invention. 上記構成例の等価回路図である。It is an equivalent circuit diagram of the above configuration example. 本発明に係るチップ素子の他の構成例を示す展開図である。It is an expanded view which shows the other structural example of the chip element which concerns on this invention.

符号の説明Explanation of symbols

１，５１，８１…チップ素子
１０，６０，８０…誘電体基板
１１，６１…スルーホール
１２，６２，８２…主面電極
１３，６３，８３…接地電極
２０，７０，９０，９５…ガラス層
２１，７１，９６…ボンディング用電極
５０…金ワイヤ
２２，７２，９７…開口
７３…下地電極
９２…銀電極DESCRIPTION OF SYMBOLS 1,51,81 ... Chip element 10, 60, 80 ... Dielectric board | substrate 11, 61 ... Through hole 12, 62, 82 ... Main surface electrode 13, 63, 83 ... Ground electrode 20, 70, 90, 95 ... Glass layer 21, 71, 96 ... Bonding electrode 50 ... Gold wires 22, 72, 97 ... Opening 73 ... Base electrode 92 ... Silver electrode

以下、図２に示すチップ素子の構成例に基づいて本発明を説明する。同図（Ａ）はチップ素子の正面図であり、同図（Ｂ）は同図（Ａ）に示すＢ−Ｂ断面図である。以下で示すチップ素子は、さらに図示していないパッケージ基板や実装基板に実装され、金ワイヤのボンディングによりボンディング用電極がパッケージ基板や実装基板の入出力パッドに接続される。なお、パッケージ基板に実装される場合にはチップ素子を覆うように金属カバーが設けられ、さらに大規模な実装基板に表面実装されることになる。   Hereinafter, the present invention will be described based on the configuration example of the chip element shown in FIG. FIG. 2A is a front view of the chip element, and FIG. 2B is a cross-sectional view taken along line BB shown in FIG. Chip elements shown below are further mounted on a package substrate or mounting substrate (not shown), and bonding electrodes are connected to input / output pads of the package substrate or mounting substrate by bonding gold wires. In the case of mounting on a package substrate, a metal cover is provided so as to cover the chip element, and surface mounting is performed on a larger mounting substrate.

チップ素子１は、本発明の基体である小型直方体状の誘電体基板１０を備える。誘電体基板１０は、酸化チタン等のセラミックの誘電体からなり、比誘電率が約１１０で、基板厚みは３００μｍ、図示する横方向の寸法が約１．４ｍｍ、主面の短手方向寸法が約１．３ｍｍの基板である。   The chip element 1 includes a small rectangular parallelepiped dielectric substrate 10 which is a base body of the present invention. The dielectric substrate 10 is made of a ceramic dielectric material such as titanium oxide, has a relative dielectric constant of about 110, a substrate thickness of 300 μm, a horizontal dimension of about 1.4 mm, and a short side dimension of the main surface. The substrate is about 1.3 mm.

誘電体基板１０の裏主面には、全面に接地電極１３を形成している。この裏主面は、実装基板やパッケージ基板に配置される実装面である。接地電極１３は電極厚みが約１２μｍの銀電極と複数のメッキ層とからなる。複数のメッキ層は、銀電極上にニッケルを主成分とするニッケルメッキ層を形成し、そのニッケルメッキ層上にさらにパラジウムを主成分とするパラジウムメッキ層を形成し、さらにその上に金を主成分とする金メッキ層を形成したものである。なお、この接地電極１３の詳細な製造工程および構成については、本発明の本質とは関わらないため詳細な説明は省くが、一般的な工程および構成を採用することができる。   A ground electrode 13 is formed on the entire back surface of the dielectric substrate 10. This back main surface is a mounting surface disposed on the mounting substrate or the package substrate. The ground electrode 13 is composed of a silver electrode having a thickness of about 12 μm and a plurality of plating layers. The plurality of plating layers are formed by forming a nickel plating layer mainly containing nickel on the silver electrode, further forming a palladium plating layer mainly containing palladium on the nickel plating layer, and further using gold as a main layer. A gold plating layer as a component is formed. The detailed manufacturing process and configuration of the ground electrode 13 are not related to the essence of the present invention, and thus a detailed description thereof is omitted, but general processes and configurations can be employed.

誘電体基板１０の表主面には、全体としてＳ字状にパターン化した主面電極１２を形成している。この主面電極１２は、本発明の電極パターンであり、電極厚み約５μｍの銀電極である。この主面電極１２は、電極精度を改善するために、感光性材に金属銀粉末を分散させた感光性銀電極ペーストを塗布し、乾燥、感光により感光性材を固化して、現像するフォトリソグラフィプロセスにより高精度にパターンを形成し、その後、焼成してなる。   On the front main surface of the dielectric substrate 10, a main surface electrode 12 patterned in an S shape as a whole is formed. The main surface electrode 12 is an electrode pattern of the present invention, and is a silver electrode having an electrode thickness of about 5 μm. In order to improve the electrode accuracy, the main surface electrode 12 is a photo that is applied by applying a photosensitive silver electrode paste in which metallic silver powder is dispersed in a photosensitive material, drying, and solidifying the photosensitive material by photosensitivity. A pattern is formed with high accuracy by a lithography process, and then fired.

なお、誘電体基板１０の中央付近には、レーザ加工やブラスト加工により主面間を貫通する貫通孔を設け、貫通孔内に銀電極ペーストを充填形成したスルーホール１１を設けている。このスルーホール１１を介して、主面電極１２は接地電極１３に導通する。主面電極１２は、スルーホール１１を中心に互いに逆方向に巻いたスパイラル状の２つのマイクロストリップ線路１２Ａ，１２Ｂを構成している。このマイクロストリップ線路１２Ａ，１２Ｂは、スルーホール１１を共通の短絡端としていて、それぞれ一端短絡、一端開放の１／４波長共振器の共振線路を構成している。この２つの１／４波長共振器はスルーホール１１のインダクタンス成分を介して結合し、フィルタを構成している。   In the vicinity of the center of the dielectric substrate 10, a through hole penetrating between the main surfaces is provided by laser processing or blasting, and a through hole 11 filled with a silver electrode paste is provided in the through hole. The main surface electrode 12 is electrically connected to the ground electrode 13 through the through hole 11. The main surface electrode 12 constitutes two spiral microstrip lines 12A and 12B wound in opposite directions around the through hole 11. The microstrip lines 12A and 12B have a through-hole 11 as a common short-circuited end, and constitute a resonant line of a quarter-wave resonator with one end short-circuited and one end open, respectively. The two quarter-wave resonators are coupled via the inductance component of the through hole 11 to form a filter.

誘電体基板１０と主面電極１２との表層側には、本発明の絶縁膜であるガラス層２０を厚み１５μｍ以上として形成している。このガラス層２０は、結晶性ＳｉＯ２や硼珪酸ガラスなどのケイ酸系ガラスを主成分としている。このガラス層２０の成分は、後述するボンディング用電極２１Ａ，２１Ｂの複数のメッキ層の成分に対して非メッキ性を有する。ガラス層２０の、誘電体基板１０のスルーホール１１両脇の主面電極１２上には、２つの開口２２Ａ，２２Ｂを設け、開口２２Ａ，２２Ｂ内にボンディング用電極２１Ａ，２１Ｂを設けている。開口２２Ａ，２２Ｂ下に位置する（露出する）主面電極が、本発明の下地電極を構成する。これらの開口２２Ａ，２２Ｂの形成精度を改善するため、ガラス層２０は感光性材を含む感光性ガラスペーストを誘電体基板１０に塗布し、乾燥、感光により感光性材を固化して、現像するフォトリソグラフィプロセスによりパターンを高精度に形成し、その後、焼成することで形成している。このガラス層２０によって、表主面電極パターンを機械的に保護するとともにフィルタの耐候性を向上させることができる。なお、ガラス層２０の各種寸法は、誘電体基板１０とガラス層２０との密着度や耐環境性、周波数特性などを考慮して適宜設定すればよい。   On the surface layer side of the dielectric substrate 10 and the main surface electrode 12, a glass layer 20 which is an insulating film of the present invention is formed with a thickness of 15 μm or more. The glass layer 20 is mainly composed of silicate glass such as crystalline SiO 2 or borosilicate glass. The component of this glass layer 20 has non-plating property with respect to the component of the some plating layer of bonding electrode 21A, 21B mentioned later. Two openings 22A and 22B are provided on the main surface electrode 12 on both sides of the through hole 11 of the dielectric substrate 10 of the glass layer 20, and bonding electrodes 21A and 21B are provided in the openings 22A and 22B. The main surface electrode located (exposed) under the openings 22A and 22B constitutes the base electrode of the present invention. In order to improve the formation accuracy of these openings 22A and 22B, the glass layer 20 is coated with a photosensitive glass paste containing a photosensitive material on the dielectric substrate 10, dried, and solidified by photosensitive to develop the photosensitive material. A pattern is formed with high accuracy by a photolithography process, and is then baked. The glass layer 20 can mechanically protect the front principal surface electrode pattern and improve the weather resistance of the filter. The various dimensions of the glass layer 20 may be set as appropriate in consideration of the degree of adhesion between the dielectric substrate 10 and the glass layer 20, environmental resistance, frequency characteristics, and the like.

ガラス層２０の２つの開口２２Ａ，２２Ｂ内には、開口２２Ａ，２２Ｂ下の主面電極１２と導通するボンディング用電極２１Ａ，２１Ｂを設けている。これらのボンディング用電極２１Ａ，２１Ｂは複数のメッキ層を形成したものである。具体的には、主面電極１２と導通する最下層に、ニッケルを主成分とする約３μｍ厚のニッケルメッキ層を無電解メッキにより形成し、ニッケルメッキの上層に、パラジウムを主成分とする約０．１μｍ厚のパラジウムメッキ層を無電解メッキにより形成し、パラジウムメッキの上層に、金ワイヤ５０Ａ，５０Ｂとの接続性を高めるために金を主成分とする約０．１μｍ厚の金メッキ層を無電解メッキにより形成している。ここではニッケルメッキ層が本発明の下地メッキ層である。なお、ここでは下地メッキ層としてニッケルメッキ層を設けるとともに、主面電極１２に対して触媒等を用いて適切な表面処理を施すことで、主面電極１２とニッケルメッキ層との間にメッキ性を与える。なお、下地メッキ層および主面電極は、良好なメッキ性が得られるような成分であれば好適であり、上記パラジウムメッキ層は除いてもよく、パラジウムメッキ層に替えて他のメッキ層を設けてもよい。ここで用いた各メッキ層の主成分は、いずれもガラス層２０に対してメッキ性がないものであるが、ガラス層２０に対してメッキ性がないものであれば他のどのような主成分を用いてもよい。   In the two openings 22A and 22B of the glass layer 20, bonding electrodes 21A and 21B that are electrically connected to the main surface electrode 12 below the openings 22A and 22B are provided. These bonding electrodes 21A and 21B are formed by forming a plurality of plating layers. Specifically, a nickel plating layer having a thickness of about 3 μm, which is mainly composed of nickel, is formed by electroless plating on the lowermost layer that is electrically connected to the main surface electrode 12. A palladium plating layer having a thickness of 0.1 μm is formed by electroless plating, and a gold plating layer having a thickness of about 0.1 μm mainly composed of gold is formed on the upper layer of the palladium plating in order to improve the connectivity with the gold wires 50A and 50B. It is formed by electroless plating. Here, the nickel plating layer is the base plating layer of the present invention. Here, a nickel plating layer is provided as a base plating layer, and an appropriate surface treatment is performed on the main surface electrode 12 using a catalyst or the like, so that the plating property is provided between the main surface electrode 12 and the nickel plating layer. give. Note that the base plating layer and the main surface electrode are suitable as long as they can provide good plating properties. The palladium plating layer may be omitted, and another plating layer is provided in place of the palladium plating layer. May be. The main component of each plating layer used here is one that does not have a plating property with respect to the glass layer 20, but any other main component as long as it does not have a plating property with respect to the glass layer 20. May be used.

ボンディング用電極２１Ａ，２１Ｂにはそれぞれ、金ワイヤ５０Ａ，５０Ｂがボンディングされる。これら金ワイヤ５０Ａ，５０Ｂは高周波信号の入出力端子である実装基板の入出力パッド（不図示）に接続する。金ワイヤ５０Ａ，５０Ｂは、ボンディング用電極２１Ａ，２１Ｂにボンディングすることで、主面電極１２によるマイクロストリップ線路１２Ａ，１２Ｂに対してタップ結合することになる。   Gold wires 50A and 50B are bonded to the bonding electrodes 21A and 21B, respectively. These gold wires 50A and 50B are connected to input / output pads (not shown) of the mounting board which are input / output terminals for high-frequency signals. The gold wires 50A and 50B are tapped to the microstrip lines 12A and 12B formed by the main surface electrode 12 by bonding to the bonding electrodes 21A and 21B.

なお図示していないが、誘電体基板１０の側面には何の電極も設けていない。   Although not shown, no electrode is provided on the side surface of the dielectric substrate 10.

以上のように、ガラス層２０に複数のメッキ層に対しての非メッキ性を付与しているので、ボンディング用電極をメッキ処理により形成しても、ガラス層２０上にメッキ層が形成されることがない。また、複数のメッキ層によりボンディング用電極を構成することで、各メッキ層間の密着性を向上させるとともに、主面電極との接続性と金ワイヤとの接続性をともに良好なものにしている。   As described above, since the non-plating property for the plurality of plating layers is imparted to the glass layer 20, even if the bonding electrode is formed by plating, a plating layer is formed on the glass layer 20. There is nothing. Further, by forming a bonding electrode with a plurality of plating layers, the adhesion between the plating layers is improved, and the connectivity with the main surface electrode and the connectivity with the gold wire are both improved.

ここでは、主面電極として銀を主成分とする例を説明したが、銀ではなく、安価で導電率の高い他の成分、例えば銅やアルミニウム、銀−パラジウム合金などを主成分とする電極を用いてもよい。この場合、ボンディング用電極の複数のメッキ層の成分を適切に設定し、表面処理を適切に実施することで、主面電極の成分がどのようなものであっても本発明を実施することが可能になる。   Here, an example in which silver is the main component has been described as the main surface electrode, but an electrode that is not silver but has other main components such as copper, aluminum, silver-palladium alloy, etc. at low cost and high conductivity is used. It may be used. In this case, by appropriately setting the components of the plurality of plating layers of the bonding electrode and appropriately performing the surface treatment, the present invention can be carried out regardless of the component of the main surface electrode. It becomes possible.

以上の構成のフィルタ素子は、図３に示す工程を経て製造される。
（Ｓ１）まず、いずれの面にも電極を形成していない誘電体親基板を用意する。
（Ｓ２）次に、上記親基板に対して、裏主面側に導電体ペーストをスクリーン印刷し、焼成を経て接地電極および端子電極を形成する。
（Ｓ３）次に、親基板に対して、表主面側に感光性銀電極ペーストを印刷し、露光、現像するフォトリソグラフィプロセスによりパターンを形成し、その後、焼成して各主面電極を形成する。
（Ｓ４）次に、親基板の表主面側に絶縁性材を主成分とし感光性材を添加した感光性ガラスペーストを印刷し、フォトマスクを用いて前記ペーストを露光し、固化していない前記ペーストを除去して開口を設ける現像を行うフォトリソグラフィプロセスによりパターンを形成し、その後、焼成を経てガラス層を形成する。なお、この工程に用いる露光装置などは、上記主面電極の形成工程で用いたものとする。これにより、露光装置などを複数用意する必要が無くなり製造コストの削減が可能になる。
（Ｓ５）次に、親基板の表主面側全体を複数回、メッキ液を異ならせながらメッキ浴する。最初にメッキ浴に用いるメッキ液は、銀電極に対してメッキ性があり、ガラス層に対してメッキ性のないニッケルを主成分とするものとする。また、最後にメッキ浴に用いるメッキ液は、金ワイヤとのボンディング性に優れ、ガラス層に対してメッキ性のない金を主成分とするものとする。The filter element having the above configuration is manufactured through the steps shown in FIG.
(S1) First, a dielectric parent substrate having no electrode formed on any surface is prepared.
(S2) Next, a conductive paste is screen-printed on the back main surface side of the parent substrate, and a ground electrode and a terminal electrode are formed through firing.
(S3) Next, a photosensitive silver electrode paste is printed on the front main surface side of the parent substrate, a pattern is formed by a photolithography process that exposes and develops, and then fired to form each main surface electrode. To do.
(S4) Next, a photosensitive glass paste containing an insulating material as a main component and added with a photosensitive material is printed on the front main surface side of the parent substrate, and the paste is exposed and solidified using a photomask. A pattern is formed by a photolithography process in which the paste is removed and development is performed to provide an opening, and then a glass layer is formed through baking. The exposure apparatus used in this step is used in the main surface electrode forming step. As a result, it is not necessary to prepare a plurality of exposure apparatuses and the manufacturing cost can be reduced.
(S5) Next, the entire front main surface side of the parent substrate is subjected to a plating bath a plurality of times while varying the plating solution. The plating solution initially used in the plating bath is mainly composed of nickel that has a plating property with respect to the silver electrode and has no plating property with respect to the glass layer. Finally, the plating solution used for the plating bath is mainly composed of gold that is excellent in bonding property with a gold wire and has no plating property with respect to the glass layer.

（Ｓ６）次に、上記のようにして構成した親基板からダイシングなどにより多数の素体を切り出し、チップ素子を製造する。 (S6) Next, many element bodies are cut out from the parent substrate configured as described above by dicing or the like to manufacture chip elements.

以上のように、このチップ素子を製造することで、チップ素子の親基板にメッキ浴において付着するメッキ液が、略ガラス層の開口内だけでメッキ層となり、メッキ層の形成面積及び含有金属の使用量を低減でき、このメッキ層のための原料コストを低減できる。   As described above, by manufacturing this chip element, the plating solution adhering to the parent substrate of the chip element in the plating bath becomes a plating layer only within the opening of the glass layer, and the formation area of the plating layer and the contained metal The amount used can be reduced, and the raw material cost for this plating layer can be reduced.

また、その際に特にレジスト処理が不要となり、その処理コストやレジスト原料コストを低減できる。このようにレジスト処理を必要とせずに、フォトリソグラフィプロセスによりボンディング用電極のパターン精度を高めることができ、チップ素子の高性能化が望める。   Further, at that time, resist processing is not particularly necessary, and the processing cost and resist material cost can be reduced. Thus, without requiring resist processing, the pattern accuracy of the bonding electrode can be increased by a photolithography process, and high performance of the chip element can be expected.

次に、チップ素子の他の構成例について図４に基づいて説明する。同図（Ａ）はチップ素子の正面図であり、同図（Ｂ）は同図（Ａ）に示すＢ−Ｂ断面図である。以下の説明では、上述の構成例と同一の構成では、場合によっては説明を省く。   Next, another configuration example of the chip element will be described with reference to FIG. FIG. 2A is a front view of the chip element, and FIG. 2B is a cross-sectional view taken along line BB shown in FIG. In the following description, in the same configuration as the above-described configuration example, description will be omitted depending on circumstances.

チップ素子５１は、本発明の基板である小型直方体状の誘電体基板６０を備える。誘電体基板６０の裏主面には、全面に接地電極６３を形成している。誘電体基板６０の表主面には、全体としてＳ字状にパターン化した主面電極６２を形成している。又、誘電体基板６０には、その中央付近にスルーホール６１を設けている。主面電極６２は、互いに逆方向に巻いたスパイラル状の２つのマイクロストリップ線路６２Ａ，６２Ｂを構成している。   The chip element 51 includes a small rectangular parallelepiped dielectric substrate 60 which is the substrate of the present invention. A ground electrode 63 is formed on the entire main surface of the back surface of the dielectric substrate 60. On the front main surface of the dielectric substrate 60, a main surface electrode 62 patterned in an S shape as a whole is formed. The dielectric substrate 60 is provided with a through hole 61 near the center thereof. The main surface electrode 62 constitutes two spiral microstrip lines 62A and 62B wound in opposite directions.

誘電体基板６０と主面電極６２との表層側には、本発明の絶縁膜であるガラス層７０を形成している。このガラス層７０は、結晶性ＳｉＯ２や硼珪酸ガラスなどのケイ酸系ガラスを主成分としている。このガラス層７０の成分は、後述するボンディング用電極７１Ａ，７１Ｂの複数のメッキ層の成分に対して非メッキ性を有する。ガラス層７０の、スルーホール６１両脇の主面電極６２上には、２つの開口７２Ａ，７２Ｂを設けている。   A glass layer 70 which is an insulating film of the present invention is formed on the surface layer side of the dielectric substrate 60 and the main surface electrode 62. This glass layer 70 is mainly composed of silicate glass such as crystalline SiO 2 or borosilicate glass. The component of this glass layer 70 has non-plating property with respect to the component of the some plating layer of bonding electrode 71A, 71B mentioned later. Two openings 72 </ b> A and 72 </ b> B are provided on the main surface electrode 62 on both sides of the through hole 61 of the glass layer 70.

ガラス層７０の２つの開口７２Ａ，７２Ｂ内には、非感光性の銀電極ペーストを充填し、乾燥、焼成する工程により銀電極を形成している。また、ガラス層７０上の、開口７２Ａ，７２Ｂ周囲には、矩形で開口７２Ａ，７２Ｂよりも大きなサイズの銀電極を、感光性の銀ペーストのフォトリソグラフィプロセスによりパターン形成している。このガラス層７０上の、開口７２Ａ，７２Ｂ周囲に設けた銀電極が、本発明の下地電極７３Ａ，７３Ｂである。なお、開口７２Ａ，７２Ｂ内の銀電極は、上述のように下地電極７３Ａ，７３Ｂとは別の工程で形成してもよいが、下地電極７３Ａ，７３Ｂと同時に、感光性の銀電極ペーストを開口内に充填して形成してもよい。   In the two openings 72A and 72B of the glass layer 70, a non-photosensitive silver electrode paste is filled, and a silver electrode is formed by a process of drying and baking. Further, around the openings 72A and 72B on the glass layer 70, rectangular silver electrodes having a size larger than the openings 72A and 72B are patterned by a photolithography process using a photosensitive silver paste. The silver electrodes provided around the openings 72A and 72B on the glass layer 70 are the base electrodes 73A and 73B of the present invention. The silver electrodes in the openings 72A and 72B may be formed in a process different from the base electrodes 73A and 73B as described above, but a photosensitive silver electrode paste is opened simultaneously with the base electrodes 73A and 73B. It may be formed by filling the inside.

下地電極７３Ａ，７３Ｂ上には、複数のメッキ層を形成してボンディング用電極７１Ａ，７１Ｂを構成している。したがって、ボンディング用電極７１Ａ，７１Ｂは開口７２Ａ，７２Ｂ下の主面電極６２と導通する。ボンディング用電極７１Ａ，７１Ｂの、下地電極７３Ａ，７３Ｂと接する最下層には、本発明の下地メッキ層であるニッケルメッキ層を約３μｍ形成し、ニッケルメッキの上層にはパラジウムメッキ層を約０．１μｍ形成し、パラジウムメッキの上層には金メッキ層を約０．１μｍ形成している。このようにして複数層のメッキ層を設けることで、各メッキ層間の密着性を向上させている。   A plurality of plating layers are formed on the base electrodes 73A and 73B to form bonding electrodes 71A and 71B. Therefore, the bonding electrodes 71A and 71B are electrically connected to the main surface electrode 62 below the openings 72A and 72B. About 3 μm of the nickel plating layer, which is the base plating layer of the present invention, is formed on the lowermost layer of the bonding electrodes 71A and 71B in contact with the base electrodes 73A and 73B. 1 μm is formed, and about 0.1 μm of a gold plating layer is formed on the upper layer of palladium plating. By providing a plurality of plating layers in this manner, the adhesion between the plating layers is improved.

なお、ここでは下地メッキ層としてニッケルメッキ層を設けるとともに、下地電極７３Ａ，７３Ｂに対して触媒等を用いて適切な表面処理を施すことで、下地電極７３Ａ，７３Ｂとニッケルメッキ層との間にメッキ性を与える。なお、下地メッキ層および下地電極７３Ａ，７３Ｂは、良好なメッキ性が得られるような成分であれば好適であり、上記パラジウムメッキ層は除いてもよく、パラジウムメッキ層に替えて他のメッキ層を設けてもよい。ここで用いた各メッキ層の主成分は、いずれもガラス層７０に対してメッキ性がないものであるが、ガラス層７０に対してメッキ性がないものであれば他のどのような主成分を用いてもよい。   Here, a nickel plating layer is provided as a base plating layer, and an appropriate surface treatment is performed on the base electrodes 73A and 73B using a catalyst or the like, so that the base electrodes 73A and 73B and the nickel plating layer are interposed. Gives plating properties. Note that the base plating layer and the base electrodes 73A and 73B are suitable as long as they can provide good plating properties. The palladium plating layer may be omitted, and other plating layers may be used instead of the palladium plating layer. May be provided. The main component of each plating layer used here is one that does not have a plating property with respect to the glass layer 70, but any other main component that has no plating property with respect to the glass layer 70. May be used.

ボンディング用電極７１Ａ，７１Ｂにはそれぞれ、高周波信号の入出力端子である実装基板の入出力パッド（不図示）に接続された金ワイヤがボンディングされることになる。これにより、主面電極６２によるマイクロストリップ線路６２Ａ，６２Ｂに対して金ワイヤがタップ結合することになる。   Each of the bonding electrodes 71A and 71B is bonded with a gold wire connected to an input / output pad (not shown) of a mounting board which is an input / output terminal for a high-frequency signal. As a result, the gold wire is tapped to the microstrip lines 62A and 62B formed by the main surface electrode 62.

以上のように、ガラス層７０に複数のメッキ層に対しての非メッキ性を付与しているので、ボンディング用電極７１Ａ，７１Ｂをメッキ処理により形成することができる。また、ボンディング用電極７１Ａ，７１Ｂを複数のメッキ層とすることで、各メッキ層間の密着性を向上させるとともに、主面電極６２との接続性と金ワイヤとの接続性をともに良好なものにしている。   As described above, since the non-plating property for the plurality of plating layers is imparted to the glass layer 70, the bonding electrodes 71A and 71B can be formed by plating. Further, by forming the bonding electrodes 71A and 71B as a plurality of plating layers, the adhesion between the plating layers is improved, and the connectivity with the main surface electrode 62 and the connectivity with the gold wire are both improved. ing.

このような構成のチップ素子を製造する場合には、チップ素子の親基板にメッキ浴により付着するメッキ液が、略ガラス層の表主面に設けた下地電極上でだけメッキ層をなし、メッキ層の形成面積及び含有金属の使用量を低減でき、このメッキ層のための原料コストを低減できる。   When manufacturing a chip element having such a structure, the plating solution adhering to the parent substrate of the chip element by a plating bath forms a plating layer only on the base electrode provided on the front main surface of the glass layer, and plating is performed. The formation area of the layer and the amount of contained metal can be reduced, and the raw material cost for the plating layer can be reduced.

また、その際に特にレジスト処理が不要となり、その処理コストやレジスト原料コストを低減できる。このようにレジスト処理を必要とせずに、フォトリソグラフィプロセスによりボンディング用電極のパターン精度を高めることができ、チップ素子の高性能化が望める。   Further, at that time, resist processing is not particularly necessary, and the processing cost and resist material cost can be reduced. Thus, without requiring resist processing, the pattern accuracy of the bonding electrode can be increased by a photolithography process, and high performance of the chip element can be expected.

ここで、このチップ素子に設けられるマイクロストリップ線路６２Ａ，６２Ｂによるフィルタの等価回路図を図５に示す。   Here, FIG. 5 shows an equivalent circuit diagram of a filter formed by the microstrip lines 62A and 62B provided in the chip element.

マイクロストリップ線路６２Ａ，６２Ｂは、共通の短絡端であるスルーホールを介してチップ素子の裏主面に設けた接地電極に接続される。したがって、マイクロストリップ線路６２Ａ，６２Ｂの接続点Ｐ１は、スルーホールの誘導性成分Ｌｗ３と抵抗成分Ｒ１とを介して接地される。マイクロストリップ線路６２Ａは、等価的に伝送線路ＬｓＡ1と伝送線路ＬｓＡ２とからなり、マイクロストリップ線路６２Ｂは、伝送線路ＬｓＢ1と伝送線路ＬｓＢ２とからなる。伝送線路ＬｓＡ1およびＬｓＡ２、伝送線路ＬｓＢ1およびＬｓＢ２は、ガラス層の開口が形成された位置である接続点Ｐ２およびＰ３により分けられ、接続点Ｐ２，Ｐ３は実装基板側の入出力端子Ｉ／Ｏに、ボンディング用電極および金ワイヤの誘導性成分Ｌｗ１，Ｌｗ２を介して接続される。   The microstrip lines 62A and 62B are connected to a ground electrode provided on the back main surface of the chip element through a through hole which is a common short-circuited end. Therefore, the connection point P1 between the microstrip lines 62A and 62B is grounded through the inductive component Lw3 and the resistance component R1 of the through hole. The microstrip line 62A is equivalently composed of a transmission line LsA1 and a transmission line LsA2, and the microstrip line 62B is composed of a transmission line LsB1 and a transmission line LsB2. The transmission lines LsA1 and LsA2 and the transmission lines LsB1 and LsB2 are divided by connection points P2 and P3 that are positions where the openings of the glass layer are formed, and the connection points P2 and P3 are connected to the input / output terminals I / O on the mounting board side. They are connected via the bonding electrodes and the inductive components Lw1 and Lw2 of the gold wire.

このように、このチップ素子のフィルタ等価回路は構成される。この構成では、ガラス層の開口に導電体を設けて、その導電体にボンディング用電極と金ワイヤとを接続するので、接続点Ｐ２およびＰ３は、ガラス層の開口が形成された位置となる。   Thus, the filter equivalent circuit of this chip element is configured. In this configuration, a conductor is provided in the opening of the glass layer, and the bonding electrode and the gold wire are connected to the conductor. Therefore, the connection points P2 and P3 are positions where the opening of the glass layer is formed.

一方、ガラス層の開口に導電体を設けず、主面電極上に直接、金ワイヤをボンディングする従来構成では、ボンディング位置がそのまま接続点Ｐ２およびＰ３となってしまう。ボンディング工程の性質上、金ワイヤのボンディング位置には精度誤差が存在するので、主面電極上の金ワイヤのボンディング位置に誤差が有れば、接続点Ｐ２およびＰ３がずれて伝送線路ＬｓＡ1およびＬｓＡ２、伝送線路ＬｓＢ1およびＬｓＢ２が不定となる。このように従来構成では、ボンディング位置の誤差による影響がフィルタ特性におよんでしまうことになる。その場合、このフィルタの入出力インピーダンスにばらつきが生じることになる。   On the other hand, in the conventional configuration in which a gold wire is bonded directly on the main surface electrode without providing a conductor in the opening of the glass layer, the bonding positions are directly connected points P2 and P3. Since there is an accuracy error in the bonding position of the gold wire due to the nature of the bonding process, if there is an error in the bonding position of the gold wire on the main surface electrode, the connection points P2 and P3 are shifted and the transmission lines LsA1 and LsA2 are shifted. The transmission lines LsB1 and LsB2 are indefinite. Thus, in the conventional configuration, the influence of the bonding position error affects the filter characteristics. In this case, the input / output impedance of this filter varies.

このように従来構成では問題が生じるが、一方、本実施形態のチップ素子の構成のように、開口に導電体を設け、導電体に接続したボンディング用電極に対して、金ワイヤをボンディングするようにする場合には、接続点Ｐ２およびＰ３のボンディング位置によるずれが低減され、フィルタ特性に影響がおよぶことが殆ど無い。これにより、タップ接続の接続位置にずれが生じることが殆ど無くなり、このフィルタの入出力インピーダンスに生じるばらつきが低減する。   As described above, there is a problem in the conventional configuration. On the other hand, as in the configuration of the chip element of the present embodiment, a conductor is provided in the opening, and a gold wire is bonded to the bonding electrode connected to the conductor. In this case, the displacement due to the bonding position of the connection points P2 and P3 is reduced, and the filter characteristics are hardly affected. Thereby, there is almost no deviation in the connection position of the tap connection, and variations occurring in the input / output impedance of this filter are reduced.

次に、図６に示すチップ素子の他の構成例に基づいて本発明を説明する。同図はチップ素子の断面図である。以下の説明では、上述の構成例と同一の構成では、場合によっては説明を省く。   Next, the present invention will be described based on another configuration example of the chip element shown in FIG. This figure is a sectional view of the chip element. In the following description, in the same configuration as the above-described configuration example, description will be omitted depending on circumstances.

このチップ素子は、ガラス層を複数層に形成し、ボンディング用電極の位置を、主面電極のパターンによらずに設定したものである。   In this chip element, a glass layer is formed in a plurality of layers, and the position of the bonding electrode is set regardless of the pattern of the main surface electrode.

チップ素子８１は、小型直方体状の誘電体基板８０を備える。誘電体基板８０の裏主面には、全面に接地電極８３を形成している。誘電体基板８０の表主面には、主面電極８２を形成している。   The chip element 81 includes a small rectangular parallelepiped dielectric substrate 80. A ground electrode 83 is formed on the entire back surface of the dielectric substrate 80. A main surface electrode 82 is formed on the front main surface of the dielectric substrate 80.

誘電体基板８０と主面電極８２との表層側には、ガラス層９０を形成している。このガラス層９０は、結晶性ＳｉＯ２および硼珪酸ガラスを主成分としている。主面電極８２上のガラス層９０には、開口を設けている。ガラス層９０の開口内と、開口の周囲には、非感光性の銀電極ペーストを印刷し、乾燥、焼成する工程により銀電極を形成している。   A glass layer 90 is formed on the surface layer side of the dielectric substrate 80 and the main surface electrode 82. The glass layer 90 is mainly composed of crystalline SiO 2 and borosilicate glass. An opening is provided in the glass layer 90 on the main surface electrode 82. In the opening of the glass layer 90 and around the opening, a silver electrode is formed by printing a non-photosensitive silver electrode paste, drying, and baking.

ガラス層９０の表層側には、さらに本発明の絶縁膜であるガラス層９５を形成している。このガラス層９５は、結晶性ＳｉＯ２および硼珪酸ガラスを主成分としている。ガラス層９０の銀電極９２上のガラス層９５には開口９７を設けている。開口９７下に位置する（露出する）銀電極９２が、本発明の下地電極を構成する。ガラス層９５の開口９７内には、複数のメッキ層が形成されていて、複数のメッキ層がボンディング用電極９６を構成している。このボンディング用電極９６は主面電極８２と導通する。ガラス層９５の開口９７下の銀電極と接する最下層にはニッケルメッキ層を約３μｍ形成し、ニッケルメッキの上層にはパラジウムメッキ層を約０．１μｍ形成し、パラジウムメッキの上層には金メッキを約０．１μｍ形成している。このようにして複数層のメッキ層を設けることで、各メッキ層間の密着性を向上させている。   A glass layer 95 which is an insulating film of the present invention is further formed on the surface layer side of the glass layer 90. This glass layer 95 is mainly composed of crystalline SiO 2 and borosilicate glass. An opening 97 is provided in the glass layer 95 on the silver electrode 92 of the glass layer 90. The silver electrode 92 positioned (exposed) under the opening 97 constitutes the base electrode of the present invention. A plurality of plating layers are formed in the opening 97 of the glass layer 95, and the plurality of plating layers constitute a bonding electrode 96. The bonding electrode 96 is electrically connected to the main surface electrode 82. About 3 μm of nickel plating layer is formed on the bottom layer in contact with the silver electrode under the opening 97 of the glass layer 95, about 0.1 μm of palladium plating layer is formed on the upper layer of nickel plating, and gold plating is formed on the upper layer of palladium plating. About 0.1 μm is formed. By providing a plurality of plating layers in this manner, the adhesion between the plating layers is improved.

以上のように、このチップ素子を製造することで、チップ素子の親基板にメッキ浴において付着するメッキ液が、略ガラス層の表主面に設けた銀電極上だけでメッキ層を形成し、メッキ層の形成面積及び含有金属の使用量を低減でき、このメッキ層のための原料コストを低減できる。   As described above, by manufacturing this chip element, the plating solution adhering to the parent substrate of the chip element in the plating bath forms a plating layer only on the silver electrode provided on the front main surface of the glass layer, The formation area of the plating layer and the amount of contained metal can be reduced, and the raw material cost for the plating layer can be reduced.

なお、上記した各実施形態での電極パターンの構成は製品仕様に応じた、どのような形状であっても良い。本発明は上記構成以外であっても適用でき、多様なチップ素子に採用できる。   The configuration of the electrode pattern in each of the above embodiments may be any shape according to product specifications. The present invention can be applied to configurations other than those described above, and can be applied to various chip elements.

Claims (10)

表主面に電極パターンを設けた基体と、表層に金メッキ層を含む複数のメッキ層からなり、金ワイヤが接続されるボンディング用電極と、を備えるチップ素子において、
前記電極パターン上に開口を形成して前記基体の表主面に形成した、前記複数のメッキ層に対して非メッキ性を有する絶縁膜を備え、
前記絶縁膜に設けた開口内に露出する前記電極パターンを下地電極として、前記下地電極上に前記複数のメッキ層をメッキして、前記ボンディング用電極を形成したことを特徴とするチップ素子。In a chip element comprising: a base provided with an electrode pattern on the front main surface; and a bonding electrode composed of a plurality of plating layers including a gold plating layer on the surface, to which a gold wire is connected,
An insulating film having a non-plating property with respect to the plurality of plating layers formed on the front main surface of the base by forming an opening on the electrode pattern,
A chip element, wherein the bonding electrode is formed by plating the plurality of plating layers on the base electrode using the electrode pattern exposed in the opening provided in the insulating film as a base electrode. 表主面に電極パターンを設けた基体と、表層に金メッキ層を含む複数のメッキ層からなり、金ワイヤが接続されるボンディング用電極と、を備えるチップ素子において、
前記電極パターン上に開口を形成して前記基体の表主面に積層した、前記複数のメッキ層に対して非メッキ性を有する絶縁膜と、
前記絶縁膜の開口に設けた導体を介して前記電極パターンに導通する、前記絶縁膜の表主面に配した下地電極と、
を備え
前記下地電極上に、前記複数のメッキ層をメッキして、前記ボンディング用電極を形成したことを特徴とするチップ素子。In a chip element comprising: a base provided with an electrode pattern on the front main surface; and a bonding electrode composed of a plurality of plating layers including a gold plating layer on the surface, to which a gold wire is connected,
An insulating film having a non-plating property with respect to the plurality of plating layers, wherein an opening is formed on the electrode pattern and laminated on a front main surface of the substrate;
A base electrode disposed on a front main surface of the insulating film, which is electrically connected to the electrode pattern through a conductor provided in an opening of the insulating film;
A chip element, wherein the bonding electrode is formed by plating the plurality of plating layers on the base electrode. 前記基体は、複数の絶縁層を積層して、前記絶縁層間にも電極パターンを設けた構成である請求項１又は２に記載のチップ素子。   The chip element according to claim 1, wherein the base has a configuration in which a plurality of insulating layers are stacked and an electrode pattern is provided between the insulating layers. 表主面に電極パターンを設けた基体と、表層に金メッキ層を含む複数のメッキ層からなり、金ワイヤが接続されるボンディング用電極と、を備えるチップ素子において、
前記電極パターン上に開口を形成して前記基体の表主面に積層した第１の絶縁膜と、
前記第１の絶縁膜の開口に設けた導体を介して前記電極パターンに導通する、前記第１の絶縁膜の表主面に配した絶縁膜上電極パターンと、
前記絶縁膜上電極パターン上に開口を形成して前記第１の絶縁膜の表主面に積層した第２の絶縁膜と、
前記第２の絶縁膜の開口に設けた導体を介して前記絶縁膜上電極パターンに導通する、前記第２の絶縁膜の表主面に配した下地電極と、
を備え、
前記第２の絶縁膜は、前記複数のメッキ層に対して非メッキ性を有し、
前記下地電極上に、前記複数のメッキ層をメッキして、前記ボンディング用電極を形成したことを特徴とするチップ素子。In a chip element comprising: a base provided with an electrode pattern on the front main surface; and a bonding electrode composed of a plurality of plating layers including a gold plating layer on the surface, to which a gold wire is connected,
A first insulating film having an opening formed on the electrode pattern and laminated on a front main surface of the substrate;
An electrode pattern on the insulating film disposed on the front main surface of the first insulating film, which is electrically connected to the electrode pattern through a conductor provided in the opening of the first insulating film;
A second insulating film formed on the front main surface of the first insulating film by forming an opening on the electrode pattern on the insulating film;
A base electrode disposed on a front main surface of the second insulating film, which is electrically connected to the electrode pattern on the insulating film through a conductor provided in an opening of the second insulating film;
With
The second insulating film has non-plating properties for the plurality of plating layers,
A chip element, wherein the bonding electrodes are formed by plating the plurality of plating layers on the base electrode. 前記ボンディング用電極は、前記金メッキ層下に、前記金メッキ層よりも前記下地電極に対しての接着性が高い下地メッキ層を備える請求項１〜４のいずれかに記載のチップ素子。   5. The chip element according to claim 1, wherein the bonding electrode includes a base plating layer having higher adhesion to the base electrode than the gold plating layer under the gold plating layer. 前記下地電極は銀を主成分とし、前記絶縁膜はケイ酸系ガラスを主成分とし、前記下地メッキ層はニッケルを主成分とする請求項５に記載のチップ素子。   The chip element according to claim 5, wherein the base electrode has silver as a main component, the insulating film has silicate glass as a main component, and the base plating layer has nickel as a main component. 前記絶縁膜はフォトリソグラフィプロセスにより前記開口を形成したものである請求項１〜６のいずれかに記載のチップ素子。   The chip element according to claim 1, wherein the insulating film has the opening formed by a photolithography process. 前記電極パターンを伝送線路としてマイクロストリップ線路フィルタを構成した請求項１〜７のいずれかに記載のチップ素子。   The chip element according to claim 1, wherein a microstrip line filter is configured using the electrode pattern as a transmission line. 表主面に電極パターンを設けた基体と、表層に金メッキ層を含む複数のメッキ層からなり、金ワイヤが接続されるボンディング用電極と、を備えるチップ素子の製造方法であって、
感光性材を分散させた絶縁性ペーストを前記基体に塗布し、フォトマスクを用いて前記絶縁性ペーストを感光させて固化し、固化していない前記絶縁性ペーストを除去して開口を設けて、前記複数のメッキ層に対して非メッキ性を有する絶縁膜を形成する絶縁膜形成工程と、
前記絶縁膜形成工程の後、前記開口の底面に複数回のメッキを施して前記複数のメッキ層を形成して前記ボンディング用電極を形成するボンディング用電極形成工程と、
を含むチップ素子の製造方法。A manufacturing method of a chip element comprising: a base provided with an electrode pattern on a front main surface; and a bonding electrode composed of a plurality of plating layers including a gold plating layer on a surface layer, to which a gold wire is connected,
An insulating paste in which a photosensitive material is dispersed is applied to the substrate, and the insulating paste is exposed and solidified using a photomask, and the insulating paste that has not been solidified is removed to provide an opening. An insulating film forming step of forming an insulating film having non-plating properties for the plurality of plating layers;
After the insulating film forming step, a bonding electrode forming step of forming the plurality of plating layers by plating the bottom surface of the opening a plurality of times to form the bonding electrode;
A method for manufacturing a chip element including: 表主面に電極パターンを設けた基体と、表層に金メッキ層を含む複数のメッキ層からなり、金ワイヤが接続されるボンディング用電極と、を備えるチップ素子の製造方法であって、
感光性材を分散させた絶縁性ペーストを前記基体に塗布し、フォトマスクを用いて前記絶縁性ペーストを感光させて固化し、固化していない前記絶縁性ペーストを除去して開口を設けて、前記複数のメッキ層に対して非メッキ性を有する絶縁膜を形成する絶縁膜形成工程と、
前記絶縁膜形成工程の後、感光性材を分散させた導電性ペーストを前記絶縁膜の表主面に塗布し、フォトマスクを用いて前記導電性ペーストを感光させて固化し、固化していない前記導電性ペーストを除去して、前記基体に設けた電極パターンに導通する下地電極を形成する下地電極形成工程と、
前記下地電極形成工程の後、前記下地電極上に、複数回のメッキを施して前記複数のメッキ層を形成して前記ボンディング用電極を形成するボンディング用電極形成工程と、
を含むチップ素子の製造方法。A manufacturing method of a chip element comprising: a base provided with an electrode pattern on a front main surface; and a bonding electrode composed of a plurality of plating layers including a gold plating layer on a surface layer, to which a gold wire is connected,
An insulating paste in which a photosensitive material is dispersed is applied to the substrate, and the insulating paste is exposed and solidified using a photomask, and the insulating paste that has not been solidified is removed to provide an opening. An insulating film forming step of forming an insulating film having non-plating properties for the plurality of plating layers;
After the insulating film forming step, a conductive paste in which a photosensitive material is dispersed is applied to the front main surface of the insulating film, and the conductive paste is exposed to light using a photomask to be solidified and not solidified. A base electrode forming step of removing the conductive paste and forming a base electrode conducting to an electrode pattern provided on the base;
After the base electrode forming step, on the base electrode, a plurality of times of plating is performed to form the plurality of plated layers to form the bonding electrode, and a bonding electrode forming step,
A method for manufacturing a chip element including:
JP2008556079A 2007-02-01 2008-01-28 Chip element and manufacturing method thereof Expired - Fee Related JP4935828B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008556079A JP4935828B2 (en) 2007-02-01 2008-01-28 Chip element and manufacturing method thereof

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2007023090 2007-02-01
JP2007023090 2007-02-01
JP2008556079A JP4935828B2 (en) 2007-02-01 2008-01-28 Chip element and manufacturing method thereof
PCT/JP2008/051166 WO2008093626A1 (en) 2007-02-01 2008-01-28 Chip element and process for producing the same

Publications (2)

Publication Number Publication Date
JPWO2008093626A1 true JPWO2008093626A1 (en) 2010-05-20
JP4935828B2 JP4935828B2 (en) 2012-05-23

Family

ID=39673938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008556079A Expired - Fee Related JP4935828B2 (en) 2007-02-01 2008-01-28 Chip element and manufacturing method thereof

Country Status (2)

Country Link
JP (1) JP4935828B2 (en)
WO (1) WO2008093626A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8889995B2 (en) 2011-03-03 2014-11-18 Skyworks Solutions, Inc. Wire bond pad system and method
US9679869B2 (en) 2011-09-02 2017-06-13 Skyworks Solutions, Inc. Transmission line for high performance radio frequency applications
KR20190058711A (en) 2012-06-14 2019-05-29 스카이워크스 솔루션즈, 인코포레이티드 Power amplifier modules with harmonic termination circuit and related systems, devices, and methods

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60195961A (en) * 1984-03-19 1985-10-04 Hitachi Ltd Semiconductor device
JPH06283566A (en) * 1993-03-25 1994-10-07 Fuji Electric Co Ltd Semiconductor device and its manufacture
JP2002016176A (en) * 2000-06-29 2002-01-18 Kyocera Corp Wiring board and connection structure therefor
JP2002151908A (en) * 2000-11-14 2002-05-24 Murata Mfg Co Ltd High frequency filter and filter system using it and electronic device employing them
JP2005322868A (en) * 2004-05-03 2005-11-17 Samsung Electro Mech Co Ltd Method for electrolytic gold plating of printed circuit board

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0108655D0 (en) * 2001-04-06 2001-05-30 Koninkl Philips Electronics Nv Microwave circuit
JP2003060428A (en) * 2001-08-21 2003-02-28 Hitachi Ltd High-frequency circuit device and production method therefor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60195961A (en) * 1984-03-19 1985-10-04 Hitachi Ltd Semiconductor device
JPH06283566A (en) * 1993-03-25 1994-10-07 Fuji Electric Co Ltd Semiconductor device and its manufacture
JP2002016176A (en) * 2000-06-29 2002-01-18 Kyocera Corp Wiring board and connection structure therefor
JP2002151908A (en) * 2000-11-14 2002-05-24 Murata Mfg Co Ltd High frequency filter and filter system using it and electronic device employing them
JP2005322868A (en) * 2004-05-03 2005-11-17 Samsung Electro Mech Co Ltd Method for electrolytic gold plating of printed circuit board

Also Published As

Publication number Publication date
JP4935828B2 (en) 2012-05-23
WO2008093626A1 (en) 2008-08-07

Similar Documents

Publication Publication Date Title
JP4028884B1 (en) Coil parts
JP6269591B2 (en) Coil parts
KR102025708B1 (en) Chip electronic component and board having the same mounted thereon
JP4404088B2 (en) Coil parts
JP7083600B2 (en) Glass circuit board with built-in capacitor and its manufacturing method
JP2007053254A (en) Electronic components and manufacturing method thereof
KR20220116328A (en) Thin film capacitor and electronic circuit board having same
CN109964544A (en) Electronic component and electronic component manufacturing method
JPS62216259A (en) Manufacture and structure of hybrid integrated circuit
CN107204295A (en) Electronic component package and the method for manufacturing the electronic component package
JP7444210B2 (en) Glass circuit board with built-in capacitor
JP7096992B2 (en) Through Silicon Via Board and Mounting Board
JP4935828B2 (en) Chip element and manufacturing method thereof
JP5707710B2 (en) Multilayer chip parts
JP2006222106A (en) Chip-type electronic component and manufacturing method thereof
CN108282157A (en) Acoustic resonator and the method for manufacturing acoustic resonator
WO2008133369A9 (en) The manufacturing method of the thin film ceramic multi layer substrate
JP2006319409A (en) Frequency adjustment device and semiconductor package including frequency adjustment device
JP2003298200A (en) Electronic component and its producing method
JP2001291615A (en) Three-terminal variable inductor
KR20190108541A (en) Chip electronic component and board having the same mounted thereon
JP4577479B2 (en) Sheet forming method having different material parts and sheet having different material parts used for multilayer wiring board formation
JP7498680B2 (en) Wiring Board
CN220067840U (en) Multilayer structure
JP2019102827A (en) Transmission circuit, wiring board, and high frequency device

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111115

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111220

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20111220

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120124

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120206

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150302

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4935828

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees