JP2006319409A - Frequency adjustment device and semiconductor package including frequency adjustment device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency adjustment device capable of being assembled with a semiconductor package in a space-saving way and to provide the semiconductor package assembled with the frequency adjustment device. <P>SOLUTION: The frequency adjustment device 10 located on a high frequency signal input transmission line 104 of the semiconductor package 100 including: a resistor 14 for connecting a first conductor 15 and a second conductor 16 formed on a substrate 17 and through which a high frequency signal is transmitted; a dielectric 11 located on an end 15 of the first conductor; and an electrode 12 arranged on the dielectric 11 and connected to the second conductor, is configured to form a filter circuit by using the resistor 14 and the dielectric 11. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a frequency adjustment device for improving transmission characteristics of a high-frequency signal, and more specifically, a frequency adjustment device formed on a signal wiring provided on a circuit board, and a semiconductor package having the frequency adjustment device It is about.

  In recent years, integrated circuit technology has been developed more and more, and there is a remarkable improvement in processing speed. Under such circumstances, high-frequency devices and optical devices in which the frequency of an input signal extends to several GHz to several tens GHz are used. In such a device, in order to prevent malfunction and achieve high-speed processing, it is necessary to give a good high frequency characteristic to the input signal. For this reason, a frequency adjustment circuit that functions as a high-pass filter is incorporated in these devices to improve signal transmission characteristics for high-frequency signals.

  However, when such a frequency adjusting circuit is incorporated into a device, there is a problem that the device becomes larger accordingly.

  On the other hand, a technology for forming a circuit element such as a resistor or a capacitor on a circuit board by forming a thin film has been developed with the progress of miniaturization technology of an integrated circuit (see Patent Documents 1 and 2). By using such a technique, the mounting density of a frequency adjusting circuit or the like is improved in the above-described high-frequency device or the like. However, due to the necessity of mounting devices in a limited space, such as mobile phones, the demand for miniaturization of high-frequency devices is very strong, and the development of technology to achieve further miniaturization It has been demanded.

JP-A-10-173307 JP 2002-33559 A

  In view of the above problems, an object of the present invention is to provide a frequency adjustment device that can be incorporated in a space-saving manner, and a semiconductor package incorporating the frequency adjustment device.

  Another object of the present invention is to provide a frequency adjusting device that constitutes a good high-pass filter by suppressing a decrease in characteristic impedance and an increase in parasitic inductance, and a semiconductor package incorporating the frequency adjusting device. To do.

  In order to achieve the above object, a frequency adjusting device according to the present invention includes a resistor formed on a substrate, connecting a first conductor for transmitting a high-frequency signal and a second conductor, and a first conductor. A dielectric disposed on the end of the substrate, and an electrode disposed on the dielectric and connected to the second conductor, wherein the resistor and the dielectric form a filter circuit. To do. The dielectric is preferably arranged so that the distance from the dielectric to the resistor is equal to or less than the distance equal to the line width of the first conductor.

  Moreover, it is preferable that the width | variety of a dielectric material is below the width | variety of a 1st conductor. This is because direct contact between the dielectric and the substrate can be prevented and transmission loss of high-frequency signal energy can be suppressed.

  Here, it is preferable that the electrode is composed of a plurality of small electrodes, each small electrode is connected by a connection conductor, and an area in which the electrode contacts the dielectric is adjusted. This is because the signal transmission characteristics of the frequency adjusting device can be easily changed according to the application.

  The plurality of small electrodes preferably include small electrodes having different contact areas with the dielectric. This is because the signal transmission characteristics of the frequency adjusting device can be changed more flexibly.

  In addition, said electrode is connected with a 2nd conductor and a connection conductor, or the electrode itself extends to the upper part of a 2nd conductor, and is connected to a 2nd conductor.

  A semiconductor package according to the present invention is characterized in that the above-described frequency adjusting device is incorporated in a high-frequency signal input transmission line of a semiconductor chip.

  By incorporating the frequency adjustment device into the package itself, which is essential for mounting the semiconductor chip on the circuit board, it is possible to improve the frequency characteristics of the input signal to the semiconductor chip while contributing to the miniaturization of the device itself. is there.

  According to the present invention, it is possible to obtain a frequency adjustment device that can be easily incorporated into a semiconductor package.

  Further, according to the present invention, it is possible to obtain a frequency adjustment device that can be incorporated in a space-saving manner, and a semiconductor package in which the frequency adjustment device is incorporated.

  Further, according to the present invention, it is possible to obtain a frequency adjusting device that constitutes a good high-pass filter and a semiconductor package incorporating the frequency adjusting device by suppressing a decrease in characteristic impedance and an increase in parasitic inductance.

  Hereinafter, the present invention will be described in detail with reference to the drawings.

  The frequency adjusting device according to the present invention plays a role as a high-pass filter for improving high-frequency characteristics and providing a good high-frequency input signal to an integrated circuit with respect to a high-frequency signal having a signal frequency of several GHz to several tens of GHz. Is.

  First, it will be described how the frequency adjustment device according to the present invention is implemented, and then the details of the frequency adjustment device will be described using some embodiments.

  FIG. 1 shows a schematic cross-sectional perspective view of a first specific example of a semiconductor package incorporating a frequency adjusting device according to the present invention.

  As shown in FIG. 1, a semiconductor package 100 as a first specific example surrounds the periphery of a semiconductor chip 101 disposed at the upper center of a metal base 102 with an insulating substrate 103 formed on the metal base 102. It has a configuration. Further, a high-frequency signal input transmission path 104 and a signal output transmission path 105, which are conductors, are formed on the insulating substrate 103, and are electrically connected to the semiconductor chip 101 by wires 106, respectively. An external input electric signal is input to the semiconductor chip 101 through the high-frequency signal input transmission path 104, and an output signal from the semiconductor chip 101 is output to the outside through the signal output transmission path 105. Yes.

  The frequency adjusting device 10 according to the present invention is provided in the middle of the high-frequency signal input transmission path 104.

  FIG. 2 is a schematic sectional perspective view of a second specific example of the semiconductor package incorporating the frequency adjusting device according to the present invention.

  The semiconductor package 200 as the second specific example is suitable for a semiconductor chip or the like that requires a large space for mounting.

  As shown in FIG. 2, the semiconductor package 200 has a semiconductor chip 201 disposed in the center of a cavity provided in a metal case 202, and has a relay substrate 203 on both sides thereof. A high-frequency signal input transmission path 204 and a signal output transmission path 205, which are conductors, are formed on the relay substrate 203, and are electrically connected to the semiconductor chip 201 by wires 206, respectively. Holes are provided at both ends of the metal case 202 so that the inside and the outside of the case 202 can communicate with each other, and a pair of lead wires 207 are disposed so as to pass through the holes. Further, the periphery of the lead wire 207 is hardened with a sealing glass 208 so as to close the hole. The pair of lead wires 207 are electrically connected to the high-frequency signal input transmission line 204 and the signal output transmission line 205, respectively (brazed and connected). An external electrical input signal is input to the semiconductor chip 201 through the high-frequency signal input transmission path 204, and an output signal from the semiconductor chip 201 is output to the outside through the signal output transmission path 205. Yes.

  Further, the frequency adjustment device 10 according to the present invention is provided in the middle of the high-frequency signal input transmission line 204, as in the semiconductor package 100.

  Thus, by incorporating the frequency adjusting device into the semiconductor package itself, it is not necessary to separately provide a region for the frequency adjusting device on the circuit board, which can contribute to miniaturization of the high frequency device or the optical device itself.

  Next, details of the frequency adjustment device according to the present invention will be described using several embodiments.

  FIG. 3 (a) shows a schematic top view of the frequency adjustment device 10 which is the first embodiment of the frequency adjustment device according to the present invention, and FIG. 3 (b) shows AA ′ in FIG. 3 (a). Figure 2 shows a schematic side cross-sectional view at the indicated line. FIG. 3C shows an equivalent circuit of the frequency adjustment device 10.

The frequency adjusting device 10 is an RC parallel circuit provided on a wiring formed on an insulating substrate 17 made of alumina ceramic (Al ₂ O ₃ ). In the frequency adjusting device 10, a layer made of tantalum nitride (Ta ₂ N) is formed on the insulating substrate 17, and the first conductor 15 and the second conductor 16 made of a gold thin film have a slight gap therebetween. Provided and arranged. The conductors 15 and 16 are part of the conductors constituting the high-frequency signal input transmission lines 104 and 204 of the semiconductor package. In the gap between the conductors 15 and 16, the tantalum nitride (Ta ₂ N) layer described above is electrically connected as the resistor 14, and an input signal can be transmitted between the conductors 15 and 16. . The resistor 14 corresponds to a resistor in the RC parallel circuit.

In the frequency adjusting device 10, a dielectric made of silicon oxide (SiO ₂ ) is formed on the first conductor 15 in the vicinity of the end of the first conductor 15 near the second conductor 16. 11 and an electrode 12 made of a gold thin film are sequentially stacked, and a capacitor is formed by the first conductor 15 and the electrode 12 and the dielectric 11 sandwiched between them. Here, the dielectric 11 and the electrode 12 have a width equal to or smaller than the width of the first conductor 15 and are stacked without protruding from the first conductor 15. By laminating in this way, it is possible to prevent transmission of electrical signals transmitted to the insulating substrate 17 and the like and transmission loss. Furthermore, the electrode 12 and the second conductor 16 are electrically connected by a connection conductor 13 which is a wire made of gold. By setting it as such a structure, the frequency adjustment device 10 which is RC parallel circuit can be provided in wiring.

When the frequency adjusting device 10 is manufactured by a manufacturing process to be described later, titanium, palladium or the like is used to facilitate formation of the conductors 15 and 16 by a gold plating method between the resistor 14 and the conductors 15 and 16. These layers, such as titanium, are omitted in FIG. 3 for simplicity of explanation. Similarly, titanium and palladium layers are also provided between the dielectric 11 and the electrode 12, but these layers are also omitted in FIG. 3 for the sake of simplicity.
Further, a conductive layer 18 of a gold thin film may be provided below the insulating substrate 17 for grounding.

  Further, the frequency adjustment device 10 may use either the first conductor or the second conductor as a signal input side.

For the dielectric 11, in addition to silicon oxide (SiO ₂ ), a metal oxide such as Ta ₂ O ₅ or an organic material such as polyimide can be used. In addition to the gold thin film, the electrode 12 and the conductors 15 and 16 may be made of tungsten metallized or the like plated with metal such as gold or copper. Further, the resistor 14 can be made of TaSiO ₂ , nichrome, or the like in addition to tantalum nitride (Ta ₂ N).

  Next, the manufacturing process of the frequency adjustment device 10 according to the first embodiment will be described.

  FIG. 4 shows a flowchart of the manufacturing process of the frequency adjustment device 10 according to the first embodiment. Moreover, the schematic top view of the frequency adjustment device 10 in each process in a manufacturing process is shown in FIGS. Further, FIGS. 8 to 10 are schematic side cross-sectional views of the frequency adjusting device 10 in each process of the manufacturing process 10 along the line DD ′ in FIG. 5 to 10, the same reference numerals are used for the numbers indicating the same parts.

First, as shown in FIG. 5A and FIG. 8A, a tantalum nitride (Ta ₂ N) layer 1 is formed on an insulating substrate 17 having a conductor layer 18 for grounding on the lower surface. Then, a layer 2 of titanium (Ti) and palladium (Pd) is formed (step S01). The tantalum nitride layer 1 is for forming the resistor 14, and the titanium and palladium layer 2 is for allowing gold plating.

First, a tantalum nitride (Ta ₂ N) layer 1 to be the resistor 14 is deposited on the entire surface of the insulating substrate 17 by sputtering. Then, titanium (Ti) and palladium (Pd) are vapor-deposited in this order so that the gold plating can be applied to the vapor-deposited tantalum nitride layer 1. By this vapor deposition, tantalum nitride, titanium, and palladium are sequentially laminated on the entire top surface of the insulating substrate 17.

  Next, resist patterning for forming the conductors 15 and 16 is performed (step S02). As shown in FIGS. 5B and 8B, the resist layer 3 is made of titanium so that only the regions where the conductors 15 and 16 are planned to be exposed are exposed by this resist patterning. , Formed on the palladium layer 2.

  Thereafter, as shown in FIGS. 5C and 8C, a gold thin film layer having a width of about 0.1 mm to 1 mm and a thickness of about 1 μm to 10 μm is formed on the surface of the palladium layer by plating. The gold thin film layer becomes the conductors 15 and 16 (step S03). Note that the gold plating method used here is an example, and another method may be used.

  When the conductors 15 and 16 are formed, etching is performed, and the palladium and titanium layer 2 is removed as shown in FIGS. 5D and 8D (step S04). The photoresist is first removed before etching. Then, etching is performed using an etching solution that dissolves titanium and palladium and does not dissolve gold, such as a mixed solution based on hydrofluoric acid, so that the insulating substrate 17 other than directly below the conductors 15 and 16 is formed. The palladium / titanium layer 2 exposed to the surface is removed.

  Thereafter, resist patterning is performed again in order to remove unnecessary tantalum nitride deposited outside the region sandwiched between the conductors 15 and 16 made of the gold thin film layer (step S05). In this resist patterning, as shown in FIGS. 5E and 8E, the photoresist layer 4 is formed so as to cover only the gap between the conductors 15 and 16.

  After the formation of the photoresist layer, as shown in FIGS. 6A and 9A, the unnecessary tantalum nitride layer 1 not covered with the photoresist layer 4 is removed by etching (step S06). . Thus, the resistor 14 is formed. When the tantalum nitride layer 1 is removed, the photoresist layer 4 is also removed.

  Next, resist patterning is performed three times in order to form a layer of the dielectric 11 on the conductor 15 made of a gold thin film (step S07).

  In this step, as shown in FIGS. 6B and 9B, in order to deposit the dielectric 11, the photoresist layer 5 is exposed so as to expose only a predetermined region where the dielectric 11 is deposited. The entire insulating substrate 17 is covered.

Thereafter, as shown in FIGS. 6C and 9C, after the photoresist layer 5 is formed, silicon oxide (SiO ₂ ) is vapor-deposited by a sputtering method, and a dielectric is formed on the uppermost surface of the insulating substrate 17. The body layer 6 is formed (step S08).

  When the dielectric layer 6 is formed, the photoresist layer 5 and the silicon oxide deposited on the photoresist layer 5 are removed by lift-off (step S09). Thus, as shown in FIGS. 6D and 9D, a layer of the dielectric 11 is formed in a predetermined region on the conductor 15.

  When the lift-off is completed, as shown in FIGS. 6 (e) and 9 (e), titanium (Ti) and palladium (Pd) are again deposited on the entire top surface of the insulating substrate 17 in this order by sputtering. The layer 7 is formed (step S10). By performing this vapor deposition, the upper surface of the dielectric 11 can be plated with gold.

  When the deposition of titanium and palladium is finished, as shown in FIGS. 7A and 10A, resist patterning is performed to form the insulating substrate 17 with a photoresist layer so that only a predetermined region on the upper surface of the dielectric 11 is exposed. 8 (step S11).

  When the resist patterning in step S11 is completed, gold plating is performed to form a gold thin film layer having a thickness of about 1 μm to 10 μm in a predetermined region on the surface of the dielectric 11 (step S12). Thus, as shown in FIGS. 7B and 10B, the electrode 12 is formed on the dielectric 11.

  When the electrode 12 is formed, as shown in FIGS. 7C and 10C, the photoresist is removed, and unnecessary titanium and palladium are removed by etching (step S13).

  Finally, as shown in FIGS. 7D and 10D, the gold wire 13 is bonded to the electrode 12 and the wiring 15 (step S14).

  The frequency adjusting device 10 can be formed on the signal transmission path by the manufacturing process described above. However, the manufacturing process mentioned above is an example, and is not limited to this.

  Next, a frequency adjustment device 20 according to a second embodiment of the present invention will be described with reference to FIG.

  11A is a schematic top view of the frequency adjustment device 20, FIG. 11B is a schematic side cross-sectional view taken along the line BB ′ in FIG. 11A, and FIG. It is a figure which shows the equivalent circuit. In FIG. 11, the same components as those of the frequency adjustment device 10 shown in FIG. 3 are denoted by the same numbers as those used in FIG.

  The frequency adjustment device 20 includes a plurality of small electrodes 22 each having a different area instead of the electrode 12 of the frequency adjustment device 10 described above. Therefore, the frequency adjusting device 20 is provided with as many connection conductors 23 as necessary for connecting the small electrodes 22 according to the application, and changes the total area of the small electrodes 22 electrically connected by the connection conductors 23. The capacitor capacity can be changed with. A gold wire can be used for the connection conductor 23.

  Further, the frequency adjusting device 20 can be formed by the same manufacturing process as the above-described manufacturing process of the frequency adjusting device 10, and in order to form an electrode, the frequency adjusting device 20 is divided into a plurality of parts in step S11 in which resist patterning is performed. The resist pattern is changed so that a thin film is formed, and wire bonding is performed. In step S14, the number of wires connecting the small electrodes 22 and the small electrodes to be connected are changed, thereby having various signal transmission characteristics. A frequency tuning device can be formed.

  Furthermore, a frequency adjustment device 30 according to a third embodiment of the present invention will be described with reference to FIG.

  12A is a schematic top view of the frequency adjustment device 30, and FIG. 12B is a schematic side cross-sectional view taken along the line CC 'in FIG. 12A. In FIG. 12, the same components as those of the frequency adjustment device 10 shown in FIG. 3 are denoted by the same numbers as those used in FIG.

  The frequency adjusting device 30 constitutes an RC parallel circuit without using wire bonding. In order to eliminate wire bonding, in the frequency adjusting device 30, the electrode 32 provided on the upper portion of the dielectric 31 is formed so as to be directly electrically connected to the conductor 16. By adopting a configuration in which the wire portion is eliminated in this way, it is possible to suppress the generation of inductance and form a frequency adjustment device having good signal transmission characteristics.

  Further, the manufacturing process of the frequency adjusting device 30 is obtained by omitting the step S14 for performing wire bonding from the manufacturing process of the frequency adjusting device 10, and the step S07 for performing resist patterning to form a dielectric and the electrode are formed. Therefore, in step S <b> 11 in which resist patterning is performed, the resist pattern may be changed so that the dielectric 31 and the electrode 32 are thinly formed on the conductor 16.

  Thus, the frequency adjustment device 30 can be formed by a simpler manufacturing process than the frequency adjustment devices 10 and 20.

  Furthermore, a frequency adjustment device 40 according to a fourth embodiment of the present invention will be described with reference to FIG.

  13A is a schematic top view of the frequency adjustment device 40, and FIG. 13B is a schematic side cross-sectional view taken along the line EE 'in FIG. 13A.

  In the frequency adjusting device 40, the conductors 45 and 46 are made of a thick film using tungsten metallized or the like plated with metal instead of using a gold thin film unlike the frequency adjusting device 10. In this embodiment, the resistor 44 is disposed only in the gap between the conductors 45 and 46. Other configurations are the same as those of the frequency adjustment device 10 according to the first embodiment.

  Next, the result of actually creating the frequency adjusting device 10 according to the first embodiment of the present invention and examining the signal transmission characteristics will be described.

An example of the created frequency adjustment device 10 is a CR parallel circuit having a capacitor capacity of 5 pF and a resistance of 10Ω. In the frequency adjusting device 10, conductors 15 and 16 made of a gold thin film having a width of 0.4 mm are formed on an alumina ceramic substrate 17 having a thickness of 0.4 mm. There is a gap of 0.08 mm in length between the conductors 15 and 16, and they are electrically connected by a resistor 14 made of tantalum nitride (Ta ₂ N) having the same resistor length as this gap. The dielectric 11 has a size of 0.3 mm in the length direction of the wiring and 0.3 mm in the width direction, and is formed on the output side wiring so as not to contact the insulating substrate 17. Further, the electrode 12 is 0.2 mm in the length direction of the wiring 15 and 0.2 mm in the width direction (the area of the region facing the dielectric is 0.04 mm ² ), which is slightly smaller than the dielectric 11. It is formed on the dielectric 11 so as not to protrude. The connection conductor 13 which is a gold wire electrically connects the electrode 12 and the input side wiring.

  Further, the length of the gap between the conductors 15 and 16, that is, the resistor 14 is changed to 0.04 mm, 0.12 mm, and 0.16 mm to change the resistance to 5Ω, 15Ω, and 20Ω (however, the capacitor capacity is 5 pF). A constant frequency adjustment device.

  Therefore, FIG. 14 shows a graph of signal transmission characteristics of the created frequency adjustment device 10.

  The horizontal axis of the graph represents the frequency of the input signal, and the unit is GHz. The vertical axis of the graph represents transmission loss due to the frequency adjustment device 10, and its unit is dB. A graph 61 represents the signal transmission characteristics of the frequency adjusting device 10 (resistor length: 0.08 mm, resistance: 10Ω). Similarly, in the graphs 62 to 64, when the resistor length of the resistor 14 is 0.04 mm, 0.12 mm, and 0.16 mm and the resistance is 5Ω, 15Ω, and 20Ω, respectively, the capacitor capacity is constant at 5 pF. The signal transmission characteristic of each frequency adjustment device is represented.

  As shown in FIG. 14, when the input signal is 6 GHz or more, the transmission loss is less than −0.2 dB for each frequency adjusting device. On the other hand, when the input signal is less than 6 GHz, the transmission loss gradually increases. It can be seen that the transmission loss is about −0.4 dB to −0.7 dB at 2 GHz, and the transmission loss is about −0.4 dB to −1.2 dB at a frequency of 1 GHz.

  Similarly, the thickness of the dielectric 11 of the frequency adjusting device 10 is changed so that the capacitance of the capacitor is 2 pF, and the lengths of the resistors are 0.04 mm, 0.08 mm, 0.12 mm, and 0.16 mm, respectively. FIG. 15 shows signal transmission characteristics of the frequency adjusting device in this case.

  In FIG. 15, the horizontal and vertical axes of the graph are the same as those in FIG. Graphs 71 to 74 show the signal transmission characteristics of the frequency adjusting device when the resistance is 5Ω, 10Ω, 15Ω, and 20Ω, respectively.

  As shown in FIG. 15, it can be seen that each frequency adjustment device is a high-pass filter in which transmission loss increases from the high frequency side as compared with the frequency adjustment device shown in FIG. 14, and specifically, the transmission loss increases. It can be seen that when the frequency of the input signal falls below 12 GHz, the transmission loss increases gradually.

  As described above, the frequency adjusting device according to the present invention is formed on the high-frequency signal input transmission path of the semiconductor package, and can contribute to space saving of the device. Further, it is possible to configure a high pass filter having good transmission characteristics for an input signal having a frequency of several GHz to 10 GHz or more.

  Furthermore, frequency adjustment devices with various specifications can be easily configured by simply changing the resistor length and the dielectric thickness.

  The above-described embodiments are for explaining the present invention, and the present invention is not limited to the above-described embodiments. For example, when there are a plurality of high-frequency signal input transmission paths for transmitting an input signal to the semiconductor chip, the frequency adjusting device according to the present invention can be formed in each high-frequency signal input transmission path.

It is a schematic perspective view of the 1st semiconductor package containing the frequency adjustment device which concerns on this invention. It is a schematic cross-sectional perspective view of the 2nd semiconductor package containing the frequency adjustment device which concerns on this invention. (A) is a schematic top view of the frequency adjustment device which concerns on the 1st Embodiment of this invention, (b) is a schematic side sectional view of the frequency adjustment device which concerns on the 1st Embodiment of this invention. (C) is a block diagram of an equivalent circuit of the frequency adjustment device according to the first embodiment of the present invention. It is a flowchart which shows the manufacturing process of the frequency adjustment device which concerns on the 1st Embodiment of this invention. It is a schematic top view explaining each manufacturing process of the frequency adjustment device which concerns on the 1st Embodiment of this invention. It is a schematic top view explaining each manufacturing process of the frequency adjustment device which concerns on the 1st Embodiment of this invention. It is a schematic top view explaining each manufacturing process of the frequency adjustment device which concerns on the 1st Embodiment of this invention. It is a schematic sectional side view explaining each manufacturing process of the frequency adjustment device which concerns on the 1st Embodiment of this invention. It is a schematic sectional side view explaining each manufacturing process of the frequency adjustment device which concerns on the 1st Embodiment of this invention. It is a schematic sectional side view explaining each manufacturing process of the frequency adjustment device which concerns on the 1st Embodiment of this invention. (A) is a schematic top view of the frequency adjustment device which concerns on the 2nd Embodiment of this invention, (b) is a schematic side sectional view of the frequency adjustment device which concerns on the 2nd Embodiment of this invention. (C) is a block diagram of the equivalent circuit of the frequency adjustment device which concerns on the 2nd Embodiment of this invention. (A) is a schematic top view of the frequency adjustment device which concerns on the 3rd Embodiment of this invention, (b) is a schematic side sectional view of the frequency adjustment device which concerns on the 3rd Embodiment of this invention. (A) is a schematic top view of the frequency adjustment device which concerns on the 4th Embodiment of this invention, (b) is a schematic sectional side view of the frequency adjustment device which concerns on the 4th Embodiment of this invention. It is the figure which showed the signal transmission characteristic of the frequency adjustment device which concerns on the 1st Embodiment of this invention. It is the figure which showed the signal transmission characteristic of the frequency adjustment device which concerns on the 1st Embodiment of this invention.

Explanation of symbols

10, 20, 30, 40 Frequency adjusting device 11, 31 Dielectric 12, 32 Electrode 22 Small electrode 13, 23 Connecting conductor 14, 44 Resistor 15, 16, 45, 46 Conductor 17, 103 Insulating substrate 104, 204 High-frequency signal input transmission path 105, 205 Signal output transmission path 100, 200 Semiconductor package 101, 201 Semiconductor chip 203 Relay substrate

Claims (7)

A resistor formed on the substrate and connecting the first conductor and the second conductor for transmitting a high-frequency signal;
A dielectric disposed on an end of the first conductor;
An electrode disposed on the dielectric and connected to the second conductor;
A filter circuit is formed by the resistor and the dielectric, and the frequency adjusting device.   The frequency adjusting device according to claim 1, wherein a width of the dielectric is equal to or less than a width of the first conductor. The electrode is composed of a plurality of small electrodes,
The frequency adjusting device according to claim 1, wherein each of the small electrodes is connected by a connecting conductor, and an area in which the electrode contacts the dielectric is adjusted.   The frequency adjustment device according to claim 3, wherein the plurality of small electrodes include small electrodes having different contact areas with the dielectric.   The frequency adjustment device according to claim 1, wherein the electrode is connected to the second conductor by a connection conductor.   The frequency adjusting device according to claim 1, wherein the electrode extends to an upper portion of the second conductor and is connected to the second conductor.   A semiconductor package comprising the frequency adjusting device according to claim 1 incorporated in a high frequency signal input transmission line of a semiconductor chip.

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