JP7472457B2 - Wiring board and semiconductor device - Google Patents

Description

This disclosure relates to a wiring board.

In wiring boards with wiring arranged on a substrate, various problems may occur depending on the relationship between the insulating material and the metal material that forms the wiring arranged on this insulating material. For example, the adhesion and thermal stress difference between the insulating material and the metal material may cause the wiring to peel off from the insulating material or cracks to form in the insulating material. If peeling or cracks occur during manufacturing, it will result in a manufacturing defect and a decrease in yield, and if they occur after the product is completed, it will lead to a decrease in reliability. For example, Patent Documents 1 and 2 disclose techniques for arranging an adhesion layer or a stress buffer layer to suppress such a decrease in yield or reliability.

JP 2017-5081 A JP 2018-107423 A

By arranging the adhesion layer or stress buffer layer as described above, various manufacturing defects can be eliminated. On the other hand, when trying to improve peeling and cracking using only such a layer, the presence of this layer may affect the electrical characteristics. In such cases, the design of the wiring board may become more complex in order to reduce the impact. When the wiring is viewed in plan from the board surface, stress is concentrated at the boundary between the wiring and the adhesion layer or stress buffer layer. In this way, peeling and cracking are likely to occur in areas where stress is concentrated. Therefore, even if the adhesion layer and stress buffer layer do not affect the electrical characteristics, it is more preferable to devise and adopt a wiring structure that is less likely to peel and crack in order to suppress product defects.

One of the objectives of this disclosure is to suppress manufacturing defects that occur in wiring boards using a method different from conventional methods.

According to the present disclosure, a wiring board is provided that includes a substrate having an inorganic insulating material on its surface, a first conductive layer disposed on the inorganic insulating material and having a first region and a second region surrounding the first region, a second conductive layer disposed on the first region of the first conductive layer and thicker than the first conductive layer, and an organic insulating layer disposed on the second region of the first conductive layer and on the inorganic insulating material.

The device may further include a third conductive layer connected onto the second conductive layer, the third conductive layer including a contact portion with the second conductive layer and an extension portion extending outward from the contact portion, and the distance from the outer edge of the first region to the outer edge of the second region may be equal to or less than the distance from the outer edge of the contact portion to the outer edge of the extension portion.

The thickness of the first conductive layer may be less than the distance from the outer edge of the first region to the outer edge of the second region.

The substrate may have a through hole formed therein that penetrates the first surface and the second surface, the first conductive layer may be disposed on the inner surface of the through hole, on the first surface, and on the second surface, and the second region may be present on the first surface and the second surface.

The substrate may have a through hole formed between the first surface and the second surface, the first conductive layer disposed on the inner surface of the through hole, and the second region may be present on the inner surface of the through hole.

The first conductive layer and the second conductive layer may have different physical properties.

The first conductive layer and the second conductive layer may be made of different materials.

The present disclosure also provides a semiconductor device including the above-mentioned wiring board and a semiconductor chip electrically connected to the wiring board.

According to the present disclosure, manufacturing defects occurring in wiring boards can be suppressed using a method different from conventional methods.

1 is a schematic plan view showing a wiring board according to a first embodiment of the present disclosure. 1 is a schematic cross-sectional view (cross-sectional view taken along line A1-A2 in FIG. 1 ) illustrating a wiring board according to a first embodiment of the present disclosure. FIG. 3 is an enlarged view of the wiring according to the first embodiment of the present disclosure (an enlarged view of the vicinity of an area AX in FIG. 2 ). FIG. 2 is a diagram showing the relationship between a first conductive layer and a second conductive layer according to the first embodiment of the present disclosure. 3A to 3C are diagrams illustrating a method for manufacturing a wiring board according to the first embodiment of the present disclosure. 3A to 3C are diagrams illustrating a method for manufacturing a wiring board according to the first embodiment of the present disclosure. 3A to 3C are diagrams illustrating a method for manufacturing a wiring board according to the first embodiment of the present disclosure. 3A to 3C are diagrams illustrating a method for manufacturing a wiring board according to the first embodiment of the present disclosure. 3A to 3C are diagrams illustrating a method for manufacturing a wiring board according to the first embodiment of the present disclosure. 5A to 5C are diagrams illustrating a method for manufacturing a wiring according to a second embodiment of the present disclosure. 5A to 5C are diagrams illustrating a method for manufacturing a wiring according to a second embodiment of the present disclosure. FIG. 11 is a schematic cross-sectional view showing details of a wiring structure according to a third embodiment of the present disclosure. 13A to 13C are diagrams illustrating a method for manufacturing a wiring board according to a third embodiment of the present disclosure. 13A to 13C are diagrams illustrating a method for manufacturing a wiring board according to a third embodiment of the present disclosure. 13A to 13C are diagrams illustrating a method for manufacturing a wiring board according to a third embodiment of the present disclosure. FIG. 11 is a schematic cross-sectional view showing details of a wiring structure according to a fourth embodiment of the present disclosure. 13A to 13C are diagrams illustrating a method for manufacturing a wiring board according to a fourth embodiment of the present disclosure. 13A to 13C are diagrams illustrating a method for manufacturing a wiring board according to a fourth embodiment of the present disclosure. 13A to 13C are diagrams illustrating a method for manufacturing a wiring board according to a fourth embodiment of the present disclosure. 13A to 13C are diagrams illustrating a method for manufacturing a wiring board according to a fifth embodiment of the present disclosure. 13A to 13C are diagrams illustrating a method for manufacturing a wiring board according to a fifth embodiment of the present disclosure. 13A to 13C are diagrams illustrating a method for manufacturing a wiring board according to a fifth embodiment of the present disclosure. 13A to 13C are diagrams illustrating a method for manufacturing a wiring board according to a fifth embodiment of the present disclosure. 13A to 13C are diagrams illustrating a method for manufacturing a wiring according to a sixth embodiment of the present disclosure. 13A to 13C are diagrams illustrating a method for manufacturing a wiring according to a sixth embodiment of the present disclosure. FIG. 13 is a diagram showing a simulation result of the operating frequency dependency of the reflection characteristic (S11). FIG. 13 is a diagram showing a simulation result of the operating frequency dependency of the pass characteristic (S21).

An embodiment of the present disclosure will be described below with reference to the drawings. Note that each embodiment shown below is an example, and the present disclosure is not to be interpreted as being limited to these embodiments. In the drawings referred to in this embodiment, identical parts or parts having similar functions are given the same or similar symbols (symbols consisting of only A, B, etc. added after a number), and repeated explanations may be omitted. In addition, the dimensional ratios of the drawings may differ from the actual ratios for the convenience of explanation, and some components may be omitted from the drawings. In the drawings attached to this specification, for the convenience of illustration and ease of understanding, the scale and aspect ratios may be appropriately changed and exaggerated from those of the actual objects, and some components may be omitted from the drawings.

First Embodiment
[1. Overall structure
A wiring board according to an embodiment of the present disclosure includes a through hole and a wiring. The wiring is formed of a metal material and disposed on an inorganic insulating material. A wiring board having such wiring will be specifically described below. In this example, the wiring board is an interposer having a through hole. The wiring board may be a board that does not have a through hole.

Figure 1 is a schematic plan view showing a wiring board 10 according to a first embodiment of the present disclosure. Figure 2 is a schematic cross-sectional view (cross-sectional view along line A-A in Figure 1) showing the wiring board 10 in the first embodiment of the present disclosure. Note that in Figure 1, some components have been omitted to make it easier to understand the positional relationship between the substrate 11, the first conductive layer 12, and the second conductive layer 14.

The wiring board 10 includes a substrate 11, a first conductive layer 12, and a second conductive layer 14. The substrate 11 has a first surface 11a and a second surface 11b opposite to the first surface 11a. The substrate 11 is a substrate having an insulating surface, and in this example, is non-alkali glass. The thickness of the substrate 11 may be appropriately designed depending on the application of the wiring board 10. For example, making the substrate 11 thicker can prevent bending due to an external force, and making the substrate 11 thinner can allow it to bend in response to an external force. However, it is necessary to set the thickness of the substrate 11 to a level that allows the formation of a through hole 15 with a desired opening width. Specifically, making the substrate 11 thinner makes it easier to form a through hole 15 with a smaller opening width. Therefore, the thickness of the substrate 11 is preferably 30 μm or more and 1000 μm or less, and is 400 μm in this example.

The substrate 11 may be an inorganic insulating material other than glass, an organic material, or a semiconductor substrate. For example, when a silicon substrate is used as an interposer, the substrate surface may be covered with an inorganic insulating material such as a silicon oxide film or a silicon nitride film. This is because silicon is a material with excellent rigidity but is conductive. By forming an inorganic insulating material such as a silicon oxide film or a silicon nitride film on the side wall of the through hole, the diameter of the through hole can be reduced, making it possible to form a through electrode with a high aspect ratio. On the other hand, since glass, especially non-alkali glass and quartz, are insulating, there is no need to cover the surface with another material to obtain insulation unless there is a particular reason. Therefore, when considering electrical properties, they can be considered as a uniform substance, which makes it easier to simulate the properties and design the wiring structure. Materials such as alkali glass that are more insulating than silicon but less insulating than non-alkali glass may be covered with an inorganic insulating material as in the case of a silicon substrate, if necessary.

The wiring 100 has a structure in which multiple conductive layers (two conductive layers in this example) are stacked, and includes a first conductive layer 12 arranged on the surface of the substrate 11 and a second conductive layer 14 stacked on a part of the first conductive layer 12. There is a region in the vicinity of the edge of the first conductive layer 12 where the second conductive layer 14 is not arranged. In the plan view shown in FIG. 1, the edge of the first conductive layer 12 is arranged outside the edge of the second conductive layer 14. The region of the first conductive layer 12 where the second conductive layer 14 is arranged is called the first region As1, and the other region, i.e., the region where the second conductive layer 14 is not arranged, is called the second region As2 (see FIG. 3). According to this definition, it can be said that the first region As1 is surrounded by the second region As2.

The first conductive layer 12 may be disposed directly on the surface of the substrate 11 (first surface 11a or second surface 11b), or may be disposed on an inorganic insulating material other than the inorganic insulating material on the surface of the substrate 11 via at least one conductive or insulating layer.

The first conductive layer 12 corresponds to a part of the seed layer. The seed layer is a conductive layer that functions as an electrode when the second conductive layer 14 is formed by electrolytic plating. In this example, the first conductive layer 12 is a copper (Cu) film, but it may be other films such as chromium (Cr), titanium (Ti), nickel (Ni), tantalum (Ta), molybdenum (Mo), etc., or may be formed of multiple films. The thickness of the first conductive layer 12 is preferably 0.05 μm or more and 2 μm or less, more preferably 0.05 μm or more and 1 μm or less, and is 0.2 μm in this example.

In this example, the first conductive layer 12 is formed by electroless plating, but may be formed by another method such as sputtering. When electroless plating is used, it is easy to form the first conductive layer 12 on the inner surface 15a of the through hole 15 even if the aspect ratio of the through hole 15 is large. On the other hand, the first conductive layer 12 formed by electroless plating tends to have a smaller adhesion force to the substrate 11 than when formed by sputtering. Even in such a case, by adopting the structure of the wiring 100 according to the present disclosure, the stress concentrated at the end of the second conductive layer 14 when the wiring is viewed in plan from the substrate surface can be dispersed by the first conductive layer 12, and the contact area of the first conductive layer 12 with the substrate 11 is increased, so that the wiring 100 can be prevented from peeling off from the substrate 11. In addition, if it is desired to further prevent peeling, an adhesion layer may be used in combination. Conversely, if it is desired to prevent cracks, a stress buffer layer may be used in combination.

The second conductive layer 14 is formed by electrolytic plating using the first conductive layer 12 as a seed layer. In this example, the second conductive layer 14 is a Cu film, but it may be a film of another conductive material, or may be formed of multiple films. The thickness of the second conductive layer 14 is preferably thin in order to prevent peeling and cracking, because the stress caused by thermal changes increases as the thickness increases. However, a thicker thickness is preferable in order to reduce wiring resistance. For this reason, the thickness of the second conductive layer 14 is designed to balance these factors, and in this example, it is preferably 0.5 μm to 40 μm, more preferably 5 μm to 30 μm, and 20 μm in this example. The first conductive layer 12 and the second conductive layer 14 may be formed of different materials or the same material. Even if the first conductive layer 12 and the second conductive layer 14 are formed of the same material, they may have different physical properties, such as different film qualities.

The substrate 11 has a through hole 15 that penetrates the first surface 11a and the second surface 11b. The first conductive layer 12 and the second conductive layer 14 are also arranged inside the through hole 15. The first conductive layer 12 and the second conductive layer 14 arranged inside the through hole 15 reach the first surface 11a side and the second surface 11b side of the substrate 11 to form a through electrode. In this example, the inside of the through hole 15 has a conductive layer arranged along the inner surface 15a of the through hole 15, and an insulating layer 22 is arranged on the central axis portion, but may be blocked by the conductive layer.

In order to suppress transmission loss, it is necessary to reduce the wiring resistance including the through electrode. Also, if the through hole 15 is made larger, the wiring pitch cannot be made smaller, making integration difficult. Therefore, the opening width of the through hole 15 needs to be at least twice the thickness of the second conductive layer 14, and considering the processing accuracy, it is preferable that it is 150 μm or less, and in this example, it is 80 μm. Here, the opening width of the through hole 15 defines the figure formed by the cross section of the through hole 15 along these faces between the first face 11a and the second face 11b, and refers to the maximum value that can be taken by the distance between any two points on the outer edge of the figure. Note that, when the figure formed by the outer edge is a circle, the above-mentioned width refers to the diameter of the circle. As will be described later, the through hole 15 does not have to be cylindrical, so the opening width may be different between the first face 11a and the second face 11b. The opening width of 150 μm or less described here refers to the narrower opening width of the opening width on the first surface 11a side of the through hole 15 and the opening width on the second surface 11b side.

For example, if the thickness of the second conductive layer 14 is 20 μm, in order to leave an opening in the through hole 15 between the first surface 11a and the second surface 11b even after the second conductive layer 14 is formed, the lower limit of the opening width needs to be twice the thickness of the second conductive layer 14, that is, 40 μm or more. By providing an opening in this way, it is possible to generate a flow of gas and liquid between the first surface 11a and the second surface 11b through the through hole 15.

On the other hand, it is also possible to block the through-hole 15 at the same time as forming the second conductive layer 14. In that case, the opening width must be twice the thickness of the second conductive layer 14, that is, less than 40 μm. In this case, in order to block the through-hole 15 and prevent a cavity from being formed inside the through-hole 15, it is preferable to make only one of the first surface 11a or the second surface 11b of the through-hole 15 smaller than 40 μm. By blocking the through-hole 15 in this way, it is possible to stack wiring by providing, for example, a via in the blocked portion, and it is also possible to prevent the flow of gas and liquid from occurring between the first surface 11a and the second surface 11b.

However, as mentioned above, for example, when the thickness of the substrate 11 is 1000 μm, the substrate 11 is sufficiently thick, so it is difficult to reduce the opening width of the through hole 15. In other words, the opening width needs to be adjusted appropriately according to the processing method and the thickness of the substrate 11. In this embodiment, since the substrate 11 having a thickness of 400 μm is used, the opening width of the through hole 15 is set to 40 μm or more in consideration of processing possibility. When the opening width of the through hole 15 is small, the method of forming the seed layer also needs to be considered. For example, when using a physical film formation method such as sputtering or vapor deposition, it may not be possible to form the seed layer to the back of the through hole 15 (the central part between the first surface 11a and the second surface 11b), but by using electroless plating, it becomes easier to form the seed layer to the back of the through hole 15. On the other hand, the adhesion to the substrate 11 is lower in electroless plating, and the adhesion is higher in physical film formation.

As shown in the figure, the through hole 15 has the same opening width between the first surface 11a and the second surface 11b, i.e., is cylindrical, but may have other shapes. For example, the opening width may vary between the first surface 11a and the second surface 11b, and may have a minimum value, a maximum value, or both a minimum value and a maximum value. Also, the opening width may gradually increase or decrease from the first surface 11a to the second surface 11b.

An insulating layer 22 is formed on the first surface 11a side and the second surface 11b side of the substrate 11. In this example, the insulating layer 22 is a layer containing a resin, which is an organic material. The organic resin is, for example, polyimide or acrylic. A via hole 23 is formed in the insulating layer 22. A third conductive layer 24 is disposed in each of the via holes 23. The third conductive layer 24 is electrically connected to the second conductive layer 14 disposed at the bottom of the via hole 23. Note that a multilayer wiring structure having even more layers may be realized by repeatedly stacking insulating layers and conductive layers.

The wiring board 10 is electrically connected to the semiconductor chip 90 through the third conductive layer 24. The wiring board 10 is also connected to the circuit board 80 through the solder balls 25 and the third conductive layer 24. The semiconductor chip 90 may also be connected to the third conductive layer 24 through the solder balls 25. According to this configuration, a semiconductor device is provided that includes the wiring board 10, the semiconductor chip 90 disposed on the first surface 11a side of the substrate 11 and electrically connected to the second conductive layer 14, and the circuit board 80 disposed on the second surface 11b side of the substrate 11 and electrically connected to the second conductive layer 14. According to the wiring board 10 of this embodiment, it is easy to mount the semiconductor chip 90 with a narrow terminal pitch on the large circuit board 80. The circuit board 80 may be, for example, a motherboard.

In this way, a wiring board such as wiring board 10 is electrically connected to other elements such as semiconductor chip 90 to realize a semiconductor device as a whole. The semiconductor chip 90 may include functions such as a memory, a processor, an acceleration sensor, a magnetic sensor, a filter, and an amplifier. The semiconductor device is mounted on various electronic devices such as mobile terminals, information processing devices, and home appliances.

2. Wiring structure
Next, the detailed structure of the wiring 100 will be described with reference to an enlarged view of the vicinity of an area AX in FIG.

3 is an enlarged view of the wiring according to the first embodiment of the present disclosure (enlarged view of the vicinity of region AX in FIG. 2). FIG. 4 is a diagram showing the relationship between the first conductive layer and the second conductive layer according to the first embodiment of the present disclosure. The thickness of the first conductive layer 12 is called thickness t1, and the thickness of the second conductive layer 14 is called thickness t2. As described above, the region of the first conductive layer 12 in which the second conductive layer 14 is arranged is called the first region As1, and the remaining region is called the second region As2. Note that when the side surface of the second conductive layer 14 is inclined and the width of the second conductive layer 14 increases or decreases as it moves away from the first conductive layer 12, the first region As1 is defined as the region of the first conductive layer 12 in contact with the second conductive layer 14.

The distance from the outer edge of the first region As1 to the outer edge of the second region As2 is called distance d1. The portion where the second conductive layer 14 and the third conductive layer 24 contact is called contact portion CA. The portion of the third conductive layer 24 that extends outward from contact portion CA is called extension portion EA. The distance from the outer edge of contact portion CA to the outer edge of extension portion EA is called distance d2.

As shown in FIG. 3, the second region As2 of the first conductive layer 12 is sandwiched between the substrate 11 and the insulating layer 22. The substrate 11 and the insulating layer 22 are in contact with each other in adjacent regions outside the second region As2. In general, in order to improve adhesion with the organic insulating material, it is good to increase the surface roughness of the underlayer on which the organic insulating material is formed. However, it is not preferable to increase the surface roughness of the first conductive layer 12 and the second conductive layer 14. This is because, when the signal transmitted through the wiring is a high-frequency signal, the signal is transmitted through the surface of the wiring, and transmission loss is likely to occur if the surface roughness increases. Therefore, in order to improve adhesion with the organic insulating material, it is easier to increase the roughness of the inorganic insulating material. In addition, inorganic insulating materials have little change in the surface and are easy to maintain the state, so it is also characterized by the ease of ensuring the stability of the chemical bond with the organic insulating material. On the other hand, since the metal that is the conductive layer has a natural oxide film formed on the surface, there is a concern that the surface state may change even during the process, so consideration must be given to the process. In other words, it is preferable to keep the surface clean, control the oxide film, or provide an adhesive layer with an organic insulating material to cover the surface. Also, the end of a certain wiring 100 is composed of the first conductive layer 12 without the second conductive layer 14. By adopting such a structure for the wiring 100, the stress of the second conductive layer 14 is dispersed in the second region As2 of the first conductive layer 12, and the second region As2 is covered by the insulating layer 22 and fixed to the substrate 11 from the outside of the second region As2. With such a configuration, it is possible to suppress peeling between the substrate 11 and the wiring 100, and also to suppress the occurrence of cracks in the substrate 11.

In this case, by adopting a structure for the wiring 100 that satisfies at least one of the following conditions, it is possible to suppress the occurrence of peeling or cracking while further improving the electrical characteristics of the wiring substrate 10 as a whole. For example, if the distance d1 is too large, it may become necessary to narrow the second conductive layer 14 due to the distance between adjacent wirings, or it may act as a stub structure, making the electrical design difficult. The structure of the wiring 100 may be such that these conditions are satisfied in a redundant manner, or it may not be necessary to satisfy some of the conditions.
(Condition 1) The distance d1 is equal to or less than the distance d2.
(Condition 2) The thickness t1 is smaller than the distance d1.
(Condition 3) The thickness t2 is greater than the distance d1.

The above-mentioned wiring 100 is not limited to being applied only to wiring 100 arranged only on the first surface 11a or the second surface 11b, but also applies to the first conductive layer 12 and the second conductive layer 14 that include a through electrode in their configuration.

[3. Manufacturing method of wiring board]
Next, a method for manufacturing the wiring board 10 will be described.

5 to 9 are diagrams illustrating a method for manufacturing a wiring board according to the first embodiment of the present disclosure. All of FIGS. 5 to 9 show the cross-sectional shape (cross-sectional view along line A1-A2 in FIG. 1) of a portion corresponding to FIG. 2. First, a substrate 11 having a first surface 11a and a second surface 11b and a through hole 15 penetrating the first surface 11a and the second surface 11b is prepared. The through hole 15 is formed by subjecting the substrate 11 to etching, laser processing, a combination of laser processing and etching, sandblasting, electric discharge processing, drilling, or the like. As shown in FIG. 5, a seed layer 1210 is formed by electroless plating on the first surface 11a, the second surface 11b of the substrate 11, and the inner surface 15a of the through hole 15.

As shown in FIG. 6, a resist mask RM is formed on a portion of the seed layer 1210. A conductive layer is formed by electrolytic plating on the portion of the seed layer 1210 that is exposed through the resist mask RM. This forms the second conductive layer 14. The resist mask RM is then removed.

As shown in FIG. 7, a resist mask RM is formed on the first surface 11a and the second surface 11b of the substrate 11 so as to cover the second conductive layer 14. At this time, the edge of the resist mask RM is positioned outside the second conductive layer 14. The distance from the edge of the second conductive layer 14 to the edge of the resist mask RM roughly corresponds to the distance d1 described above.

As shown in FIG. 8, the seed layer 1210 exposed from the resist mask RM is etched, and then the resist mask RM is removed. This separates each conductive layer, and wiring 100 having a laminated structure of a first conductive layer 12 and a second conductive layer 14 is formed on the substrate 11. Next, as shown in FIG. 9, an insulating layer 22 is formed from the first surface 11a side and the second surface 11b side. At this time, a via hole 23 is formed in the insulating layer 22. Furthermore, a third conductive layer 24 is formed so as to fill the via hole 23, thereby realizing the configuration shown in FIG. 2.

Second Embodiment
The method for manufacturing the wiring 100 is not limited to the above-mentioned method. Another method for manufacturing the wiring 100 will be described.

10 and 11 are diagrams showing a method for manufacturing a wiring according to the second embodiment of the present disclosure. FIG. 10 is a diagram showing the vicinity of the wiring 100 in the structure shown in FIG. 6 in the first embodiment, in which the resist mask RM is removed and then the seed layer 1210 exposed from the plating layer 1410 (corresponding to the second conductive layer 14 shown in FIG. 6) is etched. The seed layers 1210 separated from each other by etching are formed as the first conductive layer 12 on the substrate 11. In this example, the first conductive layer 12 (seed layer 1210) and the plating layer 1410 are formed of different materials. The combination of materials is selected from those that have a higher etching rate for the plating layer 1410 than the etching rate for the first conductive layer 12 for a given etching solution.

Subsequently, as shown in FIG. 11, the plating layer 1410 is wet-etched with the etching solution to etch a part of the exposed part of the plating layer 1410. Here, the upper surface and side surface of the plating layer 1410 that are not in contact with the first conductive layer 12 are exposed. Therefore, the plating layer 1410 is etched from the upper surface and side surface to form a second conductive layer 14 that is smaller overall. At this time, the first conductive layer 12 is hardly etched, and as shown in FIG. 11, a part of the first conductive layer 12 is exposed from the second conductive layer 14, and a structure similar to the second region As2 of the wiring 100 in the first embodiment can be formed. According to this example, unlike the first embodiment, the film thickness of the second conductive layer 14 is slightly reduced. On the other hand, the size of the second region As2 can be controlled by the wet etching time regardless of the alignment accuracy when forming the resist mask RM as in the first embodiment. As a result, the size of the second region As2 can also be controlled with high accuracy.

Third Embodiment
In the third embodiment, a structure similar to that of the first embodiment is adopted in the through electrode portion, but an example in which wiring is arranged not on the substrate 11 but on a configuration equivalent to the insulating layer 22 will be described.

12 is a schematic cross-sectional view showing the details of the wiring structure according to the third embodiment of the present disclosure. Of the first conductive layer 12A constituting the through electrode, the first region As1 is arranged across the inner surface 15a, the first surface 11a and the second surface 11b of the through hole 15, and the second region As2 is arranged on the first surface 11a and the second surface 11b. This configuration is the same as in the first embodiment. The insulating layer 22A covering the second region As2 is an organic insulating material and includes an opening 225A having a diameter larger than that of the through hole 15. The first conductive layer 12A is exposed in the portion where the opening 225A is arranged. The second conductive layer 14A is formed in the exposed portion of the first conductive layer 12A, so that portion corresponds to the first region As1.

A fourth conductive layer 16A is disposed between the second conductive layer 14A and the insulating layer 22A. The fourth conductive layer 16A corresponds to a seed layer when the second conductive layer 14A is formed by electrolytic plating. In this example, the fourth conductive layer 16A is not disposed between the first conductive layer 12A and the second conductive layer 14A, but may be disposed therein.

As in the first embodiment, a third conductive layer 24 is disposed on the second conductive layer 14A and is connected to the second conductive layer 14A via an insulating layer 22 and a via hole 23 formed in the insulating layer 22 in the first embodiment.

With this structure, in the through electrode portion, the positional relationship between the substrate 11, the first conductive layer 12A, the second conductive layer 14A, and the insulating layer 22A is the same as in the first embodiment, and the other wiring is arranged on the insulating layer 22A. When a pattern with a short wiring interval is adopted, it is not desirable to provide the second region As2, so by using such an insulating layer 22A as a stress buffer layer, wiring without the second region As2 can be used. For example, when wiring is provided to connect with the through electrode on the substrate surface, and a pattern is adopted in which the second regions As2 of adjacent wirings are connected and the distance between the wirings is short, which may cause a short circuit, it is not desirable to provide the second region As2. Therefore, by forming wiring on the insulating layer 22A, it is also possible to use wiring without the second region As2.

In addition, in the through electrode portion, the expansion or contraction of the substrate 11 due to the difference in thermal expansion coefficient occurs not only in the surface direction of the substrate 11 but also in the thickness direction, so stress is likely to occur. Therefore, peeling and cracking are likely to occur in the through electrode, but by adopting such a structure, the occurrence of peeling and cracking can be suppressed.

13 to 15 are diagrams showing a method for manufacturing a wiring board according to the third embodiment of the present disclosure. All of FIGS. 13 to 15 show the cross-sectional shape of a portion corresponding to FIG. 12. First, a substrate 11 having a first surface 11a and a second surface 11b and a through hole 15 penetrating the first surface 11a and the second surface 11b is prepared. As shown in FIG. 13, a seed layer is formed by electroless plating on the first surface 11a, the second surface 11b, and the inner surface 15a of the through hole 15 of the substrate 11, and is processed into a desired pattern to form a first conductive layer 12A.

Next, as shown in FIG. 14, an insulating layer 22A made of an organic insulating material is formed on the first surface 11a and the second surface 11b of the substrate 11 so as to cover the end portion (corresponding to the second region As2) of the first conductive layer 12A. At this time, an opening 225A having a diameter larger than that of the through hole 15 is formed in the insulating layer 22A.

Next, as shown in FIG. 15, a seed layer 1610A is formed by a film formation method such as sputtering, vapor deposition, or electroless plating, and then a resist mask RM is formed. As a result, a seed layer 1610A is formed on the surface of the insulating layer 22A. Thereafter, as in the first embodiment, a second conductive layer 14A is formed by electrolytic plating, and the resist mask RM is removed, the exposed seed layer 1610A is removed, an insulating layer 22 is formed, and a third conductive layer 24 is formed, resulting in the configuration shown in FIG. 12.

Fourth Embodiment
In the fourth embodiment, an example in which the second region As2 in the third embodiment is disposed on an inner side surface 15a of a through hole 15 will be described.

16 is a schematic cross-sectional view showing the details of the structure of the wiring according to the fourth embodiment of the present disclosure. The first conductive layer 12B constituting the through electrode is arranged in a band shape so as to go around the inside of the through hole 15. Of the first conductive layer 12B, the first region As1 and the second region As2 are arranged on the inner surface 15a of the through hole 15 and do not extend to the first surface 11a and the second surface 11b. The insulating layer 22B covering the second region As2 is an organic insulating material, and is arranged inside the through hole 15 so as to cover the end of the second region As2 of the first conductive layer 12B, and a band-shaped opening 225B is arranged so as to go around the inside of the through hole 15 between the two second regions As2. The first conductive layer 12B is exposed in the portion where the opening 225B is arranged. Since the second conductive layer 14B is formed in the exposed portion of the first conductive layer 12B, that portion corresponds to the first region As1. Note that even in this configuration, the first region As1 is surrounded by the second region As2. In other words, as in other embodiments, the first region As1 is not disposed at the end of the first conductive layer 12B.

A fourth conductive layer 16B is disposed between the second conductive layer 14B and the insulating layer 22B. The fourth conductive layer 16B corresponds to a seed layer when the second conductive layer 14B is formed by electrolytic plating. In this example, the fourth conductive layer 16B is not disposed between the first conductive layer 12B and the second conductive layer 14B, but may be disposed therein.

As in the first embodiment, a third conductive layer 24 is disposed on the second conductive layer 14B and is connected to the second conductive layer 14B via the insulating layer 22 in the first embodiment and a via hole 23 formed in the insulating layer 22.

With this structure, in the through electrode portion, the positional relationship between the substrate 11, the first conductive layer 12B, the second conductive layer 14B, and the insulating layer 22B is the same as that in the first embodiment even inside the through hole 15, and the other wiring is arranged on the insulating layer 22B. When a pattern with a short wiring interval is adopted, it is not desirable to provide the second region As2, so by adopting such an insulating layer 22B as a stress buffer layer, wiring without the second region As2 can be used. For example, when wiring that connects to the through electrode is provided on the substrate surface, and a pattern is adopted in which the distance between the wirings is short and there is a risk of short circuit due to the second regions As2 of adjacent wirings being connected, it is not desirable to provide the second region As2. Therefore, by forming wiring on the insulating layer 22B, it is also possible to use wiring without the second region As2 by using it as a stress buffer layer.

In addition, in the through electrode portion, the expansion or contraction of the substrate 11 due to the difference in thermal expansion coefficient occurs not only in the surface direction of the substrate 11 but also in the thickness direction, so stress is likely to occur. Therefore, peeling and cracking are likely to occur in the through electrode, but by adopting such a structure, the occurrence of peeling and cracking can be suppressed.

17 to 19 are diagrams showing a method for manufacturing a wiring board according to the fourth embodiment of the present disclosure. All of FIGS. 17 to 19 show the cross-sectional shape of the portion corresponding to FIG. 16. First, a substrate 11 having a first surface 11a and a second surface 11b and a through hole 15 penetrating the first surface 11a and the second surface 11b is prepared. As shown in FIG. 17, a resist mask RM is formed from the first surface 11a side and the second surface 11b side of the substrate 11. At this time, the resist mask RM is formed so as to penetrate into a part of the inside of the through hole 15. The penetration amount of the resist mask RM is adjusted by the size of the opening diameter of the portion of the resist mask RM corresponding to the through hole 15, the viscosity of the resist mask RM, etc. The center of the inner surface 15a of the through hole 15 is not covered by the resist mask RM.

Next, a first conductive layer 12B, which will become a seed layer, is formed by electroless plating. In this example, electroless plating is performed under conditions that make it easier to form the electroless plating on inorganic materials than on organic materials. As a result, as shown in FIG. 18, the first conductive layer 12B is formed on the portion of the inner surface 15a that is exposed through the resist mask RM. The resist mask RM is then removed, and an insulating layer 22B made of an organic insulating material is formed inside the through hole 15 so as to cover the end portion (corresponding to the second region As2) of the first conductive layer 12B, as shown in FIG. 19. This structure is achieved by setting the processing conditions so that the amount of penetration of the insulating layer 22B into the through hole 15 is greater than when the resist mask RM is formed.

The subsequent steps are the same as those described in the third embodiment with reference to FIG. 15. That is, a seed layer is formed on the insulating layer 22B by electroless plating under conditions that make it easier to form the seed layer on an organic material than on an inorganic material, and a resist mask RM is then formed. After that, a second conductive layer 14B is formed by electrolytic plating, and the resist mask RM is removed, the exposed seed layer is removed, the insulating layer 22 is formed, and the third conductive layer 24 is formed, resulting in the configuration shown in FIG. 16.

Fifth Embodiment
In the fifth embodiment, an example in which a structure similar to that of the fourth embodiment is manufactured by a different method will be described.

20 to 23 are diagrams showing a method for manufacturing a wiring board according to the fifth embodiment of the present disclosure. All of FIGS. 20 to 23 show the cross-sectional shape of a portion corresponding to FIG. 16. First, a substrate 11 having a first surface 11a and a second surface 11b and a through hole 15 penetrating the first surface 11a and the second surface 11b is prepared. As shown in FIG. 20, a seed layer 1210B is formed by electroless plating, and a resist mask RM is formed from the first surface 11a side and the second surface 11b side of the substrate 11. The formation of the resist mask RM is similar to that of the fourth embodiment, but the fifth embodiment differs from the fourth embodiment in that a seed layer 1210B is formed before that.

Next, as shown in FIG. 21, a plating layer 1215B is formed on the portion of the seed layer 1210B exposed from the resist mask RM by electrolytic plating. Thereafter, as shown in FIG. 22, the resist mask RM is removed, and the seed layer 1210B is etched using the plating layer 1215B as a mask, to form a first conductive layer 12B having a structure in which the seed layer 1210B and the plating layer 1215B are stacked, as shown in FIG. 23. The subsequent steps are the same as those from FIG. 19 in the fourth embodiment.

Sixth Embodiment
In the above-described embodiment, the wiring 100 is configured by stacking the first conductive layer 12 and the second conductive layer 14, but in the sixth embodiment, an example is described in which a structure similar to the wiring 100 is realized by using an integrated layer.

24 and 25 are diagrams showing a method for manufacturing a wiring according to the sixth embodiment of the present disclosure. First, as shown in FIG. 24, a conductive layer 1010C is formed on a substrate 11, and a resist mask RM is formed so as to cover a part of the conductive layer 1010C. The part covered by the resist mask RM corresponds to the first region As1, and the other part corresponds to the second region As2. Next, the part of the conductive layer 1010C exposed from the resist mask RM is etched. At this time, it is preferable to use etching with a strong anisotropy. Then, as shown in FIG. 25, a wiring 100C is formed having a part corresponding to the first region As1 and the second region As2 that is thinner than the first region As1. At this time, the relationship of the lengths as shown in FIG. 3 and FIG. 4 may be similarly applied. In this way, even if the wiring is formed in one layer, by adopting a structure similar to that in the case of forming it in two layers, the same effect as the wiring structure in the first embodiment can be obtained.

<Modification>
The present disclosure is not limited to the above-described embodiment, and includes various other modified examples. For example, the above-described embodiment has been described in detail to clearly explain the present disclosure, and is not necessarily limited to those having all the configurations described. In addition, a part of the configuration of one embodiment may be replaced with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. In addition, it is possible to add, delete, or replace other configurations with respect to a part of the configuration of each embodiment. Some modified examples will be described below. Note that the example of modifying the first embodiment can also be applied as an example of modifying other embodiments.

(1) The material of the second conductive layer 14 is not limited to Cu, but may include conductive materials such as gold (Au), silver (Ag), copper (Cu), iron (Fe), nickel (Ni), platinum (Pt), palladium (Pd), ruthenium (Ru), and tungsten (W).

(2) Various methods can be used for patterning conductive layers such as the third conductive layer 24. For example, the formation method may be a semi-additive method, a full-additive method, a subtractive method, a damascene method, or a dual damascene method.

(3) The substrate 11 described above has a structure in which at least the inorganic insulating material is exposed on the surface, but may have a structure in which the organic insulating material is exposed on the surface. As described above, in wiring arranged on an inorganic insulating material, adopting the structure in the first embodiment is effective in improving adhesion. On the other hand, in wiring arranged on an organic insulating material, problems such as adhesion are less likely to occur than in wiring arranged on an inorganic insulating material, but the contact area is increased by adopting a structure similar to that of the first embodiment. Therefore, adhesion is improved compared to when that structure is not adopted.

[Example (Simulation Results)]
In order to verify the effect of the structure of the wiring 100 of the present disclosure, the transmission characteristics were confirmed by simulation. A microstrip structure was adopted as the wiring structure, and the wiring length was 1.0 mm, and the wiring width corresponding to the first region As1 was 20 μm.

Considering the characteristics of the wiring 100 disclosed herein, the thickness t1 must be smaller than the distance d1, so the thickness of the wiring was set to 0.5 μm for the first layer (corresponding to the first conductive layer 12) and 4.5 μm for the second layer (corresponding to the second conductive layer 14). Four numerical values were substituted for the distance d1 as a variable, and the obtained S parameters (S11, S21) were compared with the distance d1 (four numerical values). The numerical values substituted for the distance d1 were 0.0 μm, 1.0 μm, 2.0 μm, and 5.0 μm, with 1.0 μm, 2.0 μm, and 5.0 μm corresponding to the present invention, and 0.0 μm corresponding to the results of the prior art.

The transmission characteristics used in the simulation are S parameters, and in this case, S11 (reflection loss at terminal 1: reflection characteristic) and S21 (insertion loss from terminal 1 to terminal 2: transmission characteristic) were the targets. Here, these characteristics were compared using the operating frequency as a variable. When giving representative examples in the following explanation, a comparison was made using characteristics at an operating frequency of 20 GHz.

In other words, to put it simply, the embodiment disclosed here assumes a microstrip structure, applies distance d1 and operating frequency as two variables, and compares the S-parameters S11 and S21 at this time. The analysis results based on the above are shown below.

Figure 26 shows the results of a simulation of the operating frequency dependency of the reflection characteristic (S11). As shown in Figure 26, S11 is roughly consistent regardless of the value of the distance d1. In other words, S11 is almost independent of the distance d1.

Figure 27 is a diagram showing the results of a simulation of the operating frequency dependency of the pass characteristic (S21). In S21, it appears that a difference occurs depending on the value of the distance d1 compared to S11. Therefore, the results of the conventional technology and the present invention were compared more closely. First, the characteristic value (dB) at an operating frequency of 20 GHz was converted to gain, which is the ratio of input to output. Next, the ratios were calculated for distances d1 of 0.1 μm, 0.2 μm, and 0.5 μm so that the gain when distance d1 is 0.0 μm was 1.00. As a result, the ratios were 0.995, 0.990, and 0.988 for distances d1 of 0.1 μm, 0.2 μm, and 0.5 μm, respectively. In this way, it was confirmed that the structure of the wiring 100 according to the present disclosure does not cause a large difference in gain. As described above, it can be seen that even if the structure of the wiring 100 described in the present disclosure is adopted, the effect on the transmission characteristics at high frequencies is minor compared to the conventional structure with distance d1 = 0.0 μm.

10...wiring board, 11...board, 11a...first surface, 11b...second surface, 12, 12A, 12B...first conductive layer, 14, 14A, 14B...second conductive layer, 15...through hole, 15a...inner surface, 16, 16A, 16B...fourth conductive layer, 22, 22A, 22B...insulating layer, 23...via hole, 24...third conductive layer, 25...solder ball, 80...circuit board, 90...semiconductor chip, 100, 100C...wiring, 225, 225A, 225B...opening, 1010C...conductive layer, 1210...seed layer, 1215B...plating layer, 1410...plating layer, 1610A...seed layer

Claims (7)

A substrate including an inorganic insulating material on a surface thereof;
a first conductive layer disposed on the inorganic insulating material and having a first region and a second region surrounding the first region;
a second conductive layer disposed on the first region of the first conductive layer, the second conductive layer being thicker than the first conductive layer;
an organic insulating layer disposed on the second region of the first conductive layer and on the inorganic insulating material;
a third conductive layer connected onto the second conductive layer;
Including,
a thickness of the second conductive layer is greater than a distance from an outer edge of the first region to an outer edge of the second region;
the third conductive layer includes a contact portion with the second conductive layer and an extension portion extending outward from the contact portion,
A wiring board , wherein a distance from an outer edge of the first region to an outer edge of the second region is equal to or less than a distance from an outer edge of the contact portion to an outer edge of the extension portion. The wiring board according to claim 1 , wherein the thickness of the first conductive layer is smaller than a distance from an outer edge of the first region to an outer edge of the second region. The substrate has a through hole formed therein, the through hole penetrating the first surface and the second surface,
the first conductive layer is disposed on an inner side surface of the through hole, on the first surface, and on the second surface;
The wiring board according to claim 1 , wherein the second region is present on both the first surface and the second surface. The substrate has a through hole formed therein, the through hole penetrating the first surface and the second surface,
The first conductive layer is disposed on an inner surface of the through hole,
The wiring board according to claim 1 , wherein the second region is present on an inner side surface of the through hole. The wiring board according to claim 1 , wherein the first conductive layer and the second conductive layer have different physical properties. The wiring board according to claim 1 , wherein the first conductive layer and the second conductive layer are made of different materials. A wiring board according to any one of claims 1 to 6 ,
a semiconductor chip electrically connected to the wiring board;
A semiconductor device comprising:

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