JP7444210B2 - Glass circuit board with built-in capacitor - Google Patents

Description

The present invention relates to a glass circuit board with a built-in capacitor and a method of manufacturing the glass circuit board with a built-in capacitor, and particularly relates to a method that can realize high reliability and stable capacitance of a capacitor.

2. Description of the Related Art As electronic devices become more sophisticated and smaller, there is an increasing demand for higher density wiring boards that constitute semiconductor devices. In response to the miniaturization of circuit wiring, passive components such as resistors, capacitors, and inductors are also required to be miniaturized. However, there is a limit to further miniaturization only by miniaturizing these passive components and high-density mounting on the substrate surface. Therefore, a technique has been proposed in which a passive element is built into a mounting board (see, for example, Patent Document 1). With this technology, miniaturization is possible by incorporating passive elements into a multilayer substrate by forming them by printing, vacuum film-forming, or the like. Furthermore, by forming it in a multilayer substrate, it is possible to shorten the wiring length, and it is also possible to reduce high frequency noise.

On the other hand, organic materials such as glass epoxy resin are generally used as materials for wiring boards. In recent years, advances in drilling techniques for glass materials have made it possible, for example, to form small-diameter through holes of 100 μm or less at a pitch of 150 μm or less in a 300 μm thick glass substrate. For this reason, electronic circuit boards using glass materials are attracting attention. A circuit board using a glass material for its core (hereinafter referred to as a "glass circuit board") has a low coefficient of linear thermal expansion (CTE) of 2 ppm to 8 ppm, and has high mounting reliability because it matches a silicon chip. Furthermore, since it has excellent flatness, highly accurate mounting is possible. Furthermore, since it has excellent flatness, it also has excellent ability to form fine wiring and high-speed transmission.

Furthermore, research is being conducted on the application of glass to electronic circuit boards that take advantage of its transparency, chemical stability, high elasticity, and low cost. The commercialization of LC branching filters (duplexers) and the like is expected (for example, see Patent Document 2). Since it is necessary to form decoupling capacitors, LC circuits, etc. in electronic circuits having glass substrates as cores, there is an increasing demand for incorporating capacitors. In order to incorporate a capacitor, it is conceivable to form a thin film capacitor having an MIM structure (Metal insulator metal) in which a dielectric material is sandwiched between a lower electrode layer and an upper electrode layer.

Japanese Patent Application Publication No. 2000-151114 Patent No. 5982585

When attempting to incorporate a capacitor into the above-mentioned glass circuit board, the following problems occurred. That is, there is a problem in that the capacitance of the capacitor changes depending on the roughness of the surface of the lower electrode layer of the capacitor portion. In particular, when the surface of the lower electrode layer is rough, the unevenness causes a short circuit in the capacitor and a large change in capacitance. In addition, variations in the roughness of the lower electrode layer surface within the substrate plane are directly linked to variations in capacitance of the capacitor, so it is necessary to have a uniform lower electrode layer surface within the substrate plane, and processing control with high precision during the manufacturing process. There is a need to.

Therefore, the present invention was made to solve the above-mentioned problems, and provides a capacitor-embedded glass that can achieve high reliability and stabilized capacity, which is necessary when electronic circuits and electronic devices are made smaller and thinner. It is an object of the present invention to provide a method for manufacturing a glass substrate with a built-in capacitor that can manufacture a circuit board and the glass substrate with a built-in capacitor at a high yield.

The invention according to claim 1 of the present invention as a means for solving the above problems includes a glass substrate, a conductor circuit layer provided on the glass substrate, and a part of the conductor circuit layer as a lower electrode. and a capacitor further including a dielectric layer provided on the lower electrode and an upper electrode layer provided on the dielectric layer, the upper surface of the conductor circuit layer having a first upper surface region; a second upper surface region serving as an upper surface of a convex portion protruding from the first upper surface region; the second upper surface region is the upper surface of the lower electrode; The corresponding portion is thinner than the portion corresponding to the second upper surface region, and the dielectric layer is located inside the second upper surface region in a plan view in the lamination direction of the glass substrate and the conductive circuit layer. The dielectric layer is a glass circuit board with a built-in capacitor, and the dielectric layer has a shape in which unnecessary portions are removed using the upper electrode layer as a mask .

According to a second aspect of the present invention, the capacitor further includes a lower adhesive layer provided between the lower electrode and the dielectric layer, the upper electrode layer is made of copper, and the lower adhesive layer is provided between the lower electrode and the dielectric layer. 2. The glass circuit board with a built-in capacitor according to claim 1, wherein the layer contains Cu or a Cu alloy, and the lower adhesive layer has a shape in which an unnecessary portion is removed using the upper electrode layer as a mask.

A third aspect of the present invention is the capacitor built-in glass circuit board according to the second aspect, wherein the lower adhesive layer has a thickness of 10 nm or more and 1 μm or less .

According to a fourth aspect of the present invention, the dielectric layer is selected from the group consisting of alumina, silica, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, and strontium titanate. 4. The glass circuit board with a built-in capacitor according to claim 3, which is made of a material .

The invention according to claim 5 of the present invention further includes a seed metal layer provided between the glass substrate and the conductor circuit board, the conductor circuit layer is made of copper, and the seed metal layer is made of Cu or 5. A glass circuit board with a built-in capacitor according to any one of claims 1 to 4, which contains a Cu alloy.

According to the present invention, by making the surface roughness of the lower electrode uniform, short-circuit induction and large changes in capacitor capacitance can be prevented, high reliability and capacitance stability can be achieved, and the above-mentioned It becomes possible to make the surface roughness uniform by easy processing control.

FIG. 1 is a vertical cross-sectional view showing a main part of a glass circuit board with a built-in capacitor according to an embodiment of the present invention. FIG. 3 is a plan view of the main parts of the glass circuit board with a built-in capacitor, viewed in the stacking direction. FIG. 3 is a vertical cross-sectional view showing the manufacturing steps of the capacitor built-in glass circuit board and the capacitor built-in glass circuit board manufacturing method. FIG. 3 is a vertical cross-sectional view showing the manufacturing process of the glass circuit board with a built-in capacitor. FIG. 3 is a vertical cross-sectional view showing the manufacturing process of the glass circuit board with a built-in capacitor. FIG. 3 is a vertical cross-sectional view showing the manufacturing process of the glass circuit board with a built-in capacitor. FIG. 3 is a vertical cross-sectional view showing the manufacturing process of the glass circuit board with a built-in capacitor. FIG. 3 is a vertical cross-sectional view showing the manufacturing process of the glass circuit board with a built-in capacitor. FIG. 3 is a vertical cross-sectional view taken along line AA in FIG. 2 and shown in the direction of the arrow, illustrating the manufacturing process of the capacitor forming portion of the glass circuit board with a built-in capacitor. FIG. 3 is a vertical cross-sectional view showing the manufacturing process of the same capacitor forming part. FIG. 3 is a vertical cross-sectional view showing the manufacturing process of the same capacitor forming part. FIG. 3 is a vertical cross-sectional view showing the manufacturing process of the same capacitor forming part. FIG. 3 is a vertical cross-sectional view showing the manufacturing process of the same capacitor forming part. FIG. 3 is a vertical cross-sectional view showing the manufacturing process of the same capacitor forming part. FIG. 3 is a vertical cross-sectional view showing the manufacturing process of the same capacitor forming part. FIG. 3 is a vertical cross-sectional view showing the manufacturing process of the same capacitor forming part. FIG. 3 is a vertical cross-sectional view showing the manufacturing process of the same capacitor forming part. FIG. 3 is a vertical cross-sectional view showing a comparative example of the manufacturing process of a glass circuit board with a built-in capacitor. FIG. 3 is a vertical cross-sectional view showing the same manufacturing process. FIG. 3 is a vertical cross-sectional view showing the same manufacturing process. FIG. 7 is a vertical cross-sectional view showing a main part of an electronic component according to a modification of the embodiment of the present invention.

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a longitudinal cross-sectional view showing a main part of a capacitor built-in glass circuit board 10 according to a first embodiment of the present invention. Note that P in FIG. 3F indicates a capacitor forming portion.

As shown in FIG. 1, the capacitor built-in glass circuit board 10 has a glass substrate 100.

A through hole 101 passing through the front and back surfaces of the glass substrate 100 is formed, and a seed metal layer 102 is formed over the inner wall surface of the through hole 101 and both surfaces of the glass substrate 100. A conductive circuit layer 104 is formed on the seed metal layer 102 . A portion of the conductor circuit layer 104 becomes a lower electrode 105 that constitutes a capacitor 109.

On the upper surface (front surface) 106 of the conductor circuit layer 104 of the capacitor 109, an upper surface 106a region of the conductor circuit layer and an upper surface (surface of the convex portion) 106b region of the lower electrode 105 are formed (see FIG. 4D).

As shown in FIG. 1, the capacitor 109 basically consists of a lower electrode, a dielectric layer, and an upper electrode, but may further include an adhesion layer or a seed layer. Therefore, in one form, as shown in FIG. 4I, a lower adhesion layer 110, a dielectric layer 111, an upper adhesion layer 112, and a seed metal layer 113 are sequentially provided on the lower electrode 105. An upper electrode 114 is formed on the seed metal layer 113.

Insulating resin layers 131 are also provided on both sides of the glass substrate. A via hole 132 and a laminated conductor circuit layer 133 are formed in the insulating resin layer 131 . Further, a second insulating resin layer and a second conductor circuit layer are formed and laminated as necessary. An external connection terminal 134 is formed at the outermost side. A solder ball 135 is formed at a predetermined portion of the external connection terminal 134 .

Next, the material, shape, etc. of each element will be explained in detail. The glass substrate 100 is a transparent glass material that transmits light. The components of the glass, the blending ratio of each component contained in the glass, and the method for producing the glass are not particularly limited. For example, examples of the glass include alkali-free glass, alkali glass, borosilicate glass, quartz glass, sapphire glass, photosensitive glass, etc., but any glass material containing silicate as a main component may be used. Furthermore, other so-called glass materials may also be used. However, in the semiconductor application according to this embodiment, it is desirable to use alkali-free glass. Further, the thickness of the glass substrate 100 is preferably 1 mm or less, but more preferably 0.1 mm or more and 0.8 mm or less in consideration of ease of the glass through-hole forming process and handling during manufacturing.

Examples of methods for manufacturing the glass substrate 100 include a float method, a down-draw method, a fusion method, an up-draw method, and a roll-out method. Glass materials manufactured by any method may be used, and the present embodiment It is not limited to those of The coefficient of linear expansion of the glass is preferably -1 ppm/K or more and 15.0 ppm/K or less. The reason for this is that if it is -1 ppm/K or less, it becomes difficult to select the glass material itself, and the glass cannot be manufactured at a low cost. On the other hand, if it is 15.0 ppm/K or more, the difference in thermal expansion coefficient with other layers will be large and reliability will decrease. Furthermore, when a silicon chip is mounted on the substrate of this embodiment, the reliability of connection with the silicon chip decreases. The linear expansion coefficient of the glass is more preferably 0.5 ppm/K or more and 8.0 ppm/K or less, and even more preferably 1.0 ppm/K or more and 4.0 ppm/K or less.

Furthermore, a functional film such as an antireflection film or an IR cut filter may be formed on the glass substrate 100 in advance. Further, functions such as strength imparting, antistatic imparting, coloring, texture control, etc. may be imparted. Examples of these functional films include hard coat films for imparting strength, antistatic films for imparting antistatic properties, optical filter films for coloring, and anti-glare and light scattering films for texture control. Not as long. As a method for forming these functional films, film forming techniques such as vapor deposition, sputtering, and wet methods are used.

The seed metal layer 102 acts as a power supply layer for electroplating in wiring formation in a semi-additive construction method. The seed metal layer 102 provided directly above the glass substrate 100 and on the inner wall of the through hole 101 is formed by, for example, a sputtering method or a CVD method, and includes, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu ₃ N ₄ and a Cu alloy alone or in combination are used. Furthermore, an electroless plating layer (electroless copper plating, electroless nickel plating, etc.) is formed thereon.

In this embodiment, a titanium layer that has good adhesion to glass, and then a copper layer are sequentially formed by sputtering, taking into consideration electrical properties, ease of manufacture, and cost. The total film thickness of the titanium and copper layers for circuit formation on the glass substrate is desirably 1 μm or less because it is advantageous for forming fine wiring by a semi-additive method. If it is thicker than 1 μm, it is difficult to form fine wiring with a pitch of 30 μm or less.

The conductor circuit layer 104 is preferably electrolytic copper plating because it is simple, inexpensive, and has good electrical conductivity; however, in addition to electrolytic copper plating, electrolytic nickel plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold Plating, electrolytic rhodium plating, electrolytic iridium plating, etc. may be used.

In the capacitor 109, the lower adhesion layer 110 has the function of improving the adhesion between the lower electrode 105 and the dielectric layer 111, and the upper adhesion layer 112 has the function of improving the adhesion between the dielectric layer 111 and the seed metal layer 113. It has the ability to improve. The material of the lower adhesive layer 110 and the upper adhesive layer 112 is, for example, Ti. In addition, for example, Cu, Ni, Al, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, or a Cu alloy alone or in combination may be used. Ti is excellent in terms of adhesion, electrical conductivity, ease of manufacture, and cost.

The thickness of the lower adhesive layer 110 and the upper adhesive layer 112 is preferably, for example, 10 nm or more and 1 μm or less. If it is less than 10 nm, there is a possibility that the adhesion strength will be insufficient. If it exceeds 1 μm, not only will it take too much time to form a film in the manufacturing process described below, resulting in a lack of mass productivity, but there is also a risk that the process of removing unnecessary portions will take even more time. The thickness of the lower adhesive layer 110 and the upper adhesive layer 112 is more preferably 10 nm or more and 500 nm or less. Although the lower adhesion layer 110 and the upper adhesion layer 112 may have different thicknesses, it is preferable that they have the same thickness in order to simplify the structure. Further, if the lower electrode 105 and the dielectric layer 111 have sufficient adhesion, the lower adhesion layer 110 may be omitted. If the adhesion between the dielectric layer 111 and the seed metal layer 113 is sufficient, the upper adhesion layer 112 may be omitted.

The dielectric layer 111 can be selected from alumina, silica, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, and strontium titanate from the viewpoint of insulation and dielectric constant. The thickness of the dielectric layer 111 is preferably 10 nm or more and 5 μm or less. If the thickness of the dielectric layer 111 is 10 nm or less, insulation cannot be maintained and the function as a capacitor will not be expressed. When the thickness of the dielectric layer 111 is 5 μm or more, not only does it take too much time to form the film, resulting in a lack of mass productivity, but the process of removing unnecessary portions takes even more time. More preferably, the thickness is 50 nm or more and 1 μm or less.

Seed metal layer 113 is a power supply layer for forming upper electrode 114 of capacitor 109 by a semi-additive method. The seed metal layer 113 is made of, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, or a combination of Cu alloys. can do. More preferably, it is copper because it facilitates subsequent etching removal. The thickness of the seed metal layer 113 is preferably 10 nm or more and 5 μm or less. If the thickness of the seed metal layer 113 is less than 100 nm, there is a possibility that failure in conduction will occur in the subsequent electrolytic plating process. If the thickness of the seed metal layer 113 exceeds 5 μm, it will take time to remove it by etching. The thickness of the seed metal layer 113 is more preferably 100 nm or more and 500 nm or less.

The upper electrode 114 is an electroplated layer. Electrolytic copper plating is desirable because it is simple, inexpensive, and has good electrical conductivity, but in addition to electrolytic copper plating, electrolytic nickel plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, Electrolytic iridium plating or the like may also be used.

The thickness of the upper electrode 114 (thickness of electrolytic copper plating) is preferably 3 μm or more and 30 μm or less. If the thickness is less than 3 μm, there is a risk that the circuit may disappear depending on the etching process after forming the upper electrode 114. Furthermore, there is a risk that the connection reliability and electrical conductivity of the circuit will decrease. When the electrolytic copper plating thickness exceeds 30 μm, it is necessary to form a resist layer with a thickness of 30 μm or more, which increases manufacturing costs. Furthermore, since resist resolution deteriorates, it becomes difficult to form fine wiring with a pitch of 30 μm or less. More preferably, it is 5 μm or more and 25 μm or less. More preferably, the thickness is 10 μm or more and 20 μm or less.

Thereafter, as shown in FIG. 1, a capacitor 109 is formed using a part of the conductive circuit layer 104 directly above the glass as a lower electrode, and then an insulating resin layer 131 and a via hole 132 are formed. Thereafter, multilayer wiring is formed by repeatedly forming the laminated conductor circuit layer 133 and the insulating resin layer 131. Note that the conductor circuit layer 104 and the laminated conductor circuit layer 133 can be formed using a known semi-additive method or subtractive method. Furthermore, after forming the laminated conductor circuit layer 133, external connection terminals 134 are formed. Furthermore, a solder ball 135 is formed on the external connection terminal 134.

As shown in FIG. 1, the circuit board according to this embodiment may have a laminated conductor circuit layer 133, external connection terminals 134, and solder balls 135 on one side, or may have them on both sides.

Note that the insulating resin layer 131 may be a solder resist as long as it is the outermost layer, and is not limited to this embodiment. Further, the external connection terminal 134 may be subjected to surface treatment. Surface treatment improves the bondability with the solder balls 135.

The surface treatment can be performed by forming a tin or tin alloy plating film, an electroless Ni-P/electroless Pd-P/Au plating film, an electroless Ni-P/Au plating film, or the like. Alternatively, a pre-solder treatment or an organic film treatment such as OSP (Organic Solderability PRerservative) may be performed. The solder balls 135 can be formed by a screen printing method, a solder ball transfer mounting method, an electrolytic plating method, or the like. The composition of the solder ball can be one or a mixture of tin, silver, copper, bismuth, lead, zinc, indium, antimony, etc., and the mixing ratio of these metal materials does not matter. Wire bonding pads may be provided instead of solder.

FIG. 2 is a plan view of the capacitor periphery of the capacitor built-in glass circuit board as viewed in the stacking direction. This figure shows the lower electrode 105 in the vicinity of the region forming the capacitor 109 in the conductive circuit layer 104. Although described later, the capacitor forming process will be explained using a cross-sectional view taken along line AA in FIG. 2 (see FIG. 4).

Next, a method for manufacturing the capacitor built-in glass circuit board 10 will be described. 3A to 3F are longitudinal cross-sectional views showing the manufacturing process of a glass circuit board with a built-in capacitor that constitutes the glass circuit board with a built-in capacitor 10. FIG.

As shown in FIG. 3A, a glass substrate 100 is prepared. Subsequently, a through hole 101 is formed in the glass substrate 100 as shown in FIG. 3B. The cross-sectional shape and diameter of the through hole 101 are not limited by this embodiment. For example, the through-hole may have a shape in which the diameter at the center is narrower than the top diameter and the bottom diameter, or may have a shape in which the bottom diameter is smaller than the top diameter. Further, the through hole may have a shape in which the diameter at the center is wider than the top diameter and the bottom diameter. Known methods for forming through holes include laser machining, electrical discharge machining, sandblasting when using a photosensitive resist material, dry etching, and chemical etching using hydrofluoric acid or the like. Furthermore, it is also possible to create a glass core using photosensitive glass. Laser machining and electric discharge machining are preferred because they are simple and have good throughput. Lasers that can be used can be selected from CO2 lasers, UV lasers, picosecond lasers, femtosecond lasers, and the like.

Subsequently, as shown in FIG. 3C, a seed metal layer 102 is formed on the surface of the glass substrate 100 in which the through hole 101 is formed and inside the through hole. The seed metal layer 102 acts as a power supply layer for electroplating in wiring formation in a semi-additive construction method.

In the process of forming the seed metal layer 102, titanium and copper layers are formed on the glass substrate 100, and then an electroless plating layer is formed. In the case of only titanium and copper layers, a metal film cannot be formed entirely inside the through hole 101, resulting in a decrease in connection reliability of the through hole 101. According to this embodiment, the connection reliability of the through hole 101 can be improved by reinforcing the metal layer inside the through hole 101 by electroless plating. Examples of the electroless plating layer include electroless copper plating and electroless nickel plating, but electroless nickel plating is used because it has good adhesion to glass, titanium, and copper layers. If the nickel plating layer is thick, not only will it be difficult to form fine wiring, but also the adhesion will decrease due to increased film stress. Therefore, the thickness of electroless nickel plating is preferably 1 μm or less. Moreover, it is more preferably 0.5 μm or less, and still more preferably 0.3 μm or less. Further, the electroless nickel plating film may contain phosphorus, which is a eutectoid derived from the reducing agent, and sulfur, lead, bismuth, etc. contained in the electroless nickel plating solution. Through the above steps, a substrate (FIG. 3C) in which a seed metal layer 102 is formed on a glass substrate in which a through hole 101 is formed is obtained.

Subsequently, a photoresist pattern PR is formed as shown in FIG. 3D. A method for forming the photoresist pattern PR will be described. First, a photoresist layer is formed on the entire surface of the seed metal layer 102. The photoresist layer to be formed may be a negative type dry film resist, a negative type liquid resist, or a positive type liquid resist, but a negative type photoresist is preferable because the resist layer can be easily formed and is inexpensive. Examples of the resist layer forming method include a roll lamination method and a vacuum lamination method in the case of a negative dry film resist. In the case of a liquid negative type or positive type resist, it can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. The method of forming these resist layers is not limited to this embodiment.

Subsequently, a pattern for forming a desired conductive circuit layer 104 is formed on the photoresist layer by a known photolithography method. That is, the resist pattern is patterned by aligning, exposing, and developing so that the portion where the conductive circuit layer 104 will be formed later is exposed. Although the thickness of the resist layer depends on the thickness of the conductor circuit layer, it is preferably 5 μm or more and 25 μm or less. If it is thinner than 5 μm, it becomes impossible to increase the electrolytic plating layer that becomes the conductive circuit layer to 5 μm or more, and there is a possibility that the connection reliability of the circuit decreases. If it becomes thicker than 25 μm, it becomes difficult to form fine wiring with a pitch of 30 μm or less. In this way, as shown in FIG. 3D, a glass substrate on which a photoresist pattern PR is formed is obtained.

Subsequently, as shown in FIG. 3E, an electrolytic plating layer 103, which will become the basis of the conductor circuit layer 104, is formed by electrolytic plating. Electrolytic plating methods include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, etc., but electrolytic copper plating is simple and inexpensive. It is desirable because it has good electrical conductivity. The thickness of the electrolytic copper plating is preferably 3 μm or more and 30 μm or less. The reason for this is that if the thickness is 3 μm or less, there is a risk that the circuit will disappear depending on the subsequent etching process, and there is also a risk that the connection reliability and electrical conductivity of the circuit will decrease. On the other hand, when the electrolytic copper plating thickness is 30 μm or more, it is necessary to form a resist layer with a thickness of 30 μm or more, which increases manufacturing costs. Furthermore, since resist resolution deteriorates, it becomes difficult to form fine wiring with a pitch of 30 μm or less. More preferably, it is 5 μm or more and 25 μm or less, and even more preferably 10 μm or more and 20 μm or less.

Subsequently, as shown in FIG. 3F, the photoresist pattern PR that is no longer needed after wiring is formed by electrolytic plating is removed, and only the conductor circuit layer 104 is placed on the glass substrate 100, and the seed metal layer 102 is exposed. . The resist removal method is not limited to this embodiment, and for example, the resist can be removed by peeling with an alkaline aqueous solution.

4A to 4I are vertical cross-sectional views showing an enlarged portion of the chain double-dashed line P in FIG. 3F. Note that in these figures, an example of forming the capacitor on the conductive circuit layer 104 formed on the glass substrate 100 is described, but the present invention is not limited to forming the capacitor 109 directly above the conductive circuit layer 104.

FIG. 4A shows a lower electrode 105 that constitutes a capacitor 109 that is part of the conductor circuit layer 104. Subsequently, as shown in FIG. 4B, a protective layer H is formed on the lower electrode 105 in order to protect the upper surface (surface) 106 of the conductive circuit layer. As the protective layer H, the photoresist pattern PR described above can be applied, and it can be formed by the same method as described above. It is preferable that the area where the protective layer is formed is slightly larger than the area where the capacitor will be formed thereafter.

Subsequently, the exposed portion of the seed metal layer 102 shown earlier in FIG. 3F is removed and the circuit is electrically separated, thereby forming the conductive circuit layer 104. In the step of removing the exposed seed layer, the conductor circuit layer 104 is also etched at the same time. At this time, as shown in FIG. 4C, the portion of the conductive circuit layer protected by the protective layer H is not etched, and a convex stepped portion is formed. Although the method for removing the seed layer is not limited to this embodiment, it is possible to use a method in which the electroless Ni layer, the copper layer, and the titanium layer are sequentially removed by chemical etching. The type of etching solution is appropriately selected depending on the type of metal to be removed, and is not limited by this embodiment.

Subsequently, as shown in FIG. 4D, the protective layer H that is no longer needed is removed. The protective layer H can be removed by a peeling process using a known aqueous alkali solution, similar to the photoresist pattern PR described above. In this case, the area where the protective layer H was formed was not etched because the conductor circuit layer 104 was protected from the etching solution.On the other hand, only the unprotected area of the conductor circuit layer was etched, and the area on the conductor circuit layer 104 was not etched. A convex step portion is formed. This convex portion becomes a region where a capacitor 109 is formed as a lower electrode 105.

Subsequently, as shown in FIG. 4E, a lower adhesion layer 110, a dielectric layer 111, an upper adhesion layer 112, and a seed metal layer 113 are sequentially deposited over the entire surface of the lower electrode 105. Methods for forming the layer include vacuum evaporation, sputtering, ion plating, MBE, laser ablation, and CVD, but are not limited to this embodiment.

The lower adhesion layer 110 under the dielectric layer 111 has a function of improving the adhesion between the dielectric layer 111 and the conductive circuit layer 104. Furthermore, if the adhesion between the dielectric layer 111 and the conductive circuit layer 104 is sufficient, the lower adhesion layer 110 may be omitted. The seed metal layer 113 functions as a power supply layer for forming the upper electrode 114 of the capacitor 109 by a semi-additive method.

Subsequently, a photoresist pattern PS is formed as shown in FIG. 4F. The photoresist pattern PS can be formed by the same method as the photoresist pattern PR described above. In this case, the opening region of the photoresist pattern PS is formed so as to be inside the convex upper surface 106b of the conductor circuit layer, and also inside when viewed from above in the stacking direction (see FIG. 2).

Subsequently, as shown in FIG. 4G, an upper electrode 114 is formed using the seed metal layer 113 by electrolytic plating.

As described above, since the photoresist pattern PS has an opening formed inside the top surface 106b of the convex portion of the conductive circuit layer, the upper electrode 114 is formed only inside the top surface 106b of the convex portion of the conductive circuit layer.

Subsequently, as shown in FIG. 4H, the photoresist pattern PS is removed. The photoresist pattern PS can be removed by a known peeling process using an alkaline aqueous solution.

Subsequently, as shown in FIG. 4I, unnecessary portions of the seed metal layer 113, the upper adhesion layer 112, the dielectric layer 111, and the lower adhesion layer 110 are removed using the upper electrode 114 as a mask. The seed metal layer 113, the upper adhesion layer 112, the dielectric layer 111, and the lower adhesion layer 110 can be removed by chemical etching or dry etching, both of which are known methods. Also, the same method may be used for all layers, and the method is not limited to this embodiment. As described above, since the upper electrode 114 is formed inside the upper surface 106b of the convex portion of the conductive circuit layer, when the unnecessary portion is removed using the upper electrode 114 as a mask, the dielectric layer 111 is formed on the upper surface of the convex portion of the conductive circuit layer. It is formed only inside 106b. Capacitor 109 is formed through the above steps.

Thereafter, as shown in FIG. 1, after a capacitor 109 is formed on the wiring circuit directly above the glass, an insulating resin layer 131 and a via hole 132 are formed. Thereafter, multilayer wiring is formed by repeatedly forming the laminated conductor circuit layer 133 and the insulating resin layer 131. Note that the conductor circuit layer 104 and the laminated conductor circuit layer 133 can be formed using a known semi-additive method or subtractive method. Furthermore, after forming the laminated conductor circuit layer 133, external connection terminals 134 are formed. Furthermore, a solder ball 135 is formed on the external connection terminal 134.

The circuit board according to this embodiment may have a laminated conductor circuit layer 133, an external connection terminal 134, and a solder ball 135 on one side as shown in FIG. Also good. Furthermore, a semiconductor chip 136 and a chip component 137 may be mounted.

A method for forming multilayer wiring will be described below. A known method can be used to form the multilayer wiring. That is, examples of materials that can be used as the insulating resin layer 131 of the multilayer wiring layer include epoxy resin, polyimide, maleimide resin, polyethylene terephthalate, polyphenylene oxide, liquid crystal polymer, and composite materials thereof, photosensitive polyimide resin, and photosensitive polybenzoxazole. , photosensitive acrylic-epoxy resin may also be used. The method for forming the insulating resin is not limited to this embodiment, but if it is in the form of a sheet, vacuum lamination, vacuum pressing, or roll lamination can be used. As long as it is liquid, it can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating.

The thickness of the insulating resin layer 131 is preferably 5 μm or more and 50 μm or less. If the diameter is 50 μm or more, it becomes difficult to reduce the diameter of the via hole 132 that can be formed in the insulating resin layer 131, making it disadvantageous to increase the wiring density. If the diameter is 5 μm or less, it is difficult to ensure interlayer insulation. becomes.

To form the via hole 132 in the multilayer wiring, laser processing can be used if a non-photosensitive insulating resin is used. Examples of lasers include CO2 lasers, UV lasers, picosecond lasers, femtosecond lasers, etc., but preferably UV lasers and CO2 lasers are convenient and desirable. If it is a photosensitive insulating resin, it can be formed by photolithography. After forming the via hole, desirably perform desmearing using a permanganic acid solution as appropriate to roughen the resin surface and clean the inside of the via hole to improve adhesion to the conductor circuit layer 104. Alternatively, a method of cleaning the resin surface and the inside of the via by plasma treatment may be used.

According to the glass circuit board with a built-in capacitor constructed in this way and the method for manufacturing the glass circuit board with a built-in capacitor, the following effects can be obtained. That is, as shown in FIG. 4B, by protecting the upper surface 106 of the conductive circuit layer with the protective layer H, as shown in FIG. It is possible to form a region of the upper surface (surface) 106b of the convex portion of the conductive circuit layer that is not attacked by the etching solution of the layer 102. The upper surface 106b of the convex portion of the conductor circuit layer is not eroded by the etching solution of the seed metal layer 102 than the upper surface 106a of the unprotected conductor circuit, so that a smooth surface can be obtained. In this case, since the capacitor can be formed on a smoother surface, it is possible to reduce short circuits in the capacitor caused by surface roughness and to reduce variations in capacitance caused by variations in the electrode surface area, thereby improving yield. .

Furthermore, as shown in FIG. 4B, by forming the protective layer H to be outside the capacitor formation region Q in a plan view in the stacking direction, the convex upper surface 106b region Q of the conductor circuit layer is made larger than the capacitor formation region. . That is, the capacitor is formed inside the convex step portion. In this case, since the entire surface of the lower electrode layer of the capacitor 109 is the smoother surface 106b of the convex portion of the conductor circuit layer, the yield can be further improved.

Furthermore, as shown in FIG. 4E, by making the thickness of the seed metal layer 113 larger than the step of the convex step portion, the power supply for forming the upper electrode 114 of the capacitor by a semi-additive method can be stabilized. It is possible to do so. In this case, since the step on the surface of the dielectric layer 111, which is an insulator, is overcome by the highly conductive seed metal layer 113, there is no possibility of disconnection due to the step on the surface of the dielectric layer 111 due to the step of the convex step portion, and the yield is improved. The upper electrode 114 can now be formed.

Further, as shown in FIGS. 4F to 4H, the upper electrode 114 is formed inside the convex top surface 106b of the conductive circuit layer in a plan view, thereby forming a capacitor on the convex top surface 106b of the conductive circuit layer. Can be formed inside. In this case, since the entire surface of the lower electrode layer of the capacitor is the smoother surface 106b of the convex portion of the conductive circuit layer, the yield can be further improved.

5A to 5C are explanatory diagrams illustrating a manufacturing process for forming a capacitor according to a comparative example. The manufacturing process shown in FIGS. 5A to 5C is a manufacturing method in which the upper surface 106 of the conductive circuit layer is not protected with the protective layer H. Note that in these figures, the same elements or parts having the same function are denoted by the same reference numerals, and overlapping explanations will be omitted.

FIG. 5A shows the lower electrode 105 constituting the capacitor 109, which is a part of the conductive circuit layer 104, and is in the same state as FIG. 4A. Subsequently, as shown in FIG. 5B, the seed metal layer 102 is removed. In this case, the entire top surface 106 of the conductor circuit layer is eroded by the etching solution for the seed metal layer 102, so that the entire top surface 106 of the conductor circuit layer is in the same state as the top surface 106a of the unprotected conductor circuit in the above-described embodiment. becomes.

Next, a capacitor is formed as shown in FIG. 5C through the same manufacturing method as in FIGS. 4E to 4H described above. In this case, the lower electrode layer side of the capacitor becomes the upper surface 106a of the unprotected conductor circuit which has been eroded by the etching solution, so the capacitor is formed on the rough surface. Short-circuiting of the capacitor due to surface roughness and variation in capacitance due to variation in electrode surface area occur, resulting in a decrease in yield.

As described above, in the glass circuit board with a built-in capacitor according to the present embodiment, reliability can be improved compared to a manufacturing method in which the upper surface 106 of the conductive circuit layer is not protected with the protective layer H, and variations in the electrode surface area can be reduced. Due to the variation in capacitance caused by this, a decrease in yield can be prevented. Furthermore, in the glass circuit board 10 with a built-in capacitor according to the present embodiment, electrical reliability can be improved, and electronic circuits and electronic devices can be made smaller and thinner.

Note that the present invention is not limited to the above-described embodiments, and can be variously modified at the implementation stage without departing from the gist thereof. Moreover, each embodiment may be implemented in combination as appropriate, and in that case, a combined effect can be obtained. Furthermore, the embodiments described above include various inventions, and various inventions can be extracted by combinations selected from the plurality of constituent features disclosed. For example, if a problem can be solved and an effect can be obtained even if some constituent features are deleted from all the constituent features shown in the embodiment, the configuration from which these constituent features are deleted can be extracted as an invention.

According to the present invention, it is possible to manufacture a circuit board with a built-in capacitor having a glass substrate with high reliability. Note that the capacitor built-in glass circuit board can be used for manufacturing semiconductor package substrates, interposers, optical element substrates, or electronic components.
The invention described in the original claims is additionally described below.
[1]
a glass substrate;
An insulating resin layer laminated on this glass substrate and having a conductor circuit layer formed inside;
A capacitor including a part of the conductive circuit layer as a lower electrode, a dielectric layer laminated on the lower electrode, and an upper electrode layer laminated on the dielectric layer,
The lower electrode has a convex step portion on the dielectric layer side in a cross-sectional view in a plane including the stacking direction of the glass substrate and the insulating resin layer, and the surface of the convex step portion is other than the convex step portion. A glass circuit board with a built-in capacitor that has a surface roughness smaller than that of the .
[2]
2. The glass circuit board with a built-in capacitor according to Item 1, wherein the capacitor is provided inside the convex step portion of the conductive circuit layer when viewed in plan in the lamination direction.
[3]
a seed metal layer is formed under the upper electrode layer of the capacitor;
2. The glass circuit board with a built-in capacitor according to item 1, wherein the seed metal layer is thicker than the step of the convex step portion of the lower electrode.
[4]
2. The glass circuit board with a built-in capacitor according to item 1, wherein the glass substrate has a through hole penetrating the front and back surfaces.
[5]
A first step of repeating multiple times a step of forming a conductor circuit layer on the surface of a glass substrate, a step of laminating an insulating resin layer on the glass substrate, and a step of forming a via in the insulating resin layer;
The first step includes forming a capacitor having a dielectric layer and an upper electrode layer on a part of the conductor circuit layer,
The step of forming the capacitor includes forming a protective layer on the conductive circuit layer, removing the seed metal layer of the conductive circuit layer using the protective layer as a mask, and peeling off the protective layer. and a method for manufacturing a glass circuit board with a built-in capacitor, comprising the step of forming a lower electrode or the dielectric layer on the conductor circuit layer.
[6]
6. The method for manufacturing a glass circuit board with a built-in capacitor according to Item 5, wherein the step of forming the protective layer extends to the outside of the capacitor formation region when viewed in plan in the lamination direction of the glass substrate and the insulating resin layer.
[7]
According to item 5, in the step of forming the capacitor, the upper electrode layer is formed inside a conductor circuit layer portion protected by the protective layer in a plan view in a lamination direction of the glass substrate and the insulating resin layer. A method for manufacturing a glass circuit board with a built-in capacitor.
[8]
The step of forming the capacitor includes forming a seed metal layer on top of the dielectric layer,
According to item 5, the step of forming the seed metal layer is carried out so that the thickness of the seed layer is thicker than the step difference between the conductor circuit layer portion protected by the protective layer and the conductor circuit layer portion not protected. A manufacturing method of the glass circuit board with a built-in capacitor described above.
[9]
6. The method for manufacturing a glass circuit board with a built-in capacitor according to Item 5, further comprising the step of forming a through hole penetrating the front and back surfaces of the glass substrate before the first step.

10, 10A...Glass circuit board with built-in capacitor, 100...Glass substrate, 101...Through hole, 102...Seed metal layer, 103...Electrolytic plating layer, 104...Conductor circuit layer, 105...Lower electrode, 106...Top surface of conductor circuit ( surface), 106a...Top surface (surface) of unprotected conductor circuit, 106b...Top surface (surface) of convex portion, 109...Capacitor, 110...Lower adhesion layer, 111...Dielectric layer, 112...Top adhesion layer, 113...Seed Metal layer, 114... Upper electrode, 131... Insulating resin layer, 132... Via hole, 133... Laminated conductor circuit layer, 134... External connection terminal, 135... Solder ball, 136... Semiconductor chip, 137... Chip component.

Claims (5)

a glass substrate;
a conductive circuit layer provided on the glass substrate;
A capacitor including a part of the conductive circuit layer as a lower electrode, and further including a dielectric layer provided on the lower electrode and an upper electrode layer provided on the dielectric layer,
The upper surface of the conductor circuit layer has a first upper surface region and a second upper surface region as the upper surface of a convex portion protruding from the first upper surface region, and the second upper surface region is the upper surface of the lower electrode. ,
A portion of the conductive circuit layer corresponding to the first upper surface region is thinner than a portion corresponding to the second upper surface region,
The dielectric layer is located inside the second upper surface region in a plan view in the stacking direction of the glass substrate and the conductive circuit layer,
The dielectric layer has a shape in which unnecessary portions are removed using the upper electrode layer as a mask . The capacitor further includes a lower adhesion layer provided between the lower electrode and the dielectric layer, the upper electrode layer is made of copper, the lower adhesion layer contains Cu or a Cu alloy, and the lower adhesion layer is made of copper. 2. The glass circuit board with a built-in capacitor according to claim 1, wherein the layer has a shape in which unnecessary portions are removed using the upper electrode layer as a mask. The glass circuit board with a built-in capacitor according to claim 2, wherein the thickness of the lower adhesive layer is 10 nm or more and 1 μm or less. The capacitor built-in glass according to claim 3, wherein the dielectric layer is made of a material selected from the group consisting of alumina, silica, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, and strontium titanate. circuit board. Any one of claims 1 to 4, further comprising a seed metal layer provided between the glass substrate and the conductor circuit layer , the conductor circuit layer being made of copper, and the seed metal layer containing Cu or a Cu alloy. The glass circuit board with a built-in capacitor according to item 1.