JP7206589B2 - Manufacturing method of glass circuit board with built-in capacitor - Google Patents

Description

The present invention relates to a glass circuit board with built-in capacitors and a method of manufacturing a glass circuit board with built-in capacitors, and more particularly to a method capable of realizing high reliability and stable capacitance of capacitors.

2. Description of the Related Art As electronic devices become more sophisticated and smaller, there is an increasing demand for high-density wiring substrates that constitute semiconductor devices. Among them, passive components such as resistors, capacitors, and inductors are also required to be miniaturized in accordance with the miniaturization of circuit wiring. However, there is a limit to further miniaturization only with miniaturization of these passive components and high-density mounting on the substrate surface. Therefore, a technology has been proposed for embedding a passive element in a mounting substrate (see, for example, Patent Document 1). In this technology, miniaturization is possible by embedding passive elements in a multi-layer substrate by forming them by printing, vacuum deposition, or the like. Furthermore, by forming it in a multilayer substrate, it becomes possible to shorten the wiring length, and it is also possible to reduce high-frequency noise.

On the other hand, as the material of the wiring board, an organic material, typically glass epoxy resin, is generally used. In recent years, advances in drilling technology for glass materials have made it possible, for example, to form small-diameter through holes of 100 μm or less in a 300 μm-thick glass substrate at a pitch of 150 μm or less. For this reason, an electronic circuit board using a glass material has attracted attention. A circuit board using a glass material for the core (hereinafter referred to as a "glass circuit board") has a small linear thermal expansion coefficient (CTE) of 2 ppm to 8 ppm and is matched with a silicon chip, so mounting reliability is high. Furthermore, since the flatness is excellent, highly accurate mounting becomes possible. In addition, due to its excellent flatness, it is also excellent in fine wiring formability and high-speed transmission.

Furthermore, application to electronic circuit substrates that take advantage of the transparency, chemical stability, high elasticity, and low cost of glass is being researched. Commercialization of an LC branching filter (duplexer) and the like is expected (see, for example, Patent Document 2). Since it is necessary to form decoupling capacitors, LC circuits, and the like in electronic circuits having glass substrates as cores, there is an increasing demand for built-in capacitors. In order to incorporate a capacitor, it is conceivable to form a thin film capacitor having an MIM structure (Metal Insulator Metal) in which a dielectric is sandwiched between a lower electrode layer and an upper electrode layer.

Japanese Patent Application Laid-Open No. 2000-151114 Japanese Patent No. 5982585

When trying to incorporate a capacitor into the glass circuit board described above, there are the following problems. That is, there is a problem that the capacitance of the capacitor changes depending on the roughness of the surface of the lower electrode layer of the capacitor portion. In particular, if the surface of the lower electrode layer is rough, the unevenness of the surface may induce a short circuit of the capacitor or cause a large change in the capacitance of the capacitor. In addition, variations in the surface roughness of the lower electrode layer within the substrate surface are directly linked to variations in the capacitance of the capacitor. There is a need to.

Therefore, the present invention has been made to solve the above-mentioned problems, and is a capacitor-embedded glass that can realize high reliability and stable capacitance, which are necessary for miniaturization and thinning of electronic circuits and electronic devices. It is an object of the present invention to provide a capacitor-embedded glass substrate manufacturing method capable of manufacturing a circuit board and the capacitor-embedded glass substrate with a high yield.

The invention according to claim 1 of the present invention comprises a step of forming a conductor circuit layer having a lower electrode on a glass substrate; and etching using the protective layer as a mask to form, on the upper surface of the conductor circuit layer, a first upper surface region and a projection as an upper surface protruding from the first upper surface region. forming a second top surface region, wherein the second top surface region is the top surface of the bottom electrode; stripping the protective layer; and forming a dielectric layer on the bottom electrode. and forming a top electrode on the dielectric layer.
The invention according to claim 2 of the present invention further includes the step of forming a lower metal layer on the glass substrate before forming the conductor circuit layer.
According to a third aspect of the present invention, the conductor circuit layer is made of any material selected from the group consisting of copper, nickel, chromium, palladium, gold, rhodium and iridium.

According to a fourth aspect of the present invention, the protective layer extends to the outside of the regions where the dielectric layer and the upper electrode are formed in a plan view in the lamination direction of the glass substrate and the conductor circuit layer. .

According to the fifth aspect of the present invention, the upper electrode is formed inside the second upper surface region when viewed from above in the lamination direction of the glass substrate and the conductor circuit layer.

According to the sixth aspect of the present invention, before forming the upper electrode, on the dielectric layer, the height difference between the second top surface region and the first top surface region is compared with Further comprising forming a top metal layer having a greater thickness.

The invention according to claim 7 of the present invention further includes the step of forming a through-hole penetrating through the front and rear surfaces of the glass substrate before forming the conductor circuit layer.

According to the present invention, by uniformizing the surface roughness of the lower electrode, it is possible to prevent the induction of a short circuit and a large change in the capacitance of the capacitor, thereby realizing high reliability and stabilization of the capacitance. It becomes possible to make the surface roughness uniform by easy processing control.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a vertical cross-sectional view showing a main part of a glass circuit board with a built-in capacitor according to an embodiment of the present invention; FIG. 2 is a plan view of the essential part of the capacitor-embedded glass circuit board viewed in the stacking direction; FIG. 4 is a vertical cross-sectional view showing the same capacitor built-in glass circuit board and a manufacturing process of a manufacturing method of the capacitor built-in glass circuit board. FIG. 4 is a longitudinal sectional view showing a manufacturing process of the same capacitor-embedded glass circuit board; FIG. 4 is a longitudinal sectional view showing a manufacturing process of the same capacitor-embedded glass circuit board; FIG. 4 is a longitudinal sectional view showing a manufacturing process of the same capacitor-embedded glass circuit board; FIG. 4 is a longitudinal sectional view showing a manufacturing process of the same capacitor-embedded glass circuit board; FIG. 4 is a longitudinal sectional view showing a manufacturing process of the same capacitor-embedded glass circuit board; FIG. 3 is a vertical cross-sectional view taken along the line AA in FIG. 2 and showing the manufacturing process of the capacitor forming portion of the glass circuit board with a built-in capacitor in the direction of the arrow; FIG. 4 is a longitudinal sectional view showing a manufacturing process of the same capacitor forming portion; FIG. 4 is a longitudinal sectional view showing a manufacturing process of the same capacitor forming portion; FIG. 4 is a longitudinal sectional view showing a manufacturing process of the same capacitor forming portion; FIG. 4 is a longitudinal sectional view showing a manufacturing process of the same capacitor forming portion; FIG. 4 is a longitudinal sectional view showing a manufacturing process of the same capacitor forming portion; FIG. 4 is a longitudinal sectional view showing a manufacturing process of the same capacitor forming portion; FIG. 4 is a longitudinal sectional view showing a manufacturing process of the same capacitor forming portion; FIG. 4 is a longitudinal sectional view showing a manufacturing process of the same capacitor forming portion; FIG. 4 is a vertical cross-sectional view showing a comparative example of a manufacturing process of a glass circuit board with a built-in capacitor. FIG. 4 is a longitudinal sectional view showing the same manufacturing process; FIG. 4 is a longitudinal sectional view showing the same manufacturing process; FIG. 5 is a vertical cross-sectional view showing a main part of an electronic component according to a modification of the embodiment of the invention;

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a vertical cross-sectional view showing a main part of a capacitor built-in glass circuit board 10 according to a first embodiment of the present invention. Note that P in FIG. 3F indicates a capacitor forming portion.

As shown in FIG. 1, the capacitor built-in glass circuit board 10 has a glass substrate 100 .

A through-hole 101 is formed in the glass substrate 100 so as to extend through the front and back surfaces, and a seed metal layer 102 is formed over the inner wall surface of the through-hole 101 and both surfaces of the glass substrate 100 . A conductive circuit layer 104 is formed on the seed metal layer 102 . A part of the conductor circuit layer 104 becomes the lower electrode 105 that constitutes the capacitor 109 .

An upper surface (surface) 106 of the conductive circuit layer 104 of the capacitor 109 is formed with an upper surface 106a region of the conductive circuit layer and an upper surface (projection surface) 106b region of the lower electrode 105 (see FIG. 4D).

The capacitor 109 basically consists of a lower electrode, a dielectric layer and an upper electrode as shown in FIG. 1, but an adhesion layer or a seed layer may be further provided. Accordingly, in one form, a lower adhesion layer 110, a dielectric layer 111, an upper adhesion layer 112, and a seed metal layer 113 are sequentially formed on the lower electrode 105, as shown in FIG. 4I. An upper electrode 114 is formed on the seed metal layer 113 .

Insulating resin layers 131 are provided on both sides of the glass substrate. A via hole 132 and a laminated conductor circuit layer 133 are formed in the insulating resin layer 131 . Furthermore, a second insulating resin layer and a second conductive circuit layer are formed and laminated as necessary. An external connection terminal 134 is formed at the outermost part. Solder balls 135 are formed at predetermined portions of the external connection terminals 134 .

Next, the material, shape, etc. of each element will be described in detail. The glass substrate 100 is a transparent glass material having optical transparency. There are no particular restrictions on the composition of the glass or the blending ratio of each component contained in the glass, and the method of manufacturing the glass. Examples of glass include alkali-free glass, alkali glass, borosilicate glass, quartz glass, sapphire glass, and photosensitive glass, but any glass material containing silicate as a main component may be used. Furthermore, other so-called glass materials may be used. However, in the semiconductor application according to this embodiment, it is desirable to use alkali-free glass. The thickness of the glass substrate 100 is preferably 1 mm or less, but more preferably 0.1 mm or more and 0.8 mm or less in consideration of the ease of the glass through-hole forming process and the handling during manufacturing.

Examples of the method for manufacturing the glass substrate 100 include a float method, a down-draw method, a fusion method, an up-draw method, and a roll-out method. are not limited to those of The coefficient of linear expansion of the glass is preferably -1 ppm/K or more and 15.0 ppm/K or less. The reason for this is that if the concentration is -1 ppm/K or less, it becomes difficult to select the glass material itself, and it cannot be manufactured at low cost. On the other hand, if it is 15.0 ppm/K or more, the difference in thermal expansion coefficient from the other layers is large, and the reliability is lowered. Moreover, when a silicon chip is mounted on the substrate of this embodiment, the connection reliability with the silicon chip is lowered. The linear expansion coefficient of the glass is more preferably 0.5 ppm/K or more and 8.0 ppm/K or less, and still more preferably 1.0 ppm/K or more and 4.0 ppm/K or less.

Further, a functional film such as an antireflection film or an IR cut filter may be formed in advance on the glass substrate 100 . In addition, functions such as strength imparting, antistatic imparting, coloring, and texture control may be imparted. Examples of these functional films include a hard coat film for imparting strength, an antistatic film for imparting antistatic properties, an optical filter film for coloring, and an antiglare and light scattering film for texture control. Not as long. As a method for forming these functional films, deposition techniques such as vapor deposition, sputtering, and wet methods are used.

The seed metal layer 102 acts as a power supply layer for electroplating in forming wiring in the semi-additive method. The seed metal layer 102 provided directly above the glass substrate 100 and on the inner wall of the through hole 101 is formed by, for example, a sputtering method or a CVD method. Ir, Ru, Pd, Pt, AlSi, _AlSiCu , AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, _Cu3N4 , and Cu alloys alone or in combination are used. Furthermore, an electroless plating layer (electroless copper plating, electroless nickel plating, etc.) is formed thereon.

In the present embodiment, a titanium layer, which has good adhesion to glass, and then a copper layer are sequentially formed by a sputtering method in consideration of electrical properties, ease of manufacture, and cost. The total film thickness of the circuit-forming titanium and copper layers on the glass substrate is preferably 1 μm or less because it is advantageous for fine wiring formation by the semi-additive method. If the thickness is more than 1 μm, it is difficult to form fine wiring with a pitch of 30 μm or less.

The conductive circuit layer 104 is preferably electrolytic copper plating because it is simple, inexpensive, and has good electrical conductivity. Plating, electrolytic rhodium plating, electrolytic iridium plating, or the like may be used.

In the capacitor 109 , the lower adhesion layer 110 has a function of improving the adhesion between the lower electrode 105 and the dielectric layer 111 , and the upper adhesion layer 112 improves the adhesion between the dielectric layer 111 and the seed metal layer 113 . It has the ability to improve The material of the lower adhesion layer 110 and the upper adhesion layer 112 is Ti, for example. In addition, for example, Cu, Ni, Al, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, Cu alloys alone or in combination may be used. Ti is superior in terms of adhesion, electrical conductivity, ease of manufacture, and cost.

It is desirable that the thickness of the lower adhesion layer 110 and the upper adhesion layer 112 is, for example, 10 nm or more and 1 μm or less. If it is less than 10 nm, the adhesion strength may be insufficient. If the thickness exceeds 1 μm, in the manufacturing process to be described later, not only does the film formation take too long to impede mass production, but there is a possibility that the process of removing unnecessary portions will take even more time. The thicknesses of the lower adhesion layer 110 and the upper adhesion layer 112 are more preferably 10 nm or more and 500 nm or less. Although the thicknesses of the lower adhesion layer 110 and the upper adhesion layer 112 may be different, it is preferable that they have the same thickness in order to simplify the structure. Further, if the adhesion between the lower electrode 105 and the dielectric layer 111 is sufficient, the lower adhesion layer 110 may be omitted. If the adhesion between the dielectric layer 111 and the seed metal layer 113 is sufficient, the upper adhesion layer 112 may be omitted.

The dielectric layer 111 can be selected from alumina, silica, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, and strontium titanate from the viewpoint of insulation and dielectric constant. The thickness of the dielectric layer 111 is desirably 10 nm or more and 5 μm or less. If the thickness of the dielectric layer 111 is 10 nm or less, the insulating property cannot be maintained and the function as a capacitor is not exhibited. If the thickness of the dielectric layer 111 is 5 .mu.m or more, it takes too long to form the film, which not only impairs mass productivity, but also takes more time in the process of removing unnecessary portions. More preferably, it is 50 nm or more and 1 μm or less.

The seed metal layer 113 is a power supply layer for forming the upper electrode 114 of the capacitor 109 by a semi-additive method. The seed metal layer 113 is made of, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, Cu alloy alone or in combination. can do. Copper is more preferable because copper is easier to remove by etching later. The thickness of the seed metal layer 113 is desirably 10 nm or more and 5 μm or less. If the thickness of the seed metal layer 113 is less than 100 nm, there is a possibility that poor conduction will occur in the subsequent electroplating process. If the thickness of the seed metal layer 113 exceeds 5 μm, it will take a long time to remove it by etching. More preferably, the thickness of the seed metal layer 113 is 100 nm or more and 500 nm or less.

The upper electrode 114 is an electrolytic plating layer. Electrolytic copper plating is desirable because it is simple, inexpensive, and has good electrical conductivity. Electrolytic iridium plating or the like may be used.

The thickness of the upper electrode 114 (thickness of electrolytic copper plating) is desirably 3 μm or more and 30 μm or less. If the thickness is less than 3 μm, the circuit may disappear depending on the etching process after the upper electrode 114 is formed. Furthermore, there is a danger that the connection reliability and electrical conductivity of the circuit will be lowered. If the electrolytic copper plating thickness exceeds 30 μm, it is necessary to form a resist layer with a thickness of 30 μm or more, which increases manufacturing costs. Furthermore, since the resist resolution deteriorates, it becomes difficult to form fine wiring with a pitch of 30 μm or less. More preferably, it is 5 μm or more and 25 μm or less. More desirably, the thickness is 10 μm or more and 20 μm or less.

After that, as shown in FIG. 1, after forming a capacitor 109 using a part of the conductor circuit layer 104 directly above the glass as a lower electrode, an insulating resin layer 131 and a via hole 132 are formed. After that, multilayer wiring is formed by repeatedly forming the laminated conductor circuit layer 133 and the insulating resin layer 131 . The conductor circuit layer 104 and the laminated conductor circuit layer 133 can be formed using a known semi-additive method or subtractive method. Furthermore, after forming the laminated conductor circuit layer 133, the external connection terminals 134 are formed. Further, solder balls 135 are formed on the external connection terminals 134 .

As shown in FIG. 1, the circuit board according to the present embodiment may have laminated conductor circuit layers 133, external connection terminals 134, and solder balls 135 on one side or both sides.

Note that the insulating resin layer 131 may be a solder resist as long as it is the outermost layer, and is not limited to this embodiment. Also, the external connection terminals 134 may be subjected to surface treatment. Bondability with the solder ball 135 is improved by surface treatment.

The surface treatment may be tin or tin alloy plating film, electroless Ni--P/electroless Pd--P/Au plating film, electroless Ni--P/Au plating film, or the like. Alternatively, pre-solder treatment or organic film treatment such as OSP (Organic Solderability Preservative) may be applied. The solder balls 135 can be formed by a screen printing method, a solder ball transfer mounting method, an electroplating method, or the like. The composition of the solder ball can be one or a mixture of tin, silver, copper, bismuth, lead, zinc, indium, antimony, etc., and the mixing ratio of these metal materials is not critical. Wire bonding pads may be provided instead of solder.

FIG. 2 is a plan view of the capacitor-embedded glass circuit substrate, viewed in the stacking direction, around the capacitors. This figure shows the lower electrode 105 in the vicinity of the region forming the capacitor 109 in the conductor circuit layer 104 . Although it will be described later, the capacitor formation process will be described with reference to a cross-sectional view taken along line AA in FIG. 2 (see FIG. 4).

Next, a method for manufacturing the capacitor built-in glass circuit board 10 will be described. 3A to 3F are vertical cross-sectional views showing manufacturing steps of a glass circuit board with built-in capacitors constituting the glass circuit board with built-in capacitors 10. FIG.

As shown in FIG. 3A, a glass substrate 100 is prepared. Subsequently, through holes 101 are formed in the glass substrate 100 as shown in FIG. 3B. The cross-sectional shape and diameter of the through-hole 101 are not limited by this embodiment. For example, the shape may be such that the diameter of the central portion is narrower than the top and bottom diameters of the through hole, or the shape may be such that the bottom diameter is smaller than the top diameter. Further, the shape may be such that the diameter of the central portion is larger than the top and bottom diameters of the through hole. Known methods for forming through-holes include laser processing, electric discharge processing, sandblast processing when using a photosensitive resist material, dry etching, and chemical etching processing using hydrofluoric acid or the like. Furthermore, it is possible to produce a glass core using photosensitive glass. Laser machining and electric discharge machining are preferable because they are simple and have good throughput. Lasers that can be used can be selected from CO2 lasers, UV lasers, picosecond lasers, femtosecond lasers, and the like.

Subsequently, as shown in FIG. 3C, a seed metal layer 102 is formed on the surface of the glass substrate 100 having the through holes 101 and inside the through holes. The seed metal layer 102 acts as a power supply layer for electroplating in forming wiring in the semi-additive method.

In the step of forming the seed metal layer 102, after forming titanium and copper layers on the glass substrate 100, an electroless plated layer is formed. If only the titanium and copper layers are used, the metal film cannot be formed entirely inside the through-hole 101, and the connection reliability of the through-hole 101 is deteriorated. According to this embodiment, the connection reliability of the through-hole 101 can be improved by reinforcing the metal layer in the through-hole 101 by the electroless plating method. The electroless plating layer may be electroless copper plating or electroless nickel plating. Electroless nickel plating is used because it has good adhesion to the glass, titanium, or copper layer. When the nickel plating layer is thick, not only is it difficult to form fine wiring, but also adhesion is lowered due to increased film stress. Therefore, the electroless nickel plating thickness is preferably 1 μm or less. Moreover, it is more preferably 0.5 μm or less, and still more preferably 0.3 μm or less. In addition, the electroless nickel plating film may contain phosphorus, which is a co-deposit derived from the reducing agent, and sulfur, lead, bismuth, and the like contained in the electroless nickel plating solution. Through the above steps, a substrate (FIG. 3C) is obtained in which a seed metal layer 102 is formed on a glass substrate having through holes 101 formed therein.

Subsequently, as shown in FIG. 3D, a photoresist pattern PR is formed. A method of forming the photoresist pattern PR will be described. First, a photoresist layer is formed on the entire surface of the seed metal layer 102 . The photoresist layer to be formed includes a negative dry film resist, a negative liquid resist, and a positive liquid resist, but the negative photoresist is preferable because the formation of the resist layer is simple and inexpensive. Examples of methods for forming a resist layer include a roll lamination method and a vacuum lamination method in the case of a negative dry film resist. In the case of a liquid negative or positive resist, it can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. The method of forming these resist layers is not limited by this embodiment.

Subsequently, a pattern for forming a desired conductor circuit layer 104 is formed on the photoresist layer by a known photolithography method. That is, the resist pattern is patterned by exposing and developing after aligning so that the portion where the conductor circuit layer 104 is to be formed later is exposed. Although the thickness of the resist layer depends on the thickness of the conductive circuit layer, it is preferably 5 μm or more and 25 μm or less. If the thickness is less than 5 μm, the electroplated layer, which will be the conductive circuit layer, cannot be increased to 5 μm or more, and the connection reliability of the circuit may be lowered. If the thickness is more than 25 μm, it becomes difficult to form fine wiring with a pitch of 30 μm or less. Thus, as shown in FIG. 3D, a glass substrate having a photoresist pattern PR formed thereon is obtained.

Subsequently, as shown in FIG. 3E, an electrolytic plated layer 103 that will form the conductor circuit layer 104 is formed by an electrolytic plating method. Electrolytic plating methods include electrolytic nickel plating, electrolytic copper plating, electrolytic chrome plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating. It is desirable because of its good electrical conductivity. The thickness of the electrolytic copper plating is desirably 3 μm or more and 30 μm or less. The reason for this is that if the thickness is 3 μm or less, there is a risk that the circuit will disappear depending on the subsequent etching treatment, and there is a risk that the connection reliability and electrical conductivity of the circuit will be lowered. On the other hand, when the electrolytic copper plating thickness is 30 μm or more, it is necessary to form a resist layer with a thickness of 30 μm or more, which increases manufacturing costs. Furthermore, since the resist resolution deteriorates, it becomes difficult to form fine wiring with a pitch of 30 μm or less. It is more preferably 5 μm or more and 25 μm or less, and still more preferably 10 μm or more and 20 μm or less.

Subsequently, as shown in FIG. 3F, the photoresist pattern PR that is no longer necessary after the wiring is formed by electrolytic plating is removed, and only the conductive circuit layer 104 is arranged on the glass substrate 100, and the seed metal layer 102 is exposed. . The method of removing the resist is not limited to this embodiment, and for example, an alkaline aqueous solution can be used to remove the resist.

4A to 4I are vertical cross-sectional views showing enlarged portions of the chain double-dashed line P in FIG. 3F. Although these figures show an example of capacitor formation on the conductor circuit layer 104 formed on the glass substrate 100, the formation of the capacitor 109 directly above the conductor circuit layer 104 is not limited.

FIG. 4A shows a bottom electrode 105 forming a capacitor 109 that is part of the conductive circuit layer 104. FIG. Subsequently, as shown in FIG. 4B, a protective layer H is formed on the lower electrode 105 to protect the upper surface (surface) 106 of the conductive circuit layer. The photoresist pattern PR described above can be applied as the protective layer H, and can be formed by the same method as described above. The formation area of the protective layer is preferably slightly larger than the subsequent capacitor formation area.

A conductive circuit layer 104 is then formed by removing the exposed portions of the seed metal layer 102 previously shown in FIG. 3F and electrically breaking the circuit. In the step of removing the exposed seed layer, the conductive circuit layer 104 is also etched at the same time. At this time, as shown in FIG. 4C, the portion of the conductor circuit layer protected by the protective layer H is not etched, and a convex stepped portion is formed. The method of removing the seed layer is not limited by this embodiment, but a method of sequentially removing the electroless Ni layer, the copper layer and the titanium layer by chemical etching can be used. The type of etchant is appropriately selected depending on the type of metal to be removed, and is not limited by this embodiment.

Subsequently, as shown in FIG. 4D, the unnecessary protective layer H is removed. The removal of the protective layer H can be carried out using a known alkaline aqueous solution in the same manner as the photoresist pattern PR described above. In this case, since the conductive circuit layer 104 was protected from the etchant, the region where the protective layer H was formed was not etched, while only the non-protected portion of the conductive circuit layer was etched, and the conductive circuit layer 104 was etched. A convex step is formed. This convex portion becomes a region where the capacitor 109 is formed as the lower electrode 105 .

Subsequently, as shown in FIG. 4E, a lower adhesion layer 110, a dielectric layer 111, an upper adhesion layer 112, and a seed metal layer 113 are sequentially deposited over the entire surface of the lower electrode 105. Then, as shown in FIG. Methods for forming the above layers include a vacuum deposition method, a sputtering method, an ion plating method, an MBE method, a laser abrasion method, and a CVD method, but are not limited by this embodiment.

The lower adhesion layer 110 under the dielectric layer 111 has a function of improving adhesion between the dielectric layer 111 and the conductor circuit layer 104 . Further, if the adhesion between the dielectric layer 111 and the conductive circuit layer 104 is sufficient, the lower adhesion layer 110 may be omitted. The seed metal layer 113 functions as a power supply layer for forming the upper electrode 114 of the capacitor 109 by a semi-additive method.

Subsequently, a photoresist pattern PS is formed as shown in FIG. 4F. The photoresist pattern PS can be formed by the same method as the photoresist pattern PR described above. In this case, the opening region of the photoresist pattern PS is formed so as to be inside the convex upper surface 106b of the conductor circuit layer, and is also formed so as to be inside in plan view in the stacking direction (see FIG. 2).

Subsequently, as shown in FIG. 4G, the seed metal layer 113 is used to form the upper electrode 114 by electroplating.

As described above, the photoresist pattern PS has an opening formed inside the upper surface 106b of the conductor circuit layer protrusion, so that the upper electrode 114 is formed only inside the upper surface 106b of the protrusion 106b of the conductor circuit layer.

Subsequently, as shown in FIG. 4H, the photoresist pattern PS is removed. The removal of the photoresist pattern PS can be carried out using a known method of alkaline aqueous solution.

Subsequently, as shown in FIG. 4I, unnecessary portions of the seed metal layer 113, the upper adhesion layer 112, the dielectric layer 111, and the lower adhesion layer 110 are removed using the upper electrode 114 as a mask. As a method for removing the seed metal layer 113, the upper adhesion layer 112, the dielectric layer 111, and the lower adhesion layer 110, a known method such as a chemical etching method or a dry etching method can be used, and a different method can be used for each layer. Also, the same method may be used for all layers, and is not limited by this embodiment. As described above, since the upper electrode 114 is formed inside the upper surface 106b of the convex portion of the conductor circuit layer, when the unnecessary portion is removed using the upper electrode 114 as a mask, the dielectric layer 111 is formed on the upper surface of the convex portion of the conductor circuit layer. It is formed only inside 106b. The capacitor 109 is formed by the above steps.

After that, as shown in FIG. 1, after forming a capacitor 109 on the wiring circuit directly on the glass, an insulating resin layer 131 and a via hole 132 are formed. After that, multilayer wiring is formed by repeatedly forming the laminated conductor circuit layer 133 and the insulating resin layer 131 . The conductor circuit layer 104 and the laminated conductor circuit layer 133 can be formed using a known semi-additive method or subtractive method. Furthermore, after forming the laminated conductor circuit layer 133, the external connection terminals 134 are formed. Further, solder balls 135 are formed on the external connection terminals 134 .

The circuit board according to this embodiment may have laminated conductor circuit layers 133, external connection terminals 134, and solder balls 135 on one side as shown in FIG. Also good. Furthermore, a semiconductor chip 136 and a chip component 137 may be mounted.

A method for forming a multilayer wiring will be described below. A known method can be used as a method for forming the multilayer wiring. That is, examples that can be used as the insulating resin layer 131 of the multilayer wiring layer include epoxy resin, polyimide, maleimide resin, polyethylene terephthalate, polyphenylene oxide, liquid crystal polymer and composite materials thereof, photosensitive polyimide resin, and photosensitive polybenzoxazole. , a photosensitive acrylic-epoxy resin may be used. The method of forming the insulating resin is not limited by this embodiment, but vacuum lamination, vacuum press, and roll lamination can be used as long as it is in the form of a sheet. If it is liquid, it can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating.

The thickness of the insulating resin layer 131 is preferably 5 μm or more and 50 μm or less. If the thickness is 50 μm or more, it becomes difficult to reduce the diameter of the via hole 132 that can be formed in the insulating resin layer 131, which is disadvantageous in increasing the wiring density. becomes.

Laser processing can be used to form the via holes 132 in the multi-layer wiring if the non-photosensitive insulating resin is used. Examples of lasers include CO2 lasers, UV lasers, picosecond lasers, femtosecond lasers, etc., but UV lasers and CO2 lasers are preferred because they are simple and easy to use. If it is a photosensitive insulating resin, it can be formed by a photolithographic method. After forming the via hole, desmearing with a permanganic acid solution is preferably performed to roughen the surface of the resin and clean the inside of the via hole to improve the adhesion to the conductive circuit layer 104 . Alternatively, a method of cleaning the resin surface and the inside of the via by plasma treatment may be performed.

According to the glass circuit board with a built-in capacitor and the method for manufacturing the glass circuit board with a built-in capacitor thus configured, the following effects can be obtained. That is, as shown in FIG. 4B, by protecting the upper surface 106 of the conductive circuit layer with the protective layer H, as shown in FIG. It is possible to form a region of the convex upper surface (surface) 106b of the conductive circuit layer which is not affected by the etchant of the layer 102 . Compared with the upper surface 106a of the non-protected conductor circuit, the upper surface 106b of the convex portion of the conductor circuit layer is not damaged by the etchant for the seed metal layer 102, so a smooth surface can be obtained. In this case, since the capacitor can be formed on a smoother surface, it is possible to reduce short-circuiting of the capacitor due to surface roughness and to reduce variation in capacitance due to variation in electrode surface area, thereby improving yield. .

Further, as shown in FIG. 4B, by forming the protective layer H so as to be outside the capacitor formation region Q in plan view in the stacking direction, the region Q of the upper surface of the convex portion 106b of the conductor circuit layer is larger than the capacitor formation region. . That is, the capacitor is formed inside the convex stepped portion. In this case, since the entire surface of the lower electrode layer of the capacitor 109 is the upper surface 106b of the convex portion of the conductive circuit layer, which is a smoother surface, the yield can be further improved.

Further, as shown in FIG. 4E, by making the thickness of the seed metal layer 113 larger than the step of the convex stepped portion, the power supply for forming the upper electrode 114 of the capacitor by the semi-additive method is stabilized. It is possible to do In this case, since the step on the surface of the dielectric layer 111, which is an insulator, is overcome by the highly conductive seed metal layer 113, there is no possibility of disconnection due to the step on the surface of the dielectric layer 111 due to the step of the convex stepped portion, resulting in a high yield. An upper electrode 114 can be formed.

In addition, as shown in FIGS. 4F and 4H, the upper electrode 114 is formed inside the upper surface 106b of the conductor-circuit layer protrusion in plan view, thereby forming a capacitor on the upper surface 106b of the protrusion 106b of the conductor-circuit layer. Can be formed inside. In this case, since the entire surface of the lower electrode layer of the capacitor is the upper surface 106b of the convex portion of the conductor circuit layer, which is a smoother surface, the yield can be further improved.

5A to 5C are explanatory diagrams explaining manufacturing steps for forming a capacitor according to a comparative example. 5A to 5C is a manufacturing method in which the upper surface 106 of the conductive circuit layer is not protected by the protective layer H. FIG. In these drawings, the same reference numerals are used for the same elements or portions having the same functions, and overlapping descriptions are omitted.

FIG. 5A shows a lower electrode 105 forming a capacitor 109 which is part of the conductor circuit layer 104, and is in the same state as in FIG. 4A. Subsequently, as shown in FIG. 5B, the seed metal layer 102 is removed. In this case, since the entire upper surface 106 of the conductor circuit layer is eroded by the etchant for the seed metal layer 102, the entire upper surface 106 of the conductor circuit layer is in the same state as the upper surface 106a of the unprotected portion conductor circuit in the above-described embodiment. becomes.

Then, a capacitor is formed as shown in FIG. 5C through the same manufacturing method as in FIGS. 4E to 4H. In this case, since the lower electrode layer side of the capacitor becomes the upper surface 106a of the non-protected portion conductor circuit which is corroded by the etchant, the capacitor is formed on the roughened surface. Short-circuiting of capacitors due to surface roughening and variation in capacitance due to variation in electrode surface area occur, leading to a decrease in yield.

As described above, in the glass circuit substrate with a built-in capacitor according to the present embodiment, the reliability can be improved compared to the manufacturing method in which the upper surface 106 of the conductor circuit layer is not protected by the protective layer H, and variations in electrode surface area can be prevented. Since the resulting capacitance variation occurs, it is possible to prevent a decrease in yield. Also, in the glass circuit substrate 10 with a built-in capacitor according to the present embodiment, electrical reliability can be improved, and electronic circuits and electronic devices can be made smaller and thinner.

It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made in the implementation stage without departing from the scope of the invention. Further, each embodiment may be implemented in combination as appropriate, in which case the combined effect can be obtained. Furthermore, various inventions are included in the above embodiments, and various inventions can be extracted by combinations selected from a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiments, if the problem can be solved and effects can be obtained, the configuration with the constituent elements deleted can be extracted as an invention.

According to the present invention, it is possible to manufacture a capacitor built-in circuit board having a glass substrate with high reliability. The capacitor-embedded glass circuit substrate can be used for manufacturing semiconductor package substrates, interposers, substrates for optical elements, or for manufacturing electronic components.
The description equivalent to the invention described in the original claims of the present application is added below.
[1]
a glass substrate;
an insulating resin layer laminated on the glass substrate and having a conductive circuit layer formed therein;
a capacitor having a dielectric layer formed by laminating a part of the conductor circuit layer as a lower electrode, a dielectric layer laminated on the lower electrode, and an upper electrode layer laminated on the dielectric layer;
The lower electrode has a convex stepped portion on the dielectric layer side in a cross-sectional view in a plane including the stacking direction of the glass substrate and the insulating resin layer, and the surface of the convex stepped portion is other than the convex stepped portion. A capacitor-embedded glass circuit substrate having a surface roughness smaller than that of the surface of the capacitor.
[2]
The capacitor-embedded glass circuit board according to [1], wherein the capacitor is provided inside the convex stepped portion of the conductor circuit layer when viewed from above in the stacking direction.
[3]
a seed metal layer is formed under the upper electrode layer of the capacitor;
The capacitor-embedded glass circuit board according to [1], wherein the seed metal layer is thicker than the step of the convex step portion of the lower electrode.
[4]
The capacitor-embedded glass circuit board according to [1], wherein the glass substrate is formed with a through hole penetrating through the front and back surfaces.
[5]
a first step of repeating a step of forming a conductive circuit layer on the surface of a glass substrate, a step of laminating an insulating resin layer on the glass substrate, and a step of forming vias in the insulating resin layer a plurality of times;
The first step includes forming a capacitor having a dielectric layer and an upper electrode layer on a portion of the conductor circuit layer,
The step of forming the capacitor includes forming a protective layer on the conductive circuit layer, removing a seed metal layer of the conductive circuit layer using the protective layer as a mask, and peeling off the protective layer. and a method of manufacturing a glass circuit substrate with a built-in capacitor, comprising a step of forming a lower electrode or the dielectric layer on the conductive circuit layer.
[6]
The method for manufacturing a capacitor-embedded glass circuit board according to [5], wherein the step of forming the protective layer includes forming the protective layer up to the outside of the capacitor forming region in a plan view in the lamination direction of the glass substrate and the insulating resin layer. .
[7]
The step of forming the capacitor includes forming the upper electrode layer inside the conductive circuit layer portion protected by the protective layer in plan view in a lamination direction of the glass substrate and the insulating resin layer [5]. A method for manufacturing the glass circuit board with a built-in capacitor as described above.
[8]
forming the capacitor comprises forming a seed metal layer on top of the dielectric layer;
The step of forming the seed metal layer is performed so that the thickness of the seed layer is thicker than the step between the conductor circuit layer portion protected by the protective layer and the unprotected conductor circuit layer portion [5]. 3. A method for manufacturing the capacitor-embedded glass circuit board according to 1.
[9]
The method for manufacturing a glass circuit board with a built-in capacitor according to [5], further comprising, prior to the first step, forming a through hole penetrating through the front and back surfaces of the glass substrate.

10, 10A... glass circuit substrate with built-in capacitor, 100... glass substrate, 101... through hole, 102... seed metal layer, 103... electroplating layer, 104... conductor circuit layer, 105... lower electrode, 106... upper surface of conductor circuit ( Surface), 106a... Upper surface (surface) of non-protected portion conductor circuit, 106b... Upper surface of convex portion (surface), 109... Capacitor, 110... Lower adhesive layer, 111... Dielectric layer, 112... Upper adhesive layer, 113... Seed Metal layer 114 Upper electrode 131 Insulating resin layer 132 Via hole 133 Laminated conductor circuit layer 134 External connection terminal 135 Solder ball 136 Semiconductor chip 137 Chip component.

Claims (7)

forming a conductive circuit layer having a lower electrode on a glass substrate;
forming a protective layer on the conductor circuit layer so that the upper surface of the conductor circuit layer is partially exposed;
A step of forming, on the upper surface of the conductive circuit layer, a first upper surface region and a second upper surface region as an upper surface of a projection protruding from the first upper surface region by etching using the protective layer as a mask. wherein the second top surface region is the top surface of the bottom electrode;
peeling off the protective layer;
forming a dielectric layer on the bottom electrode;
forming a top electrode on the dielectric layer;
A method for manufacturing a glass circuit board with a built-in capacitor. 2. The method of claim 1 , further comprising forming a lower metal layer on the glass substrate before forming the conductive circuit layer. 3. The manufacturing of the capacitor built-in glass circuit board according to claim 1 , wherein the conductor circuit layer is made of any material selected from the group consisting of copper, nickel, chromium, palladium, gold, rhodium and iridium. Method. 4. The protective layer according to any one of claims 1 to 3 , wherein the protective layer is formed up to the outside of the formation regions of the dielectric layer and the upper electrode in a plan view in a lamination direction of the glass substrate and the conductive circuit layer. 10. A method for manufacturing the capacitor-embedded glass circuit board according to the above item. 5. The glass circuit with a built - in capacitor according to claim 1 , wherein the upper electrode is formed inside the second upper surface region in plan view in a lamination direction of the glass substrate and the conductor circuit layer. Substrate manufacturing method. Forming a top metal layer on the dielectric layer prior to forming the top electrode, the top metal layer having a thickness greater than the height difference between the second top region and the first top region. 6. The method for manufacturing a capacitor built-in glass circuit substrate according to any one of claims 1 to 5 , further comprising steps. 7. The manufacturing of the glass circuit board with built-in capacitor according to claim 1 , further comprising the step of forming through-holes penetrating through the front and rear surfaces of the glass substrate before forming the conductor circuit layer. Method.

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