JP2011129665A - Method of manufacturing laminated wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem wherein the formation of fine irregularities for increasing adhesion strength causes a disadvantage to capacitor characteristics and reliability when a wiring layer of a laminated wiring board is utilized as a capacitor lower electrode. <P>SOLUTION: In the method of manufacturing a laminated wiring board, an MIM structure covering a part of a wiring layer (14) is formed, and fine irregularities are formed on a wiring layer surface not being covered therewith. An insulating substrate 19a is stuck on the fine irregularities, and an opening is formed in the insulating substrate 19a in a capacitive element part to form electrode extraction wiring (24) of a capacitive element in the opening. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a laminated wiring board in which a wiring layer and another insulating board are alternately and repeatedly laminated one or more times on one or both sides of an insulating substrate, and a capacitive element is included therein.

Technological development for forming a parallel plate type capacitive element inside a multilayer wiring board such as a printed wiring board has been activated.
In many types of multilayer wiring boards, multilayer wiring boards are formed by alternately forming wiring layers and insulating layers on both sides of a core substrate.
In addition to improving general capacitive elements such as increasing capacitance, increasing accuracy, and reducing variation in capacitance values, eliminating the disadvantages associated with the inclusion in a multilayer wiring board is an issue to be addressed. It is done.

A dielectric film is formed by using an inclined surface of an insulating base material, thereby increasing the capacitance value per unit occupation area (for example, Patent Document 1).
Further, as a contrivance of the base surface for forming a thin uniform capacitor dielectric film, a technique for flattening the upper surface of the insulating layer and the wiring layer (lower electrode) on which the capacitor dielectric film is formed is known (for example, a patent) Reference 2).

JP 2008-159686 A JP 2007-19530 A

In the case of pasting an insulating substrate for multilayering in a multilayer wiring board, conductive wiring is arranged on the pasting surface with a considerable area occupancy. Need to increase. Therefore, a process for increasing the mechanical coupling strength is known as a technique for forming a fine unevenness on the surface of the wiring layer on the insulating substrate on the side where the wiring layer is formed, thereby providing a so-called anchor effect.
As a typical example, so-called blackening treatment and reduction treatment are known. In the blackening treatment, the surface of copper as wiring is oxidized to form fine needle crystals of copper oxide. The reduction treatment imparts acid resistance by performing a reduction treatment after the oxidation treatment. As a result, needle-like irregularities are formed on the surface of the copper wiring to provide an anchor effect, thereby improving the adhesion between the insulating substrates.
The technology for forming such fine irregularities is essential for the multilayer wiring board in the sense of preventing peeling at the interface between the core substrate and the insulating layer (generally a resin layer).

However, if there are needle-like irregularities on the surface of the lower electrode where the dielectric film of the capacitive element is formed, the characteristics and reliability of the capacitive element, such as an increase in leakage current due to electric field concentration, are greatly reduced.
As the dielectric film is made thinner in order to increase the capacity of the capacitive element, the increase in leakage current due to the needle-like unevenness becomes more remarkable.

In the above-mentioned Patent Document 2, there is a description about blackening processing and reduction processing. The problem here is that the conductive pattern (lower electrode) is covered with a thermosetting insulating material and then polished to flatten the insulating material surface where the upper surface of the lower electrode of the capacitor element is exposed, and then blacken the flattened surface. Processing and reduction processing.
This treatment is inevitably necessary for preventing peeling because the substrate resin is pasted thereon. However, in Patent Document 2, the surface is simultaneously the formation surface of the capacitor dielectric film. Can't escape.

Moreover, in the said patent document 1, the copper foil previously formed in the insulated substrate is opened by laser processing etc., the desired area | region of an insulated substrate is opened by the etching by chemical treatment etc., or laser machining, and copper foil is exposed. This surface is used as the lower electrode of the capacitive element. Thereafter, a dielectric film and an upper electrode are formed to form a capacitive element.
The exposed surface of the copper foil has fine irregularities formed in order to improve the adhesion to the insulating substrate 121, and is unsuitable as a lower electrode of a capacitor element because of an increase in leakage.

As disclosed in Patent Document 2, it is effective to improve the accuracy of the capacitance value to define the effective area of the capacitive element by the electrode area exposed by the opening in laser processing.
However, the exposed copper surface is affected by laser processing, or unevenness occurs on the electrode surface of the opening by performing laser processing or scanning a plurality of times to open a large diameter. Both of these are unsuitable for the lower electrode of the capacitive element.

  The present invention provides a multilayer structure for forming a structure in which the formation of fine irregularities that increase adhesion strength and the processing of an insulating substrate do not adversely affect capacitor characteristics and reliability when the wiring layer of the multilayer wiring board is used as a capacitor lower electrode. A method for manufacturing a wiring board is provided.

The method for manufacturing a multilayer wiring board according to the first aspect of the present invention includes the following steps.
(A) Capacitance that covers at least a part of the upper surface of the wiring layer before bonding the insulating substrate in the formation of the laminated substrate structure in which the wiring layer and another insulating substrate are alternately stacked and bonded to the insulating substrate at least once. Forming an element stack;
(B) A step of forming fine irregularities on the surface of the wiring layer that is not covered with the capacitive element laminate to ensure adhesion at the time of bonding.
(C) A step of attaching an insulating substrate to the capacitive element laminate.
(D) forming a first opening in which a part of the upper surface of the capacitive element stack is exposed and a second opening in which a part of the upper surface of the wiring layer is exposed in the bonded insulating substrate.
(E) A step of forming an electrode lead-out wiring of the capacitive element in the first and second openings.

In this manufacturing method, since the fine unevenness forming process is performed after the capacitor element is formed, the capacitor dielectric film is protected by the upper electrode, and there is no fear of an increase in leakage.
On the other hand, when the material is copper, fine irregularities are formed not only on the surface of the wiring layer but also on the upper electrode of the capacitive element, so that it is easy to ensure adhesion.

The method for manufacturing a multilayer wiring board according to the second aspect of the present invention includes the following steps.
(A) Protection for covering at least a part of the upper surface of the wiring layer before bonding the insulating substrate in the formation of the laminated substrate structure in which the wiring layer and another insulating substrate are alternately stacked and bonded to the insulating substrate at least once. Forming a conductive layer;
(B) A step of forming fine irregularities on the surface of the wiring layer that is not covered with the protective conductive layer in order to ensure adhesion at the time of bonding.
(C) A step of attaching an insulating substrate to the protective conductive layer side.
(D) forming a first opening in which a part of the upper surface of the protective conductive layer is exposed and a second opening in which a part of the upper surface of the wiring layer is exposed in the bonded insulating substrate;
(E) A step of selectively removing a part of the protective conductive layer exposed in the first opening from the underlying wiring layer.
(F) A step of selectively forming a capacitor dielectric film on at least the bottom surface of the opening in the first opening.
(G) forming an electrode lead-out wiring of the capacitive element in the first and second openings.

  In this manufacturing method, the protective conductive layer is removed, but fine unevenness processing is performed before the removal, so that there is no concern about an increase in leakage. Since the surface can be selectively removed from the base during the removal, it is difficult to cause surface roughness.

  According to the present invention, when a wiring layer of a multilayer wiring board is used as a capacitor lower electrode, a structure is formed in which formation of fine irregularities that increase adhesion strength and processing of an insulating substrate do not adversely affect capacitor characteristics and reliability. A method for manufacturing a multilayer wiring board can be provided.

It is a schematic sectional drawing in the middle of formation of the printed wiring board containing the via | veer in connection with 1st Embodiment. It is sectional drawing in the middle of manufacture following FIG. It is sectional drawing in the middle of manufacture following FIG. It is sectional drawing of the laminated wiring board containing a capacitive element structure. It is sectional drawing in the middle of manufacture for demonstrating the manufacturing method of 1st Embodiment. It is sectional drawing in the middle of manufacture following FIG. It is sectional drawing in the middle of manufacture following FIG. It is sectional drawing in the middle of manufacture following FIG. It is sectional drawing in the middle of manufacture for demonstrating the manufacturing method of 2nd Embodiment. FIG. 10 is a cross-sectional view during manufacturing subsequent to FIG. 9. It is sectional drawing in the middle of manufacture following FIG. It is sectional drawing in the middle of manufacture following FIG. It is sectional drawing in the middle of manufacture following FIG.

Embodiments of the present invention will be described with reference to the drawings in the following order, taking a printed wiring board as an example.
1. First Embodiment: An embodiment in which fine unevenness processing is performed after covering a formation surface of a capacitor element with a protective conductive layer.
2. Second Embodiment: An embodiment in which fine unevenness processing is performed after forming a capacitive element laminate.

<1. First Embodiment>
[Schematic manufacturing method of multilayer wiring board without capacitor details]
The feature of the present invention lies in the details of the capacitive element, particularly the lower electrode structure using the wiring layer of the multilayer wiring board. However, since the overall formation method of the multilayer wiring substrate does not appear in the drawings (to be described later) of the description, an outline of the premise substrate formation method will be described first with reference to FIGS.
The laminated wiring board to which the present invention is applied has a broad concept including a flexible board having a laminated structure, and hereinafter, a printed wiring board is assumed.

1 to 3 are schematic cross-sectional views during the formation of a printed wiring board including vias.
A through-hole 10A is formed by drilling or laser processing (FIG. 1 (B)) on a core substrate (FIG. 1 (A)) in which copper foils 11a and 11b are bonded to both surfaces of the insulating substrate 10 (FIG. 1 (B)). Primary copper plating layers 12a to 12c are formed by electrolytic plating (FIG. 1C).

Patterning is performed with the resist 13 (FIG. 2A), and a wiring layer 14 is formed by selective plating (FIG. 2B).
After removing the resist 13 (FIG. 2C), the entire surface is etched to remove the primary copper plating layers 12a to 12c and the copper foils 11a and 11b to form a copper wiring (FIG. 3A). .

In FIG. 3B, a blackening process for forming needle-like irregularities on the surface of the copper wiring is performed to give an anchor effect. Subsequently, in FIG. 3C, the insulating substrates 19a and 19b and the copper foils 20a and 20b are bonded together by a laminating press using high-temperature pressurization.
Thereafter, through holes and contact holes are formed, and the laminated wiring board is formed so as to have a desired number of layers by repeating the steps after FIG.

  The above is the wiring formation method by the semi-additive construction method. Here, “semi-additive” means a wiring layer (14) when the entire surface is etched to remove the primary copper plating layers 12a to 12c and the copper foils 11a and 11b in FIGS. 2 (C) to 3 (A). ) Slightly recedes and a slight dimensional change (pattern shift) occurs.

  In the present embodiment, it is possible to adopt a full additive method as a similar forming method. In FIG. 1 (C), the full additive method performs only catalysis, and does not form the primary copper plating layers 12a to 12c to be plating seed layers. Thereafter, the resist 13 is patterned (FIG. 2A), and electroless plating is performed in FIG. 2B to form a wiring layer (14). In this method, since there is no plating seed layer, the entire surface etching shown in FIG. 3A is not performed, or when there are copper foils 11a and 11b as in this example, etching is extremely light. Therefore, the pattern shift of the wiring layer (14) hardly occurs. This is called "full additive".

In this embodiment, a subtractive construction method can be adopted as another typical wiring formation method. In this method, copper wiring is formed by etching copper using a resist after copper plating. In this case, since wet etching is usually used, the pattern shift is large as compared with the above two other methods.
In any method, the process of forming needle-like irregularities on the surface of the copper wiring for improving the patterning adhesion (FIG. 3B) is common.

  As described above, since the thick copper layer is etched by the subtractive method, it is inevitable that the variation of the pattern becomes larger than other methods. The semi-additive method can increase the accuracy because etching after the conductor formation can be reduced, but deviation from the resist pattern occurs. The full additive method can form a conductor as the resist pattern. However, since plating takes a long time, a resist with high alkali resistance is required, and electroless copper plating must be continuously maintained in the same state. Management is difficult.

[Capacitance element structure]
FIG. 4 is a more detailed cross-sectional view showing the capacitive element structure. FIG. 4 is a cross-sectional view of the case where the capacitor element having the MIM structure is formed after the formation of the wiring layer (14) in FIG. 3B, and then the capacitor element is completed through the formation of the insulating substrate 19a. Therefore, the same components as those in FIGS. 1 to 3 are denoted by the same reference numerals, and the description thereof is omitted.
A part of the “protective conductive layer (15)” of the present invention remains on the wiring layer (14), but most of it is removed.

The insulating substrate 19a is opened at the place where the protective conductive layer (15) is removed (first opening), and the capacitor dielectric film 17 is formed along the bottom and side surfaces of the opening.
A copper wiring layer 24 is formed so as to fill the space of the first opening above the capacitor dielectric film 17. A second opening that opens the end of the wiring layer (14) is formed in the insulating substrate 19a. Another copper wiring layer 24 is formed so as to fill the second opening.
These two copper wiring layers 24 are electrode extraction wirings of the capacitive element.

Thus, in this structure, the lower electrode of the MIM capacitor (capacitance element) is formed from the wiring layer formed on the insulating substrate 10, and the upper electrode is formed from the wiring layer on the other layer formed on the insulating substrate 19a. Has been. The proximity arrangement of the two wiring layers having two different layers through the thin dielectric film is performed in the first opening portion opened in the insulating substrate 19a with a relatively large area.
Although not shown in the drawing, the fine unevenness processing (for example, blackening treatment and reduction treatment) for ensuring the adhesion between the insulating substrates is due to the protective conductive layer (15) and the capacitor dielectric film 17, Almost no upper surface of the wiring layer (14) is applied.
However, since the wiring layer (14) and the copper wiring layer 24 are firmly bonded across the capacitor dielectric film 17 in the MIM structure portion, the adhesion strength of this portion is particularly lower than in other places. There is nothing.

  For the capacitive element, the fact that fine irregularities are not formed on the upper surface portion of the copper wiring layer 14 at this location greatly contributes to the reduction of leakage.

  Here, the capacitor dielectric film 17 is preferably formed of a crystalline metal oxide. This crystalline metal oxide has the property of exhibiting crystallinity (cubic crystal or monoclinic crystal) even at a temperature low enough to avoid the restriction of materializing the maximum heating temperature of the multilayer wiring board such as the insulating substrate 19a. The film is formed to have The conditions for developing such a property are, for example, an apparatus for processing a substrate without being exposed to plasma that raises the substrate temperature, such as a counter-sputtering apparatus. Has been confirmed to do.

On the other hand, the occurrence of leak paths along the grain boundaries is also well known. Therefore, this crystalline metal oxide does not require high annealing such as 400 to 450 [° C.] or substrate heating during film formation, and is practical dielectric constant within a range of 200 [° C.] or less and room temperature or more. There is an advantage that a rate can be obtained. On the other hand, crystalline metal oxides are more likely to leak than amorphous metal oxides.
In the present embodiment, since there is a structural feature in which leakage is not easily generated by protecting the base of the capacitor dielectric film 17 while maintaining substrate adhesion, the capacitor dielectric film 17 is formed of this crystalline metal oxide. It is desirable.

Further, at least the surface of the wiring layer (14) in contact with the capacitor dielectric film 17 can be obtained with sufficient crystallinity of the capacitor dielectric film even with Cu, but may be nickel (Ni) or platinum (Pt).
As will be described later, since Ni is recommended as a suitable material for the protective conductive layer (15), Ni or Pt may be selectively formed thin after removing the protective conductive layer (15).
Examples of the metal oxide will be described later.

[Manufacturing Method of Laminated Wiring Board Location Including Capacitance Element Formation]
FIG. 5A to FIG. 8B are cross-sectional views in the middle of manufacturing for explaining the manufacturing method of the first embodiment.
As shown in FIG. 5A, through holes or the like (not shown) are formed in the insulating substrate 10 in which the copper foils 11a and 11b are bonded to the front and back surfaces, and the primary copper plating layers 12a and 12b are formed on the copper foils 11a and 11b. Form.

  As shown in FIG. 5B, patterning is performed with a resist 13, and a wiring layer (14) is formed by selective plating. At this time, patterning with a resist (not shown) and a copper wiring layer are also formed on the back surface. In the following description, wiring formation on the back surface is not shown, but the same processing is performed on the back surface side simultaneously with the front surface side.

  As shown in FIG. 5C, after removing the resist 13, the entire surface is etched in order to remove the copper foil 11a and the primary copper plating layer 12a.

  As shown in FIG. 6A, patterning is performed with, for example, a resist 9 and, for example, a nickel layer (16) is formed in a desired region of the capacitor element forming portion by a selective plating method. As a result, a wiring serving as a lower electrode of the capacitive element is formed.

  As shown in FIG. 6B, after removing the resist 9, needle-like irregularities (not shown) are formed on the exposed portion of the copper surface by blackening treatment or the like. At this time, since the capacitor element forming portion is covered with the nickel layer (16), the surface of the copper wiring layer 14 is not selectively formed with needle-like irregularities.

  As shown in FIG. 7A, the insulating substrate 19a and the copper foil 20a are bonded together by a lamination press. At this time, an insulating substrate (not shown) and a copper foil are bonded to the back surface.

  As shown in FIG. 7B, the insulating film 19a and the copper foil 20a in the dielectric film forming portion of the capacitive element and the other contact portions are opened by laser processing. At this time, the opening is made so that at least the nickel layer (16) in the dielectric film forming portion is not completely lost.

As shown in FIG. 7C, the nickel layer (16) exposed at the opening by the laser processing is removed by selective etching with the copper wiring layer. A number of methods for selectively etching the nickel layer (16) while leaving the copper wiring layer 14 have been introduced. For example, there is an etching method using a chemical solution disclosed in the patent document “Japanese Patent Laid-Open No. 2004-190054”. Accordingly, at least the dielectric film forming portion in the region where the copper wiring layer 14 is exposed can obtain a surface that is free of needle-like irregularities due to blackening treatment or the like or damaged by laser processing.
At this time, the nickel layer (16) can be etched using the opening of the resin substrate (insulating substrate 19a) as a mask, and a dedicated patterning step can be omitted.

As shown in FIG. 8A, a capacitor dielectric film 17 is formed in an opening of a dielectric film formation portion of the capacitor element, and then patterned with a resist 23, and then a copper wiring layer 24 by selective plating. Form.
Finally, as shown in FIG. 8B, the resist 23 is removed.

In this embodiment, the nickel layer (16) is formed by a selective plating method, but the present invention is not limited to this. For example, a plate material (a so-called metal mask) having an opening in a desired region may be disposed on the film formation surface of the substrate and formed by sputtering. In consideration of this action, the material is not limited to nickel, and the same effect can be obtained as long as the material can be selectively removed from copper.
Furthermore, copper and nickel may form an alloy at a temperature of about 200 [° C.]. There is a concern that the alloy may hinder selective removal of nickel, or the roughness of the lower electrode surface may deteriorate due to variations in alloy formation. Therefore, the lamination press is performed at 200 [° C.] or less, more preferably 150 [° C.] or less. Also in this sense, the compatibility with the method of forming the capacitor dielectric film 17 including the crystalline metal oxide formed with the same temperature range as the upper limit is high.

Incidentally, as the material of the capacitor dielectric film 17 may be, for example, _{SiO 2, Si 3 N 4,} Al 2 O 3, HfO 2, ZrO 2, Ta 2 O 5, STO, BTO, a material such as BST. These dielectric materials have a relative dielectric constant of 4 to 400. When such a material is used to incorporate a capacitive element in a printed wiring board, the thickness of the capacitor dielectric film 17 is preferably about 20 to 1000 [nm].

<2. Second Embodiment>
FIG. 9 is a cross-sectional view of the multilayer wiring board according to the second embodiment.
As shown in FIG. 9, a parallel plate type MIM capacitor (capacitance element) is formed on the upper surface of the wiring layer (14).
The lower electrode of the capacitive element can be formed from, for example, a nickel layer. Moreover, the upper electrode can be formed from a copper layer, for example. Since the fine concavo-convex process is performed in a state where the capacitor element having the three-layer structure is formed, the capacitor dielectric film 17 is not damaged by the process. Further, the capacitor dielectric film 17 is not damaged when the insulating substrate 19a is opened.

FIG. 10A to FIG. 13B are cross-sectional views in the middle of manufacturing for explaining the manufacturing method of the second embodiment.
As shown in FIG. 10A, through holes or the like (not shown) are formed in the insulating substrate 10 to which the copper foils 11a and 11b are bonded, and the primary copper plating layers 12a and 12b are formed on the copper foils 11a and 11b. .

As shown in FIG. 10B, patterning is performed with a resist 13, a wiring layer (14) is formed by selective plating, and then a nickel layer 15 is formed by selective plating. By performing the plating of both layers continuously, the resist formation of selective plating can be made common.
At this time, patterning with a resist (not shown) and a copper wiring layer are also formed on the back surface. In the following description, wiring formation on the back surface is not shown, but it is performed on the back surface side simultaneously with the front surface side.

  As shown in FIG. 10C, after removing the resist 13, the entire surface is etched in order to remove the copper foil 11a and the primary copper plating layer 12a. As a result, a wiring serving as a lower electrode of the capacitive element is formed. At this time, many methods of selectively etching copper while leaving nickel have been introduced. For example, there is an etching method using a chemical solution disclosed in a patent document of “Japanese Patent Application Laid-Open No. 2004-043895”.

  As shown in FIG. 11A, a capacitor dielectric film 17 is formed on the lower electrode of the capacitive element. As a method of forming the capacitor dielectric film 17, for example, there is a method of selectively forming a film by a sputtering method using the above-described metal mask.

  As shown in FIG. 11B, a conductive layer (18) serving as an upper electrode is formed in a desired region on the capacitor dielectric film 17. As a method for forming the conductive layer (18), for example, there is a method of selectively forming a film by a sputtering method or the like using the above-described metal mask. The conductive layer (18) may have a laminated structure made of a plurality of materials, but it is desirable to dispose copper as the uppermost layer.

  As shown in FIG. 12A, the region other than the capacitor element portion of the nickel layer 15 is removed. At this time, many methods for selectively etching nickel while leaving copper have been introduced. For example, there is an etching method using a chemical solution disclosed in the patent document “Japanese Patent Laid-Open No. 2004-190054”. At this time, it is possible to etch the nickel layer 15 other than the capacitance forming portion using the dielectric film as a mask. Therefore, a dedicated patterning process for removing unnecessary portions of the nickel layer 15 can be eliminated.

In the state where the copper of the wiring portion is exposed, in order to improve the adhesion by subsequent bonding with the resin substrate (insulating substrate 19a), needle-like irregularities (not shown) are formed by blackening treatment or the like.
At this time, as described above, by removing unnecessary portions of the nickel layer 15 using the upper electrode 18 as a mask, the exposed area of the wiring layer (14) can be maximized, and the resin substrate (insulating substrate 19a). Adhesiveness can be improved.
Further, in the structure of the capacitive element provided by the present embodiment, the upper electrode portion is wider than the wiring width, and therefore the adhesion of this portion is important. At this time, if the uppermost layer of the conductive layer (18) serving as the upper electrode is copper, needle-like irregularities can be formed. Furthermore, according to this manufacturing method, needle-like irregularities can be formed on the upper electrode surface simultaneously with the lower electrode surface, so that it is not necessary to add a blackening treatment process or the like dedicated to the upper electrode.

  As shown in FIG. 12B, the insulating substrate 19a and the copper foil 20a are bonded together by a lamination press. At this time, an insulating substrate (not shown) and a copper foil are bonded to the back surface.

As shown in FIG. 13A, the insulating substrate 19a and the copper foil 20a in the contact portion are opened by laser processing, patterned with a resist 25, and then a copper wiring layer 24 is formed by selective plating.
Finally, as shown in FIG. 13B, the resist 25 is removed.

Even if the nickel layer 15 is not present, needle-like irregularities are not formed on the surface of the wiring layer (14) that becomes the lower electrode portion of the capacitive element, but nickel is formed on the wiring layer (14) formed of the copper plating layer. By forming the plating layer, the surface state can be further improved.
Copper and nickel may form an alloy at a temperature of about 200 [° C.]. Due to this variation in alloy formation, there is a concern that the roughness of the lower electrode surface may deteriorate. Therefore, the formation of the dielectric film, the formation of the upper electrode, and the lamination press are performed at 200 [° C.] or less, more preferably 150 [° C.] or less.

  In the present embodiment, the formation of the dielectric film is not limited to the sputtering method using a metal mask. In the present embodiment, the method for forming the upper electrode is not limited to the sputtering method using a metal mask. For example, by forming by copper plating by the semi-additive method, the area accuracy of the upper electrode that defines the effective capacitance area is improved, and the accuracy of the capacitor can be increased. Further, in the present embodiment, the upper electrode is not limited to being formed from a copper single layer. For example, the same effect can be obtained even in a laminated structure in which the same material as the lower electrode is used as the lower layer and the upper layer is made of copper. Can be increased.

In the first and second embodiments described above, the following effects are obtained.
According to the first embodiment of the present invention, since the effective area of the capacitive element is defined by the area of the lower electrode exposed by the opening by laser processing, high accuracy can be achieved. Further, it is possible to avoid acicular irregularities due to blackening treatment or the like, damage due to laser processing, and the like, and to form a highly reliable capacitive element in the printed wiring board.

According to the second embodiment, it is possible to easily form a highly reliable capacitive element while achieving further improvement of the lower electrode by nickel plating. For example, the removal of the nickel layer can be performed using the dielectric film of the capacitive element as a mask, and a dedicated patterning step can be eliminated. Furthermore, removing the nickel layer using the dielectric film as a mask can maximize the area of the lower electrode where acicular irregularities can be formed, and has a structure advantageous for adhesion to the resin substrate (insulating substrate).
Further, according to the second embodiment, adhesion between the upper electrode having a large area and the insulating substrate is important, but in this embodiment, needle-like irregularities can be formed on the upper electrode surface simultaneously with the lower electrode surface, It is possible to eliminate the processing for the upper electrode.
Furthermore, the present invention smoothes the surface state of the lower electrode of the capacitive element, and the effect is not a technique effective only for a thin film dielectric film. The capacitance element used with the conventional thick dielectric film can also reduce the leakage current.

    DESCRIPTION OF SYMBOLS 10 ... Insulating substrate, 12a, 12b ... Primary copper plating layer, 14, 14c ... Wiring layer, 15 ... Nickel layer, 17 ... Capacitor dielectric film, 18 ... Upper electrode, 19a ... Insulating substrate.

Claims (11)

Capacitor element laminate that covers at least a part of the upper surface of the wiring layer before bonding the insulating substrate in the formation of the laminated substrate structure in which the wiring layer and the other insulating substrate are alternately stacked and bonded to the insulating substrate at least once Forming a step;
Forming fine irregularities to ensure adhesion at the time of bonding to the surface of the wiring layer not covered with the capacitive element stack;
Bonding an insulating substrate to the capacitive element laminate side;
Forming a first opening in which a part of the upper surface of the capacitive element stack is exposed and a second opening in which a part of the upper surface of the wiring layer is exposed in the bonded insulating substrate;
Forming an electrode lead-out wiring of a capacitive element in the first and second openings;
A method for manufacturing a laminated wiring board including: The capacitive element laminate is
A capacitor dielectric film comprising a crystalline metal oxide formed on the lower electrode layer and on the lower electrode layer at a temperature lower than or equal to a heat resistant temperature of the insulating substrate and higher than room temperature;
The method for manufacturing a multilayer wiring board according to claim 1, further comprising: an upper electrode on the capacitor dielectric film. The method for manufacturing a multilayer wiring board according to claim 2, wherein the capacitor dielectric film includes a crystalline metal oxide formed at a temperature lower than a heat resistant temperature of the insulating substrate and higher than a room temperature. The manufacturing method of the multilayer wiring board according to claim 3, wherein the heat resistance temperature of the insulating substrate is 200 ° C. 5. The method for manufacturing a multilayer wiring board according to claim 4, wherein a material of the lower electrode is nickel (Ni) or platinum (Pt). The method for manufacturing a multilayer wiring board according to claim 5, wherein a material of the upper electrode is copper (Cu), and the unevenness is formed on a surface thereof. In the formation of a laminated substrate structure in which a wiring layer and another insulating substrate are alternately stacked and bonded to the insulating substrate at least once, a protective conductive layer that covers at least a part of the upper surface of the wiring layer is bonded before the insulating substrate is bonded. Forming step;
Forming fine irregularities to ensure adhesion at the time of bonding to the surface of the wiring layer not covered with the protective conductive layer;
Bonding an insulating substrate to the side of the protective conductive layer;
Forming a first opening in which a part of the upper surface of the protective conductive layer is exposed and a second opening in which a part of the upper surface of the wiring layer is exposed in the bonded insulating substrate;
Selectively removing a part of the protective conductive layer exposed in the first opening from the underlying wiring layer;
Selectively forming a capacitor dielectric film on at least a bottom surface of the opening in the first opening;
Forming an electrode lead-out wiring of a capacitive element in the first and second openings;
A method for manufacturing a laminated wiring board including: The method for manufacturing a multilayer wiring board according to claim 7, wherein the capacitor dielectric film includes a crystalline metal oxide formed at a temperature lower than a heat resistant temperature of the insulating substrate and higher than a room temperature. The manufacturing method of the multilayer wiring board according to claim 8, wherein the heat-resistant temperature of the insulating substrate is 200 ° C. The method for manufacturing a multilayer wiring board according to claim 9, wherein a material of the lower electrode is nickel (Ni) or platinum (Pt). The method for manufacturing a multilayer wiring board according to claim 10, wherein a material of the upper electrode is copper (Cu), and the unevenness is formed on a surface thereof.

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