JP2019016636A - Wiring board having penetration wiring and manufacturing method therefor - Google Patents

Abstract

To provide a wiring board on which a capacitive element is mounted in which capacitance dispersion is significantly suppressed.SOLUTION: A wiring board 100 includes a board 102 having a through hole 104, a side wall of the through hole, a first wiring 110 that continuously covers a first surface of the board and a second surface of the board, a first dielectric film 116-1 on the first wiring, a first insulating film 118 having an opening overlapping with the first dielectric film on the first dielectric film, and a second wiring 122-1 positioned on the first insulating film and overlapping with the first wiring. The wiring board may further include a metal layer 132 that causes the first dielectric film to be brought into contact with the second wiring between the first dielectric film and the second wiring.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a wiring board and a manufacturing method thereof. For example, the present invention relates to a wiring board having a through wiring and a manufacturing method thereof.

  A semiconductor device (semiconductor chip) manufactured using a semiconductor substrate such as silicon is mounted on almost all electronic devices and provides various functions to the electronic devices. A semiconductor device is formed by laminating various patterned insulating films and conductive films on a semiconductor substrate. The semiconductor device is provided with terminals for inputting power and signals necessary for the operation, and is mounted on the main board. At this time, a wiring board (hereinafter also referred to as an interposer) is provided between the semiconductor device and the main board. The interposer has a substrate and a through wiring (through electrode) penetrating the substrate, and the terminal of the semiconductor device and the wiring on the main substrate are electrically connected by the through wiring.

  As the substrate for the interposer, a silicon substrate or a glass substrate is used. For example, Patent Documents 1 and 2 disclose an interposer manufactured using a glass substrate, a glass-epoxy composite substrate, or the like and mounted with a passive element such as a capacitor element, an inductor, or a resistance element.

Japanese Patent Laid-Open No. 2005-26670 JP 2004-047667 A

  One of the problems of the present disclosure is to provide an interposer on which a passive element such as a capacitor is mounted and a manufacturing method thereof. For example, it is an object to provide an interposer on which a capacitor element in which capacitance variation is significantly suppressed is mounted and a manufacturing method thereof. Alternatively, it is an object to provide a method for manufacturing an interposer with a smaller number of steps.

  One embodiment of the present disclosure is a wiring board. This wiring board has a first surface and a second surface located on the opposite side of the first surface, a substrate having a through hole penetrating from the first surface to the second surface, a sidewall of the through hole, the first surface And a first wiring continuously covering the second surface, a first dielectric film on the first wiring, and a first dielectric film having an opening overlapping the first dielectric film on the first dielectric film. And an insulating film and a second wiring which is located on the first insulating film and overlaps with the first wiring.

  One embodiment of the present disclosure is a wiring board. This wiring board has a first surface and a second surface located on the opposite side of the first surface, a substrate having a through-hole penetrating from the first surface to the second surface, a side wall of the through-hole, the first of the substrate A first wiring continuously covering one surface and the second surface of the substrate; a first insulating film located on the first wiring and having an opening overlapping the first wiring; and the first insulating film A first dielectric film positioned and covering the opening; and a second wiring positioned on the first dielectric film and overlapping the first wiring.

  One embodiment of the present disclosure is a wiring board. This wiring board has a first surface and a second surface located on the opposite side of the first surface, a substrate having a through hole penetrating from the first surface to the second surface, a sidewall of the through hole, the first surface , And a first wiring continuously covering the second surface, located on the substrate, in contact with the substrate, thinner than the first wiring, and covering the through hole, a first insulating film covering the through-hole, and a first wiring on the first wiring And a second wiring which is located on the first dielectric film and overlaps the first wiring.

  One embodiment of the present disclosure is a wiring board. This wiring board has a first surface and a second surface located on the opposite side of the first surface, a substrate having a through hole penetrating from the first surface to the second surface, a sidewall of the through hole, the first surface And a first wiring continuously covering the second surface, a first dielectric film on the first wiring, a second wiring located on the first dielectric film and overlapping the first wiring, A first insulating film located on the second wiring and having an opening overlapping the second wiring, and a lower insulating film located below the substrate. The number of layers of the first insulating film and the number of layers of the lower insulating film are the same.

  One embodiment of the present disclosure is a method for manufacturing a wiring board. In this manufacturing method, a through-hole penetrating from the first surface to the second surface is formed in a substrate having a first surface and a second surface located on the opposite side of the first surface, the side wall of the through-hole, Forming a first wiring so as to continuously cover the surface and the second surface, forming a first dielectric film on the first wiring, and forming a first dielectric on the first dielectric film Forming an insulating film; forming an opening exposing the first dielectric film in the first insulating film; and forming a second wiring covering the opening.

  One embodiment of the present disclosure is a method for manufacturing a wiring board. In this manufacturing method, a through-hole penetrating from the first surface to the second surface is formed in a substrate having a first surface and a second surface located on the opposite side of the first surface, the side wall of the through-hole, Forming a first wiring so as to continuously cover the surface and the second surface, forming a first insulating film on the first wiring, and opening the first wiring to expose the first wiring Forming in the insulating film, forming a first dielectric film covering the opening, and forming a second wiring overlying the first wiring on the first dielectric film.

  One embodiment of the present disclosure is a method for manufacturing a wiring board. In this manufacturing method, a through-hole penetrating from the first surface to the second surface is formed in a substrate having a first surface and a second surface located on the opposite side of the first surface, the side wall of the through-hole, Forming a first wiring so as to continuously cover the surface and the second surface; forming a first insulating film thinner than the first wiring on the substrate so as to be in contact with the substrate; Forming a first dielectric film on the first wiring, and forming a second wiring overlapping the first wiring on the first dielectric film.

  One embodiment of the present disclosure is a method for manufacturing a wiring board. In this manufacturing method, a through-hole penetrating from the first surface to the second surface is formed in a substrate having a first surface and a second surface located on the opposite side of the first surface, the side wall of the through-hole, Forming a first wiring so as to continuously cover the surface and the second surface, forming a first dielectric film on the first wiring, and forming a first dielectric film on the first dielectric film, Forming a second wiring that overlaps the first wiring, forming a first insulating film over the second wiring, and forming a lower insulating film under the substrate. The number of layers of the first insulating film and the number of layers of the lower insulating film are the same.

The cross-sectional schematic diagram of the wiring board of 1st Embodiment. FIG. 3 is a schematic cross-sectional view illustrating a method for manufacturing the wiring board according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating a method for manufacturing the wiring board according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating a method for manufacturing the wiring board according to the first embodiment. FIG. 3 is a schematic cross-sectional view illustrating a method for manufacturing the wiring board according to the first embodiment. The cross-sectional schematic diagram which shows the preparation methods of the conventional wiring board. The cross-sectional schematic diagram which shows the preparation methods of the conventional wiring board. The cross-sectional schematic diagram which shows the preparation methods of the conventional wiring board. The cross-sectional schematic diagram which shows the manufacturing method of the conventional wiring board, and the manufacturing method of the wiring board of one Embodiment. The cross-sectional schematic diagram of the wiring board of 2nd Embodiment. Sectional drawing which shows the preparation methods of the wiring board of 2nd Embodiment. Sectional drawing which shows the preparation methods of the wiring board of 2nd Embodiment. Sectional drawing which shows the preparation methods of the wiring board of 2nd Embodiment. The cross-sectional schematic diagram of the wiring board of 3rd Embodiment. Sectional drawing which shows the preparation methods of the wiring board of 3rd Embodiment. Sectional drawing which shows the preparation methods of the wiring board of 3rd Embodiment. The cross-sectional schematic diagram of the wiring board of 4th Embodiment. Sectional schematic diagram which shows the preparation methods of the wiring board of 4th Embodiment. Sectional schematic diagram which shows the preparation methods of the wiring board of 4th Embodiment. Sectional schematic diagram which shows the preparation methods of the wiring board of 4th Embodiment. Sectional schematic diagram which shows the preparation methods of the wiring board of 5th Embodiment. Sectional schematic diagram which shows the preparation methods of the wiring board of 5th Embodiment. Sectional schematic diagram which shows the preparation methods of the wiring board of 5th Embodiment. Sectional schematic diagram which shows the preparation methods of the wiring board of 5th Embodiment. Sectional schematic diagram which shows the preparation methods of the wiring board of 5th Embodiment. The cross-sectional schematic diagram of the wiring board of 6th Embodiment. Sectional drawing which shows the preparation methods of the wiring board of 6th Embodiment. Sectional drawing which shows the preparation methods of the wiring board of 6th Embodiment. The cross-sectional schematic diagram of the semiconductor module of 7th Embodiment. The cross-sectional schematic diagram of the semiconductor module of 7th Embodiment. The cross-sectional schematic diagram of the semiconductor module of 7th Embodiment.

  Hereinafter, each embodiment of the present disclosure will be described with reference to the drawings. However, the present disclosure can be implemented in various modes without departing from the gist thereof, and is not construed as being limited to the description of the embodiments exemplified below.

  In order to clarify the description, the drawings may be schematically represented with respect to the width, thickness, shape, and the like of each part as compared to actual aspects, but are merely examples and limit the interpretation of the present disclosure. Not what you want. In the present specification and each drawing, elements having the same functions as those described with reference to the previous drawings may be denoted by the same reference numerals, and redundant description may be omitted.

  In the present specification and claims, in expressing a mode of disposing another structure on a certain structure, when simply describing “on top”, unless otherwise specified, It includes both the case where another structure is disposed immediately above and a case where another structure is disposed via another structure above a certain structure.

  When a plurality of films are formed by processing a certain film, or when a plurality of films are formed at the same time in the same process, the plurality of films may have different functions and roles. However, the plurality of films are derived from films formed as the same layer in the same process, and the plurality of films have the same structure and the same material except when a part of these films is selectively processed. Have Therefore, in the present specification and claims, the plurality of films are defined as existing in the same layer.

  In the present specification, when a plurality of constituent elements are distinguished from each other, they are expressed using a hyphen and a natural number after the sign. When noting each of a plurality of constituent elements as a whole, or expressing a constituent element arbitrarily selected from them, only the reference numerals are used.

(First embodiment)
A structure and a manufacturing method of the wiring board 100 which is one embodiment of the present disclosure will be described with reference to the drawings.

1. Structure A schematic cross-sectional view of the wiring board 100 is shown in FIG. The wiring board 100 is sandwiched between, for example, a semiconductor device and a main board, and functions as an interposer for electrically connecting them.

  Specifically, the wiring substrate 100 includes a substrate 102, and the substrate 102 is provided with one or a plurality of through holes 104 penetrating therethrough. The wiring substrate 100 further includes a first wiring (also referred to as a through wiring or a through electrode) that continuously covers the side wall of the through hole 104 and the second surface located on the opposite side of the first surface and the first surface of the substrate 102. ) 110. In FIG. 1, the first wiring 110 does not close the through hole 104, but the first wiring 110 may be provided so as to close the through hole 104.

  In addition to the first wiring 110, various wirings and insulating films can be provided on the wiring substrate 100, and these wirings not only enable electrical connection between the semiconductor device and the main substrate, but also the capacitive element. A passive element such as can be formed. In the example shown in FIG. 1, the wiring substrate 100 includes lower wirings 112-1 and 112-2 positioned below the substrate 102, that is, on the second surface side, and upper portions positioned on the substrate 102, that is, on the first surface side. Wirings 114-1 and 114-2 are provided. Since the connection relationship between the first wiring 110, the lower wiring 112, and the upper wiring 114 can be arbitrarily determined according to the use and function of the wiring substrate 100, they may be electrically connected to each other. Each may be electrically separated. Hereinafter, for convenience, the upper wirings 114-1 and 114-2 are referred to as a third wiring and a fifth wiring, respectively, and the third wiring 114-1 and the fifth wiring 114-2 are collectively referred to as an upper wiring 114.

  Although details will be described later, the first wiring 110, the lower wiring 112, and the upper wiring 114 can be formed by electrolytic plating. In this case, as shown in FIG. 1, a metal layer (hereinafter also referred to as a seed layer) 124 is formed between the substrate 102 and these wirings. The seed layer 124 is in contact with the substrate 102, and is in contact with the corresponding first wiring 110, lower wiring 112, and upper wiring 114. The first wiring 110, the lower wiring 112, and the upper wiring 114 can be formed in the same process. In this case, these wirings exist in the same layer. Note that all or part of these wirings may be formed by another method without providing the seed layer 124. For example, the lower wiring 112 and the upper wiring 114 formed on one surface of the substrate 102 may be formed using a sputtering method, a chemical vapor deposition (CVD) method, an evaporation method, or the like. The wiring is in contact with the substrate 102.

  A dielectric film 116 (a first dielectric film 116-1 and a second dielectric film 116-2) is provided on each of the first wiring 110 and the third wiring 114-1. The dielectric film 116 is also an insulating film, and typically includes silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon carbide, silicon nitride carbide, silicon-containing inorganic compounds such as silicon oxide to which carbon is added, oxidation An aluminum-containing inorganic compound such as aluminum or aluminum nitride, an inorganic compound containing hafnium such as hafnium silicate or hafnium aluminate, or a rare earth-containing inorganic compound such as yttrium oxide can be included. In FIG. 1, the first dielectric film 116-1 and the second dielectric film 116-2 have structures separated from each other. However, since they can be formed in the same process, Can exist in a layer. Although not shown, one dielectric film 116 may be provided so as to overlap the first wiring 110 and the third wiring 114-1. In this case, a part of the dielectric film 116 having an integrated structure functions as the first dielectric film 116-1, and the other part functions as the second dielectric film 116-2.

  A first insulating film 118 is provided on the dielectric film 116 and the fifth wiring 114-2 so as to cover a part of them. The first insulating film 118 covers end portions of the first wiring 110, the upper wiring 114, and the dielectric film 116. In other words, it has an opening overlapping these. On the other hand, a lower insulating film 120 is provided under the substrate 102. The lower insulating film 120 also covers the first wiring 110 and the lower wiring 112 under the substrate 102. Although not shown, the lower insulating film 120 can also have an opening that overlaps the first wiring 110 and the lower wiring 112, whereby the electrical connection between the first wiring 110 and the lower wiring 112 and the semiconductor device or the main substrate can be achieved. Connection is made. The first insulating film 118 and the lower insulating film 120 are made of polyamide such as polyimide and aromatic amide, polyamide imide, polyester such as polyalkylene terephthalate and polyarylate, polycarbonate, polybenzoxazole, polyolefin, syndiotactic polystyrene, and the like. Stereoregular polystyrene, polyarylene sulfides such as polyphenylene sulfide, polyacetals, polyethers containing carbonyl groups such as polyether ketones and polyether ether ketones, polyethers having sulfone groups (polyether sulfones), polyethers having imide groups (Polyetherimide), polyether having nitrile group (polyethernitrile), epoxy resin, benzocyclobutene resin, phenol resin, silicone It may include polymers such as cyanate resins such as triazine resin - fat, fluorine resin, acrylic resin, bismaleimide. These polymers may be mixed with inorganic compounds such as silicon oxide, talc, mica and alumina classified as glass and silica gel as fillers. These polymers may have liquid crystallinity. The first insulating film 118 and the lower insulating film 120 may have the same composition. As shown in FIG. 1, the first insulating film 118 and the lower insulating film 120 may be provided so as to close the through hole 104.

  A lead wiring 122 that overlaps the first wiring 110 and the upper wiring 114 is further provided on the dielectric film 116 and the fifth wiring 114-2. The lead wiring 122 may be provided so as to cover an opening provided in the first insulating film 118, and may cover a part of the first insulating film 118. Specifically, the lead wiring 122 may cover the upper surface of the first insulating film 118, that is, the surface of the first insulating film 118 on the side opposite to the substrate 102. Hereinafter, for convenience, the lead wiring 122 overlapping the first wiring 110, the third wiring 114-1, and the fifth wiring 114-2 will be referred to as the second wiring 122-1, the fourth wiring 122-2, and the second wiring 122-2, respectively. 6 wiring 122-3. Further, the second wiring 122-1, the fourth wiring 122-2, and the sixth wiring 122-3 are collectively referred to as a lead wiring 122.

  The connection between the second wiring 122-1, the fourth wiring 122-2, and the sixth wiring 122-3 can be arbitrarily determined according to the use and function of the wiring board 100, and can be directly or indirectly with each other. May be electrically connected or electrically separated. Similar to the first wiring 110 and the upper wiring 114, the lead wiring 122 can also be formed by electrolytic plating or vapor deposition. In this case, as shown in FIG. 1, a seed layer 132 in contact with these is provided on the first dielectric film 116-1, the second dielectric film 116-2, and the fifth wiring 114-2. Lead wiring 122 is formed in contact with seed layer 132. Note that the formation of the seed layer 132 over the fifth wiring 114-2 is arbitrary, and the fifth wiring 114-2 and the sixth wiring 122-3 can be in direct contact with each other without providing the seed layer 132. Although not shown, when the lead wiring 122 is formed by sputtering or CVD, the lead wiring 122 is in direct contact with the dielectric film 116 or the fifth wiring 114-2.

  A second insulating film 126 is formed on the lead wiring 122 to cover the end of the lead wiring 122. The second insulating film 126 also has an opening overlapping the lead wiring 122, and the lead wiring 122 is electrically connected to the semiconductor device or the main substrate through this opening. Similarly to the first insulating film 118, the second insulating film 126 can contain the above-described polymer, and may have the same composition as the first insulating film 118.

  A capacitor is formed by stacking the first wiring 110, the first dielectric film 116-1, and the second wiring 122-1. Similarly, a capacitor is formed by stacking the third wiring 114-1, the second dielectric film 116-2, and the fourth wiring 122-2. The lead wiring 122 forms an electrical circuit of the wiring board 100 and can be used for electrical connection with other wiring boards, semiconductor devices, and main boards provided thereon. That is, the lead wiring 122 functions not only as one electrode of the capacitor element but also as a wiring for constructing an electric circuit in the wiring substrate 100 and for electrical connection with another substrate. With the above-described configuration, the wiring board 100 functions as an interposer on which passive elements are mounted.

  Although FIG. 1 illustrates the wiring substrate 100 having two capacitive elements, the number of capacitive elements is not limited. In addition, it is not always necessary to form a capacitor element using the first wiring 110 functioning as a through wiring, and the capacitor element may be formed only on the upper wiring 114.

2. Manufacturing Method Hereinafter, a manufacturing method of the wiring substrate 100 will be described. The method of manufacturing the wiring substrate 100 is mainly by forming the first wiring 110, forming the dielectric film 116, forming the first insulating film 118, forming the lead wiring 122, and forming the second insulating film 126. Composed.

2-1. Substrate First, the through hole 104 is formed in the substrate 102 (FIG. 2A). There is no particular limitation on the material included in the substrate 102; for example, glass, silicon, gallium arsenide, gallium nitride, ceramics, or a composite material of glass and resin can be given. Examples of the resin include materials that can be used for the first insulating film 118 described above, such as epoxy resin, polyimide, polyamide, and polyester. When a glass substrate is used as the substrate 102, the through-hole 104 may be formed by etching such as plasma etching or wet etching, laser irradiation, or mechanical processing such as sand blasting or ultrasonic drilling. The number and size of the through holes 104 can be arbitrarily determined according to the design of the wiring board 100.

2-2. First Wiring, Lower Wiring, Upper Wiring Next, a seed layer 124 is formed on the surface of the substrate 102 and the side wall of the through hole 104 (FIG. 2A). The seed layer 124 is provided for forming the first wiring 110, the lower wiring 112, and the upper wiring 114 by electrolytic plating, and includes a metal such as titanium, nickel, chromium, copper, gold, or an alloy thereof. Among these, a metal with high adhesiveness with glass is preferable. The seed layer 124 can be formed by sputtering, CVD, electroless plating, vapor deposition, or the like. Although not shown, the surface of the substrate 102 may be coated with the above-described film containing a resin or an inorganic compound before the seed layer 124 is formed. In this case, the entire surface of the substrate 102 including the side wall of the through hole 104 may be coated, or the side wall of the through hole 104 is not coated and the first surface and the second surface of the substrate 102 are selectively coated. May be.

  Next, a resist 130 is provided on the first surface of the substrate 102 (FIG. 2B). As the resist 130, a liquid resist may be used. However, since the substrate 102 has the through hole 104, the resist 130 has a relatively uniform thickness by attaching a film-like resist to the substrate 102. Can be formed. After that, patterning is performed by performing exposure and development through a photomask to form a resist mask 131 that covers a region where the first wiring 110, the lower wiring 112, and the upper wiring 114 are not formed (FIG. 2C). Through a similar process, a resist mask 131 is also formed on the lower side of the substrate 102 (FIG. 2D). Note that the resist mask 131 may be formed on the substrate 102 first, or may be provided below the substrate 102 first, or may be provided on the top and bottom of the substrate 102 at the same time.

  Thereafter, power is supplied to the seed layer 124 to perform electrolytic plating, and the first wiring 110, the lower wiring 112, and the upper wiring 114 are formed on the seed layer 124 that is not covered with the resist mask 131 (that is, in the opening of the resist mask 131). (FIG. 3A). These wirings can include metals such as titanium, aluminum, copper, nickel, tungsten, molybdenum, gold, silver, iron, and chromium, and alloys thereof. These wirings may have a laminated structure of different metal films, for example, a laminated film of metal films containing copper, nickel, and gold, respectively. After that, the resist mask 131 is removed, and the seed layer 124 exposed from the first wiring 110, the lower wiring 112, and the upper wiring 114 is removed by etching (FIG. 3B). The etchant can be arbitrarily selected from etchants that do not damage the substrate 102. Examples of the etchant include acidic etchants containing sulfuric acid.

2-3. Dielectric Film Next, the dielectric film 116 of the capacitive element is formed. Specifically, a dielectric film is formed using a CVD method or a sputtering method so as to cover almost the entire surface of the substrate 102, and this is etched so that one of the first wiring 110 and the third wiring 114-1 is formed. To dielectric films 116-1 and 116-2 that selectively cover the respective portions. As shown in FIG. 3C, the dielectric film 116 can be provided so as to be in contact with the side surfaces of the first wiring 110 and the third wiring 114-1 and part of the first surface of the substrate 102. As described above, the first dielectric film 116-1 and the second dielectric film 116-2 may have an integrated structure.

2-4. Insulating Film Subsequently, a first insulating film 118 and a lower insulating film 120 are formed so as to cover the first surface and the second surface of the substrate 102, respectively (FIG. 4A). These insulating films may be formed so as to cover the through hole 104 or may be formed so as not to block the through hole 104. The first insulating film 118 and the lower insulating film 120 are also regions in which film-like insulating materials are provided on the first and second surfaces of the substrate 102 to form openings for exposing the dielectric film 116 and the fifth wiring. It can be formed by curing other materials and removing the insulating material in other regions (FIG. 4B). The lower insulating film 120 may be formed using either a film-like insulating material or a liquid insulating material, and the insulating material may be photosensitive or non-photosensitive. For example, a film-like resist used for forming the resist 130 may be used, or a resist having a composition different from that of the resist 130 may be applied.

2-5. Lead wiring Next, the lead wiring 122 is formed. Specifically, as shown in FIG. 4C, a seed layer 132 is formed over the first insulating film 118, the dielectric film 116, and the fifth wiring 114-2, and a resist 130 is formed over the seed layer 132. Form. However, as described above, the formation of the seed layer 132 on the fifth wiring 114-2 is arbitrary. Similar to the formation of the first wiring 110, the resist 130 is patterned by exposure and development to form a resist mask 131 having openings that overlap with the first wiring 110 and the upper wiring 114 (FIG. 5A). .

  Thereafter, lead wires 122 are formed by electrolytic plating. As a result, the second wiring 122-1 that overlaps the first wiring 110 via the dielectric film 116-1, and the fourth wiring 122- that overlaps the third wiring 114-1 via the dielectric film 116-2. 2 and the 6th wiring 122-3 which overlaps with the 5th wiring 114-2 is formed. After that, the resist mask 131 is peeled off, and the seed layer 132 is removed by etching (FIG. 5B).

  Note that the lead wiring 122 may be formed by a CVD method, a sputtering method, a vapor deposition method, or the like. In this case, the seed layer 132 does not need to be formed, and the second wiring 122-1, the fourth wiring 122-2, and the sixth wiring 122-3 are formed on the first dielectric film 116-1, It is in direct contact with the second dielectric film 116-2 and the fifth wiring 114-2.

2-6. Second Insulating Film Subsequently, a second insulating film 126 is formed using a method similar to the formation of the first insulating film 118 (FIG. 5C).

3. Conventional Wiring Board Manufacturing Method For comparison, an example of a conventional wiring board manufacturing method is briefly described. The conventional manufacturing method mainly forms the first wiring 110, the dielectric film 116, the upper electrode 123, the first insulating film, the lead wiring, and the second insulating film. including. That is, after forming the dielectric film 116 of the wiring substrate 100 (FIG. 3C), the seed layer 132 is formed (FIG. 6A). Subsequently, formation of the resist mask 131 (FIG. 6B), formation of the upper electrode 123 by electrolytic plating, removal of the resist mask (FIG. 6C), removal of the seed layer 132 (FIG. 7A), first The insulating film 118 is formed (FIG. 7B). Subsequently, a seed layer 134 is formed on the first insulating film 118, a resist mask 131 is formed on the seed layer 134 (FIG. 7C), and a lead wiring 122 is provided using an electrolytic plating method (FIG. 8 ( A)). After that, the resist mask 131 and the seed layer 134 are removed (FIG. 8B), and the second insulating film 126 is formed (FIG. 8C). Therefore, in the conventional method, the upper electrode 123 functions as one electrode of the capacitive element.

  Here, an enlarged view of a region surrounded by a dotted line in FIG. 7A is shown in FIG. FIG. 9A shows a state where the seed layer 132 is removed by etching after the upper electrode 123 is formed. Etching of the seed layer 132 is performed under the condition that an etching rate difference as large as possible is obtained between the seed layer 132 and the upper electrode 123. Specifically, a condition that the seed layer 132 is dissolved at a rate higher than that of the upper electrode 123 is selected. In the etching, since it is necessary to reliably remove the seed layer 132 in a region not covered with the upper electrode 123, a part of the seed layer 132 covered with the upper electrode 123 is also etched (side-etched). As a result, the length L ′ at which the seed layer 132 contacts the dielectric film is smaller than the length L of the upper electrode 123.

  As can be understood from FIGS. 6B and 6C, the length L can be controlled by an opening provided in the resist mask 131. Since the size of the opening is determined by the exposure to the resist 130 and the subsequent development, it can be controlled accurately and easily by a comparative operator. On the other hand, it is not always easy to precisely control the side etching of the seed layer 132, and a large variation occurs in the length L ′.

  Here, the capacitance of the capacitive element of the wiring substrate 100 is determined by the area where an electric field is applied to the dielectric film 116. In the conventional example, the capacitance is determined not by the area of the upper electrode 123 but by the contact area between the dielectric film 116 and the seed layer 132. Therefore, the occurrence of the variation in the length L ′ directly causes the variation in the capacitance.

  In contrast, in the manufacturing method of this embodiment, as shown in the enlarged view of the region surrounded by the dotted line in FIG. 5B (FIG. 9B), the contact between the dielectric film 116 and the seed layer 132 is performed. The area is determined by the opening of the first insulating film 118. Since the size and shape of the opening are determined by exposure using a photomask to the first insulating film 118 and subsequent development (see FIGS. 4A and 4B), it can be easily controlled. . Even if the seed layer 132 is side-etched, the side-etched portion is located on the upper surface of the first insulating film 118, that is, the surface of the first insulating film 118 opposite to the substrate 102. The length L ′ is not affected, and the contact area between the dielectric film 116 and the seed layer 132 does not change. For this reason, by applying this embodiment, it is possible to form a capacitive element having an accurate capacitance, and to reduce variations thereof.

  Furthermore, in the manufacturing method according to the present embodiment, the number of wiring forming steps is small compared to the conventional example. More specifically, the step of forming the upper electrode 123 is unnecessary, and the lead wiring 122 also serves as the upper electrode 123. For this reason, it is possible to manufacture a wiring board at low cost. In addition, since the number of electrical connection portions is reduced, the risk of contact failure is eliminated, and an improvement in processing yield can be expected.

(Second Embodiment)
In the present embodiment, a structure and manufacturing method of a wiring board 150 having a structure different from that of the wiring board 100 will be described. A description of the same or similar configuration as in the first embodiment may be omitted.

  FIG. 10A is a schematic cross-sectional view of the wiring board 150, and FIG. 10B is an enlarged view of a region surrounded by a dotted line in FIG. The wiring substrate 150 is located on the dielectric film 116 and the side surface of the seed layer 132 in contact with the first insulating film 118 and the side surfaces of the first wiring 110 and the upper wiring 114 are flush or substantially the same. It differs from the wiring board 100 in that it is located on the same plane (see FIG. 10B). Further, the upper surface of the first wiring 110, that is, a part of the surface of the first wiring 110 located on the side opposite to the substrate 102 is in contact with the second insulating film 126.

  The wiring board 150 having such a structure can be manufactured by the following method. First, similarly to the production of the wiring substrate 100, the first wiring 110, the lower wiring 112, and the upper wiring 114 are formed on the substrate 102, and the first wiring 110 and the third wiring 114-1 are respectively formed on the first wiring 110 and the third wiring 114-1. A first dielectric film 116-1 and a second dielectric film 116-2 are formed (FIG. 11A). After that, as shown in FIG. 11B, a first insulating film 118 is formed. The first insulating film 118 is formed by exposing and developing a film-like photosensitive resin. Specifically, after an unresolved photosensitive resin is provided on the substrate 102, exposure is performed from below the substrate 102, that is, from the surface where the lower wiring 112 is formed. Thereby, light irradiation is performed in a region other than the region where the first wiring 110, the lower wiring 112, and the upper wiring 114 are provided. When the photosensitive resin is a negative type, the region irradiated with light is cured, so that the first insulating film 118 is not formed over the first wiring 110, the lower wiring 112, and the upper wiring 114 after development (FIG. 11 (C)). After that, the lower insulating film 120 is formed under the substrate 102 (FIG. 12A).

  Subsequent steps can be performed in the same manner as the fabrication of the wiring substrate 100. That is, a seed layer 132 is formed over the first insulating film 118 and the dielectric film 116, and a resist mask 131 is further formed (FIG. 12B). Electrolytic plating is applied to form the lead wiring 122 on the seed layer 132 (FIG. 12C), and after removing the resist mask 131 (FIG. 13A), the end of the lead wiring 122 is covered. Then, a second insulating film 126 is formed (FIG. 13B). Thereby, the wiring board 150 can be obtained.

  In the manufacturing method described above, it is not necessary to use a photomask when exposing the photosensitive resin, and alignment of the photomask at the time of exposure is unnecessary. For this reason, it becomes possible to provide a wiring board at lower cost.

(Third embodiment)
In the present embodiment, a structure and manufacturing method of a wiring board 160 having a structure different from that of the wiring boards 100 and 150 will be described. A description of the same or similar configuration as in the first and second embodiments may be omitted.

  As shown in the schematic cross-sectional view of FIG. 14, the wiring substrate 160 includes a dielectric film 116 provided on the first wiring 110, the third wiring 114-1, and the first insulating film 118. It differs from the wiring boards 100 and 150 in that it does not come into contact with 102. The first insulating film 118 has openings that overlap the first wiring 110, the third wiring 114-1, and the fifth wiring 114-2, and the dielectric film 116 covers the former two. Is formed. A part of the dielectric film 116 covers the upper surface of the first insulating film 118, that is, the surface of the first insulating film 118 located on the side opposite to the substrate 102.

  The wiring board 150 having such a structure can be manufactured by the following method. First, similarly to the production of the wiring substrate 100, the first wiring 110, the lower wiring 112, and the upper wiring 114 are formed on the substrate 102, and then the first insulating film 118 is formed thereon. The first insulating film 118 is provided with an opening that overlaps the first wiring 110 and the upper wiring 114, and the first wiring 110 and the upper wiring 114 are exposed in the opening (FIG. 15A). After that, the first wiring 110 is covered so as to cover the former two and to be in contact with the upper surface of the first insulating film 118, that is, a part of the surface of the first insulating film 118 opposite to the substrate 102. A first dielectric film 116-1 and a second dielectric film 116-2 are formed over the third wiring 114-1, respectively (FIG. 15B).

  The subsequent steps are the same as those for manufacturing the wiring substrate 100, and after forming the seed layer 132 over the first insulating film 118 and the dielectric film 116, the resist mask 131 is formed (FIG. 15C). Electrolytic plating is performed by supplying power to the seed layer 132 exposed through the opening of the resist mask 131 to form the lead wiring 122. As a result, the second wiring 122-1 is disposed on the first wiring 110 and the third wiring 114-1 via the first dielectric film 116-1 and the second dielectric film 116-2, respectively. The fourth wiring 122-2 is formed, and the sixth wiring 122-3 is formed over the fifth wiring 114-2 (FIG. 16A). After that, a second insulating film 126 that covers an end portion of the lead wiring 122 and has an opening overlapping the lead wiring 122 is formed (FIG. 16B).

  In the manufacturing method described in this embodiment, after the first wiring 110 and the upper wiring 114 are formed, the first insulating film 118 is formed before the dielectric film 116 is formed. Therefore, the dielectric film 116 and the upper wiring 114 can be etched in a state where the end portions of the first wiring 110 and the upper wiring 114 are covered with the first insulating film 118. As a result, the side surfaces of the first wiring 110 and the upper wiring 114, the interface between the first wiring 110 and the upper wiring 114 and the seed layer 124, or the interface between the seed layer 124 and the substrate 102 are not exposed to the etchant. The side etching and peeling of the wiring 110 and the upper wiring 114 can be prevented, and a highly reliable capacitive element can be formed.

  Further, due to the difference between the coefficient of thermal expansion of the substrate 102 and the coefficient of thermal expansion of the first wiring 110 and the upper wiring 114, the substrate 102 may be cracked by heating during the formation of the dielectric film 116. Before the body film 116 is formed, the first insulating film 118 is used to cover the first wiring 110 and the upper wiring 114, so that interface peeling between the substrate 102 and the first wiring 110 and the upper wiring 114 is suppressed. Since force is applied, the generation of cracks can be suppressed. Furthermore, since the substrate heating temperature when forming the dielectric film 116 can be set high, it is possible to form the dielectric film 116 having a high dielectric constant, thereby forming a capacitor element having a high withstand voltage.

  Further, like the wiring boards 100 and 150, the number of wiring forming steps is smaller than that of a conventional wiring board manufacturing method. For this reason, it is possible to manufacture a wiring board with fewer steps.

(Fourth embodiment)
In the present embodiment, a wiring board 170 having a structure different from that of the wiring boards 100, 150, and 160 and a manufacturing method thereof will be described. A description of the same or similar configuration as in the first to third embodiments may be omitted.

  As schematically shown in the cross-sectional view of FIG. 17, one of the differences between the wiring boards 100, 150, 160 and the wiring board 170 is the first insulating film 118 located on the substrate 102 and in contact with the substrate 102. The thickness of the first wiring 110 is the same as or smaller than the thickness of the first wiring 110 or the sum of the thickness of the seed layer 124 and the first wiring 110. Further, the first insulating film 118 is formed so as to close the through hole 104. In the wiring substrate 170 shown in FIG. 17, the upper electrode 123 is provided between the first wiring 110 and the second wiring 122-1, and between the third wiring 114-1 and the fourth wiring 122-2. It has been. In such a structure, the capacitance of the capacitive element is determined by the contact area between the dielectric film 116 and the seed layer 132 (the contact area with the upper electrode 123 of the dielectric film 116 when the seed layer 132 is not used). The upper electrode 123 is not an essential component, and the upper electrode 123 may not be provided as described later.

  The wiring board 170 can be manufactured by the following method. First, similarly to the method for manufacturing the wiring substrate 100, the first wiring 110, the lower wiring 112, and the upper wiring 114 are formed on the substrate 102. After that, as shown in FIG. 18A, a first insulating film 118 is formed. The thickness of the first insulating film 118 is the sum of the thickness of the first wiring 110 and the upper wiring 114, the thickness of the first wiring 110 and the seed layer 124, or the thickness of the upper wiring 114 and the seed layer 124. Or less. The first insulating film 118 is formed by attaching a film-like photosensitive resin to the substrate 102 on which the wiring is formed, and performing exposure and development through a photomask. A lower insulating film 120 is provided on the second surface of the wiring substrate 100, that is, the surface located on the substrate 102 side of the wiring substrate 100 (FIG. 18B). The thickness of the lower insulating film 120 can be arbitrarily determined, and may be provided to be thicker than the first insulating film 118.

  Subsequently, a dielectric film 116 is formed on the first wiring 110 and the third wiring 114-1 (FIG. 18C), and a seed layer 132 is provided thereon (FIG. 19A). . These formations may be performed by applying the method described in the first embodiment.

  A resist mask 131 is formed over the seed layer 132, and openings that overlap with the dielectric film 116, the first wiring 110, and the third wiring 114-1 are provided in the resist mask 131 (FIG. 19A). ). As described above, since the through-hole 104 is blocked by the first insulating film 118, the resist mask 131 can be manufactured using not only a film-like resist but also a liquid resist. That is, a resist mask is formed by applying a liquid resist on the seed layer 132 using a wet film forming method such as a spin coating method, a dip coating method, a printing method, or an ink jet method, and performing exposure and development through a photomask. 131 can be formed.

  Compared with a film-like resist, a liquid resist can form a finer resist pattern with high accuracy, and thus the shape of the resist mask 131 can be controlled more precisely. As understood from FIG. 17, the capacitance of the capacitive element of the wiring board 170 is determined by the contact area between the dielectric film 116 and the seed layer 132, which is determined by the area of the opening of the resist mask 131 (FIG. 19 ( A) and FIG. 19 (B)). Therefore, by precisely controlling the patterning of the resist mask 131 using a liquid resist, the capacity can be accurately controlled. Although a specific description is omitted, patterning of the dielectric film 116 may also be performed using a liquid resist.

  Thereafter, the upper electrode 123 is formed by using an electrolytic plating method (FIG. 19B), and then the resist mask 131 is removed and the seed layer 132 is etched (FIG. 19C). After that, a second insulating film 126 is formed (FIG. 20A). The second insulating film 126 has an opening that overlaps with the upper electrode 123 and the fifth wiring 114-2, and covers these end portions. The second insulating film 126 is formed to have a larger thickness than the first insulating film 118. These steps can be performed by a method similar to the method described in the first and second embodiments.

  Thereafter, the lead wiring 122 is formed similarly to the formation of the lead wiring 122 of the wiring substrate 100. That is, the seed layer 134 is formed on the second insulating film 126, the upper electrode 123 exposed through the opening, and the fifth wiring 114-2, and after forming a resist mask 131 (not shown), electrolytic plating is performed, and the lead wiring is formed. 122 is formed on the upper electrode 123. As a result, the first wiring 110, the third wiring 114-1, the second wiring 122-1 overlapping the fifth wiring 114-2, the fourth wiring 122-2, and the first wiring 110-2 through the upper electrode 123 Six wirings 122-3 are formed (FIG. 20B).

  Thereafter, a third insulating film 128 is formed so as to cover the end portion of the lead wiring 122 (FIG. 20C). The third insulating film 128 can be formed by a method similar to that of the second insulating film 126.

  As described above, by applying this embodiment, a wiring board having a precisely controlled capacitance can be produced.

(Fifth embodiment)
In this embodiment, a manufacturing method different from the manufacturing method of the wiring substrate 170 described in the fourth embodiment will be described. Specifically, four modified examples are shown below. A description of the same or similar configuration as in the first to fourth embodiments may be omitted.
1. First Modification In this modification, the upper electrode 123 is not provided, and the lead wiring 122 also serves as one electrode of the capacitive element. Specifically, as shown in FIG. 21A, after the dielectric film 116 is formed, the second insulating film 126 is formed. The second insulating film 126 has an opening overlapping the first wiring 110 and the upper wiring 114 and covers these end portions.

  Thereafter, the seed layer 132 is formed on the second insulating film 126 and the dielectric film 116 exposed in the opening, the resist mask 131 is formed, the lead wiring 122 is formed by electrolytic plating, and the resist mask is formed. 131 and the seed layer 132 are removed (FIG. 21B). As a result, the second wiring 122-1 and the fourth wiring are formed on the first wiring 110 and the third wiring 114-1 via the first dielectric film 116-1 and the second insulating film 126-2. A wiring 122-2 is formed, and a sixth wiring 122-3 is formed over the fifth wiring 114-2. After that, a third insulating film 128 is formed so as to cover the end portion of the lead wiring 122 (FIG. 21C).

  Also in this modification, the shape and size of the opening of the second insulating film 126 that determines the capacitance of the capacitor element are determined by patterning by application of a liquid resist and subsequent exposure and development. Since a liquid resist can be used as the resist, precise patterning is possible. As a result, a wiring board having an accurate capacity can be provided. Further, as with the wiring board 100, the lead wiring 122 also serves as one electrode of the capacitive element, so that the number of wiring forming steps is less than that of a conventional wiring board manufacturing method, and the wiring board can be manufactured at a lower cost. Is possible.

2. Second Modification FIGS. 22A to 22D illustrate a manufacturing process of a capacitor including the third wiring 114-1. In this modification, the case where the first insulating film 118 is formed using a negative resist will be described. As shown in FIG. 22A, in this modification, when the photosensitive resin providing the first insulating film 118 is irradiated with light, the light shielding portion 142 having a larger area than the third wiring 114-1 is formed. The formed photomask 140 is used. Then, the photomask 140 is placed so that the light shielding portion 142 overlaps the third wiring 114-1 and the resist located outside thereof, and exposure is performed. Then, development is performed to separate the end portion of the third wiring 114-1 from the first insulating film 118 and expose the first surface of the substrate 102 therebetween as shown in FIG. 22B. To do. Although not shown, a light shielding portion having an area larger than those of the first wiring 110 and the fifth wiring 114-2 is also arranged on the first wiring 110 and the fifth wiring 114-2. Through the subsequent development process, the end portions of these wirings and the first insulating film 118 are separated from each other.

  Thereafter, a dielectric film 116 is formed (FIG. 22C). The dielectric film 116 is in contact with the substrate 102 between the end portion of the third wiring 114-1 and the first insulating film 118. Similarly, the first dielectric film 116-1 is in contact with the substrate 102 between the end portion of the first wiring 110 and the first insulating film 118.

  The subsequent steps are the same as those in the fourth embodiment, and the second insulating film 126, the upper electrode 123, the lead wiring 122, and the third insulating film 128 are sequentially formed on the dielectric film 116 (FIG. 22 ( D)).

  The above-described example is applied when a negative resist is used. On the other hand, when a positive resist is used, a photomask 140 in which a light transmitting part having a larger area than the first wiring 110 and the upper wiring 114 is used is used. A photomask 140 may be placed so as to overlap with the outside and exposure may be performed.

  In the example shown in FIGS. 22A to 22D, the upper electrode 123 is provided between the upper wiring 114 and the lead wiring 122, but the upper electrode 123 is provided as in the first modification. It does not have to be.

  As described above, the dielectric film 116 is in contact with the substrate 102 between the end portions of the first wiring 110 and the upper wiring 114 and the first insulating film 118, and as a result, as shown in FIG. Step (arrow) occurs. Since the second insulating film 126 enters the step (FIG. 22D), the adhesion between the second insulating film 126 and the dielectric film 116 is improved by the anchor effect. As a result, the reliability of the wiring board can be improved.

3. Third Modification In this modification, in contrast to the second modification, a light-shielding portion having an area smaller than that of the third wiring 114-1 when the resist that provides the first insulating film 118 is irradiated with light. A photomask 140 in which 142 is formed is used (FIG. 23A). Then, the photomask 140 is arranged so that the light shielding portion 142 does not overlap the end portion of the third wiring 114-1, and exposure is performed. Then, development is performed, so that part of the first insulating film 118 covers the end portion of the third wiring 114-1 and the opening of the first insulating film 118 is used as shown in FIG. The third wiring 114-1 is exposed. Although not shown, the same exposure method can be applied to the first wiring 110 and the fifth wiring 114-2.

  After that, as in the first modification, the dielectric film 116, the second insulating film 126, the lead wiring 122, and the third insulating film 128 are sequentially formed (FIGS. 23C and 23D). ).

  In this modification, the size of the capacitance is determined by the contact area between the first wiring 110 and the first dielectric film 116-1, and the third wiring 114-1 and the second dielectric film 116-2. Is determined by the opening of the first insulating film 118. As described above, the first insulating film 118 is formed to have a small thickness. Therefore, even when the first insulating film 118 is formed using a film-like resist, microfabrication is easy, and an opening having an accurate shape and size can be provided in the first insulating film 118. As a result, variation in capacitance can be reduced.

4). Fourth Modification In this modification, when the first insulating film 118 is formed, the resist is exposed from the lower side of the substrate 102 (that is, the side where the lower wiring 112 is provided) (FIG. 24 ( A)). In the subsequent development process, the first insulating film 118 is in contact with the side surface of the third wiring 114-1, and the portion in contact with the end of the third wiring 114-1 is a ridge (a portion surrounded by a dotted circle). give. Although not shown, the same applies to the first wiring 110 and the fifth wiring 114-2, the side surfaces of these wirings are in contact with the first insulating film 118, and the first insulating film is at the end of these wirings. 118 has a ridge.

  Thereafter, a dielectric film 116 is formed, and a resist for providing the second insulating film 126 is provided thereon (FIGS. 24C and 24D). Exposure at the time of forming the second insulating film 126 is also performed from the lower side of the substrate 102 (FIG. 24D). By applying such a method, as shown in FIG. 25A, the side surface of the third wiring 114-1 and the side surface of the second insulating film 126 exist on the same plane. Subsequently, the seed layer 132 and the lead wiring 122 are formed (FIG. 25B), and a third insulating film 128 covering the end of the lead wiring 122 is formed (FIG. 25C).

  In this manufacturing method, since the side surface of the third wiring 114-1 and the side surface of the second insulating film 126 are on the same plane, the side surface of the seed layer 132 in contact with the second insulating film 126 is also on the third wiring 114. -1 and the same plane. In other words, the possibility that the position of the lead wiring 122 or the seed layer 132 that functions as one electrode of the capacitor is shifted from the position of the third wiring 114-1 is eliminated. Therefore, it is not necessary to increase the area of the upper wiring 114 in consideration of the process margin, and the area occupied by the capacitive element can be reduced. As a result, the degree of freedom in designing the wiring board can be improved.

(Sixth embodiment)
In this embodiment, a wiring board 180 having a structure different from that of the wiring boards 100, 150, 160, and 170 and a manufacturing method thereof will be described. A description of the same or similar configuration as in the first to fifth embodiments may be omitted.

  Wiring substrate 180 is the same in that the number of insulating films provided on substrate 102 is the same as the number of insulating films provided below substrate 102 except for dielectric film 116. This is one of the differences from 160 and 170. In the example shown in FIG. 26, the insulating film provided on the substrate 102 is the first insulating film 118, and the insulating film provided below the substrate is the lower insulating film 120. The first insulating film 118 and the lower insulating film 120 can each be composed of a single layer or a plurality of layers, but the number of layers is the same. In addition, the thicknesses of the first insulating film 118 and the lower insulating film 120 may be the same or substantially the same. Further, the compositions of the first insulating film 118 and the lower insulating film 120 may be the same.

  The wiring board 180 can be manufactured by the following method. First, after forming the first wiring 110, the lower wiring 112, and the upper wiring 114 on the substrate 102, the dielectric film 116 is formed on the first wiring 110 and the upper wiring 114. After that, the lead wiring 122 is formed over the dielectric film 116 and the fifth wiring 114-2 through the seed layer 132 (FIG. 27A).

  Subsequently, a first insulating film 118 that covers an end portion of the lead wiring 122 and has an opening overlapping the lead wiring 122, and a lower insulating film 120 that covers the lower wiring 112 are formed (FIG. 27B). Although not shown, the lower insulating film 120 may have an opening overlapping the lower wiring 112. Thereby, the wiring board 180 is produced.

  Note that as shown in FIG. 28A and an enlarged view thereof (FIG. 28B), the second wiring 122-1 and the fourth wiring 122-2 that form the capacitor are the first wiring 110. Alternatively, it may be provided so as to cover the side surfaces of the third wiring 114-1 and the dielectric film 116. With such a structure, the side surfaces of the first wiring 110, the third wiring 114-1, and the dielectric film 116 can also be used as part of the capacitor element, and the capacitance per unit area of the capacitor element is increased. Can do. For this reason, it is possible to reduce the size of the capacitive element, and the degree of freedom in designing the wiring board is improved.

  Usually, when insulating films are provided above and below a substrate, the insulating film gives stress to the substrate due to a difference in thermal expansion coefficient between the substrate and the insulating film. When the magnitudes of stress applied to the upper and lower insulating films are different, the substrate is warped, which greatly affects the performance and reliability of the wiring substrate. However, by adopting the above-described structure, stress received from above and below the substrate 102 is canceled out, warping of the substrate 102 can be prevented, and the reliability of the wiring substrate can be improved.

(Seventh embodiment)
In the present embodiment, a semiconductor module using the wiring board described in the first to sixth embodiments will be described. Here, as an example, a semiconductor module including the wiring substrate 100 will be described with reference to FIGS.

  A semiconductor module 200 illustrated in FIG. 29 includes a main substrate 202 and a plurality of wiring substrates 100-1, 100-2, and 100-3 stacked thereon. The number of wiring boards 100 is not limited and is determined according to the performance required for the semiconductor module 200. Various semiconductor chips (memory device, central processing unit) and semiconductor elements (such as micro electro mechanical system (MEMS)) (not shown) are connected to the main substrate 202. As described in the first embodiment, the wiring board 100 includes the first wiring 110, the lower wiring 112, and the upper wiring 114, which function as terminals in the semiconductor module 200. The first wiring 110 of the lowermost wiring substrate 100-1 is electrically connected to the terminal 204 provided on the main substrate 202 via the bump 206. Further, the laminated wiring boards 100-1, 100-2, 100-3 are also electrically connected by the bump 206. The bump 206 includes a metal such as indium, copper, or gold, or an alloy such as solder.

  Like the semiconductor module 210 shown in FIG. 30, the stacked wiring boards 100 may be different in size and shape, and the number of wiring boards 100 stacked on the main board 202 may be different. In the example shown in FIG. 30, two wiring boards 100-4 and 100-5 are stacked in some areas, and three wiring boards 100-1, 100-2, and 100-3 are stacked in some areas. Has been.

  A semiconductor module 220 shown in FIG. 31 has a structure in which a plurality of semiconductor chips (or semiconductor elements) 208-1 and 208-2 are stacked on the main substrate 202 via the wiring substrate 100. Terminals 212 and 213 are formed on the semiconductor chips 208-1 and 208-2, respectively, and these are electrically connected to the first wiring 110 and the upper wiring 114 of the wiring substrate 100 through the bumps 206. Thereby, the semiconductor chips 208-1 and 208-2 are electrically connected to each other. Further, the semiconductor chip 208-2 and the main substrate 202 may be electrically connected by the wire wiring 214.

  The embodiments described above as the embodiments of the present disclosure can be implemented in appropriate combination as long as they do not contradict each other. In addition, components that are appropriately added, deleted, or changed in design by those skilled in the art based on each embodiment are also included in the scope of the present disclosure as long as they include the gist of the present disclosure.

  Of course, other operational effects that are different from the operational effects provided by each of the above-described embodiments are obvious from the description of the present specification or can be easily predicted by those skilled in the art. It is understood that this disclosure provides.

  100: wiring substrate, 102: substrate, 104: through hole, 110: first wiring, 112: lower wiring, 114: upper wiring, 114-1: third wiring, 114-2: fifth wiring, 116 : Dielectric film, 116-1: first dielectric film, 116-2: second dielectric film, 118: first insulating film, 120: lower insulating film, 122: lead wiring, 122-1: Second wiring, 122-2: Fourth wiring, 122-3: Sixth wiring, 123: Upper electrode, 124: Seed layer, 126: Second insulating film, 128: Third insulating film, 130 : Resist, 131: resist mask, 132: seed layer, 134: seed layer, 140: photomask, 142: light shielding part, 150: wiring board, 160: wiring board, 170: wiring board, 180: wiring board, 200: Semiconductor module, 202: Mei Substrate, 204: Terminal, 206: bump, 208: semiconductor chip, 210: semiconductor module 212: Terminal, 213: Terminal, 214: wire wiring, 220: semiconductor module

Claims (41)

A substrate having a first surface and a second surface located opposite to the first surface, and having a through-hole penetrating from the first surface to the second surface;
A first wiring continuously covering the side wall of the through hole, the first surface, and the second surface;
A first dielectric film on the first wiring;
A first insulating film having an opening overlapping the first dielectric film on the first dielectric film;
A wiring board having a second wiring located on the first insulating film and overlapping the first wiring.   The wiring board according to claim 1, further comprising a metal layer in contact with the first dielectric film and the second wiring, between the first dielectric film and the second wiring.   The wiring board according to claim 1, wherein the second wiring covers the first insulating film. A second insulating film on the second wiring;
The wiring board according to claim 1, wherein the second insulating film has an opening overlapping the second wiring. A third wiring located on the substrate and present in the same layer as the first wiring;
A second dielectric film located on the third wiring and covered with the first insulating film;
2. The wiring board according to claim 1, further comprising a fourth wiring located on the first insulating film and overlapping the third wiring and the second dielectric film. A substrate having a first surface and a second surface located opposite to the first surface, and having a through-hole penetrating from the first surface to the second surface;
A first wiring continuously covering the side wall of the through hole, the first surface, and the second surface;
A first insulating film located on the first wiring and having an opening overlapping the first wiring;
A first dielectric film located on the first insulating film and covering the opening;
A wiring board having a second wiring located on the first dielectric film and overlapping the first wiring.   The wiring board according to claim 6, further comprising a metal layer in contact with the first dielectric film and the second wiring between the first dielectric film and the second wiring.   The wiring substrate according to claim 6, wherein the first dielectric film is in contact with a surface of the first insulating film located on a side opposite to the substrate.   The wiring board according to claim 6, wherein the second wiring covers the first insulating film.   The wiring board according to claim 6, further comprising a second insulating film that is located on the second wiring and has an opening overlapping the second wiring. A third wiring located on the substrate and in the same layer as the first wiring, and covered with the first insulating film;
A second dielectric film located on the first insulating film and overlapping the third wiring;
The wiring board according to claim 6, further comprising a fourth wiring located on the second dielectric film and overlapping the third wiring. A substrate having a first surface and a second surface located opposite to the first surface, and having a through-hole penetrating from the first surface to the second surface;
A first wiring continuously covering the side wall of the through hole, the first surface, and the second surface;
A first insulating film located on the substrate, in contact with the substrate, thinner than the first wiring, and covering the through hole;
A first dielectric film on the first wiring;
A wiring board having a second wiring located on the first dielectric film and overlapping the first wiring.   The wiring board according to claim 12, further comprising a metal layer in contact with the first dielectric film and the second wiring between the first dielectric film and the second wiring.   The wiring board according to claim 12, further comprising a second insulating film having an opening overlapping the second wiring on the second wiring.   The wiring board according to claim 14, further comprising a lead wiring that covers the opening on the second wiring. A third wiring located on the substrate and present in the same layer as the first wiring;
A second dielectric film on the third wiring;
The wiring board according to claim 12, further comprising a fourth wiring located on the second dielectric film and overlapping the third wiring. A substrate having a first surface and a second surface located opposite to the first surface, and having a through-hole penetrating from the first surface to the second surface;
A first wiring continuously covering the side wall of the through hole, the first surface, and the second surface;
A first dielectric film on the first wiring;
A second wiring located on the first dielectric film and overlapping the first wiring;
A first insulating film located on the second wiring and having an opening overlapping the second wiring;
A lower insulating film located on the second surface side of the substrate,
A wiring board in which the number of layers of the first insulating film and the number of layers of the lower insulating film are the same.   The wiring board according to claim 17, wherein the first insulating film and the lower insulating film have the same thickness.   The wiring board according to claim 17, wherein the second wiring covers a side surface of the first wiring. A third wiring located on the substrate and present in the same layer as the first wiring;
A second dielectric film located on the third wiring;
A fourth wiring positioned on the second dielectric film and overlapping the third wiring;
The wiring board according to claim 17, wherein the first insulating film covers the second dielectric film and a part of the fourth wiring. Forming a through-hole penetrating from the first surface to the second surface in a substrate having a first surface and a second surface located on the opposite side of the first surface;
Forming a first wiring so as to continuously cover the side wall of the through hole, the first surface, and the second surface;
Forming a first dielectric film on the first wiring;
Forming a first insulating film on the first dielectric film;
Forming an opening exposing the first dielectric film in the first insulating film;
A method for manufacturing a wiring board, comprising forming a second wiring covering the opening. Forming a metal film in contact with the first dielectric film on the first dielectric film;
The manufacturing method according to claim 21, wherein the second wiring is formed in contact with the metal film.   The manufacturing method according to claim 21, wherein the second wiring is formed so as to cover the first insulating film. Forming a second insulating film on the second wiring;
The manufacturing method according to claim 21, further comprising forming an opening in the second insulating film to expose the second wiring. Forming a third wiring on the substrate simultaneously with the first wiring;
Forming a second dielectric film on the third wiring simultaneously with the first dielectric film;
Forming a fourth wiring on the second dielectric film;
The first insulating film is formed so as to cover the second dielectric film, and has an opening overlapping the second dielectric film,
The manufacturing method according to claim 21, wherein the third wiring is formed so as to overlap with the fourth wiring in the opening overlapping with the second dielectric film. Forming a through-hole penetrating from the first surface to the second surface in a substrate having a first surface and a second surface located on the opposite side of the first surface;
Forming a first wiring so as to continuously cover the side wall of the through hole, the first surface, and the second surface;
Forming a first insulating film on the first wiring;
Forming an opening in the first insulating film to expose the first wiring;
Forming a first dielectric film covering the opening;
A method of manufacturing a wiring board, comprising: forming a second wiring overlapping the first wiring on the first dielectric film. Forming a metal film in contact with the first dielectric film on the first dielectric film;
27. The manufacturing method according to claim 26, wherein the second wiring is formed in contact with the metal film.   27. The manufacturing method according to claim 26, wherein the first dielectric film is formed so as to cover the first insulating film.   27. The manufacturing method according to claim 26, wherein the second wiring is formed so as to cover the first insulating film. Forming a second insulating film on the second wiring;
27. The manufacturing method according to claim 26, further comprising forming an opening exposing the second wiring in the second insulating film. Forming a third wiring on the substrate simultaneously with the first wiring;
Forming a second dielectric film on the third wiring simultaneously with the first dielectric film;
Forming a fourth wiring overlapping the third wiring on the second dielectric film;
The first insulating film is formed so as to cover the third wiring and has an opening overlapping the third wiring;
27. The manufacturing method according to claim 26, wherein the second dielectric film and the third wiring are formed so as to overlap with the opening overlapping with the third wiring. Forming a through-hole penetrating from the first surface to the second surface in a substrate having a first surface and a second surface located on the opposite side of the first surface;
Forming a first wiring so as to continuously cover the side wall of the through hole, the first surface, and the second surface;
Forming a first insulating film thinner than the first wiring on the substrate so as to be in contact with the substrate;
Forming a first dielectric film on the first wiring;
A method of manufacturing a wiring board, comprising: forming a second wiring overlapping the first wiring on the first dielectric film.   The manufacturing method according to claim 32, wherein the first insulating film is formed to cover the through hole. Forming a metal film in contact with the first dielectric film on the first dielectric film;
The manufacturing method according to claim 32, wherein the second wiring is formed so as to be in contact with the metal film. Forming a second insulating film on the second wiring;
The manufacturing method according to claim 32, further comprising forming an opening overlapping the second wiring in the second insulating film.   The manufacturing method according to claim 35, further comprising forming a lead wiring that covers the opening. Forming a third wiring on the substrate simultaneously with the first wiring;
Forming a second dielectric film on the third wiring simultaneously with the first dielectric film;
The manufacturing method according to claim 32, further comprising forming a fourth wiring that overlaps with the third wiring on the second dielectric film. Forming a through-hole penetrating from the first surface to the second surface in a substrate having a first surface and a second surface located on the opposite side of the first surface;
Forming a first wiring so as to continuously cover the side wall of the through hole, the first surface, and the second surface;
Forming a first dielectric film on the first wiring;
Forming a second wiring overlapping the first wiring on the first dielectric film;
Forming a first insulating film on the second wiring;
Forming a lower insulating film on the second surface side of the substrate;
A method of manufacturing a wiring board, wherein the number of layers of the first insulating film and the number of layers of the lower insulating film are the same.   The manufacturing method according to claim 38, wherein a thickness of the first insulating film and a thickness of the lower insulating film are the same.   39. The manufacturing method according to claim 38, wherein the second wiring is formed so as to cover a side surface of the first wiring. Forming a third wiring on the substrate simultaneously with the first wiring;
Forming a second dielectric film on the third wiring simultaneously with the first dielectric film;
39. The manufacturing method according to claim 38, further comprising forming a fourth wiring overlying the third wiring on the second dielectric film.

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