JP2011114233A - Laminated wiring board and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent disadvantages to capacitor characteristics and reliability that may be caused by the formation of fine unevenness to increase adhesion strength when using an interconnection layer of a laminated wiring board as a capacitor bottom electrode. <P>SOLUTION: On the surface of the interconnection layer 14 in a laminated board structure, fine unevenness is formed to obtain the adhesion strength when pasting the other insulation substrate 19a to an insulation substrate 10. On the interconnection layer 14 having the fine unevenness, a conductive layer 16 is formed. With the conductive layer 16 as a bottom electrode, a capacitive element composed of a capacitor dielectric film 17 and a top electrode 18 that are laminated on each other is formed on the bottom electrode. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a laminated wiring board in which a wiring layer and another insulating board are alternately and repeatedly laminated on one side or both sides of an insulating substrate and have a capacitive element therein, and a method for manufacturing the same.

Technological development for forming a parallel plate type capacitive element inside a multilayer wiring board such as a printed wiring board has been activated.
In many types of multilayer wiring boards, multilayer wiring boards are formed by alternately forming wiring layers and insulating layers on both sides of a core substrate.
In addition to improving general capacitive elements such as increasing capacitance, increasing accuracy, and reducing variation in capacitance values, eliminating the disadvantages associated with the inclusion in a multilayer wiring board is an issue to be addressed. It is done.

For high accuracy and large capacity, approach from high dielectric material (for example, Patent Document 1), dielectric film is formed by using the slope of insulating base material, and thereby capacity value per unit occupied area Is known (for example, Patent Document 2).
Further, as a contrivance of the base surface for forming a thin uniform capacitor dielectric film, a technique for flattening the upper surface of the insulating layer and the wiring layer (lower electrode) on which the capacitor dielectric film is formed is known (for example, a patent) Reference 3).

JP 2004-59716 A JP 2008-159686 A Japanese Unexamined Patent Publication No. 20000007-19530

In the case of attaching an insulating substrate for multilayering in a multilayer wiring board, conductive wiring is arranged with a considerable area occupancy on the attaching surface, so that adhesion between the substrates is improved when attaching. Need to increase. Therefore, a process for increasing the mechanical coupling strength is known as a technique for forming a fine unevenness on the surface of the wiring layer on the insulating substrate on the side where the wiring layer is formed, thereby providing a so-called anchor effect.
As a typical example, so-called blackening treatment and reduction treatment are known. In the blackening treatment, the surface of copper as wiring is oxidized to form fine needle crystals of copper oxide. The reduction treatment imparts acid resistance by performing a reduction treatment after the oxidation treatment. As a result, needle-like irregularities are formed on the surface of the copper wiring to provide an anchor effect, thereby improving the adhesion between the insulating substrates.
The technology for forming such fine irregularities is essential for the multilayer wiring board in the sense of preventing peeling at the interface between the core substrate and the insulating layer (generally a resin layer).

However, if there are needle-like irregularities on the surface of the lower electrode where the dielectric film of the capacitive element is formed, the characteristics and reliability of the capacitive element, such as an increase in leakage current due to electric field concentration, are greatly reduced.
As the dielectric film is made thinner in order to increase the capacity of the capacitive element, the increase in leakage current due to the needle-like unevenness becomes more remarkable.

Patent Document 3 has a description of blackening processing and reduction processing. The problem here is that the conductive pattern (lower electrode) is covered with a thermosetting insulating material and then polished to flatten the insulating material surface where the upper surface of the lower electrode of the capacitor element is exposed, and then blacken the flattened surface. Processing and reduction processing.
In this process, it is necessary to prevent peeling because the substrate resin is stuck on the substrate. However, in Patent Document 3, the surface is simultaneously the formation surface of the capacitor dielectric film. Can't escape.

  The present invention newly proposes a multilayer wiring board having a structure in which formation of fine irregularities that increase adhesion strength does not adversely affect capacitor characteristics and reliability when the wiring layer of the multilayer wiring board is used as a capacitor lower electrode. Is. Moreover, this invention provides the manufacturing method of the laminated wiring board for forming this structure.

  The multilayer wiring substrate according to the first aspect of the present invention has a multilayer substrate structure in which wiring layers and other insulating substrates are alternately stacked and bonded to an insulating substrate at least once. On the surface of the wiring layer in the multilayer substrate structure, fine irregularities are formed to ensure adhesion strength when another insulating substrate is bonded to the insulating substrate on which the wiring layer is formed. A conductive layer is formed on the wiring layer surface on which the fine irregularities are formed. A capacitive element in which the conductive layer is used as a lower electrode and a capacitor dielectric film and an upper electrode are stacked on the lower electrode is formed.

  The multilayer wiring board according to the second aspect of the present invention has a multilayer substrate structure in which wiring layers and other insulating substrates are alternately stacked and bonded to an insulating substrate at least once. A capacitor element in which a capacitor dielectric film and an upper electrode are laminated is formed on a wiring layer in the laminated substrate structure. Ensuring adhesion strength when another insulating substrate is bonded to the insulating substrate on which the wiring layer is formed on the upper surface region of the wiring layer other than the region where the capacitive element is formed and on the upper surface and side surfaces of the upper electrode. Fine irregularities are formed.

  In these laminated wiring boards, when the insulating substrates are bonded to each other, in one insulating substrate on which the wiring layer is formed, most of the surface of the wiring layer is formed with fine unevenness, so that sufficient peel strength ( Adhesion) is obtained. However, fine irregularities are not formed on the lower ground of the wiring layer or the like on which the capacitor dielectric film of the capacitive element is formed. For this reason, the characteristics and reliability of the capacitive element are high from the viewpoints of ensuring sufficient adhesion and, therefore, reducing leakage and variation in capacitance value.

The method for manufacturing a multilayer wiring board according to the third aspect of the present invention includes the following steps.
(A) A step of forming a wiring layer on the insulating substrate.
(B) A step of forming fine irregularities on the surface of the wiring layer.
(C) forming a conductive layer to be a lower electrode of the capacitive element on the wiring layer;
(D) depositing an insulating layer and planarizing the upper surface of the insulating layer and the conductive layer so that the height from the upper surface of the wiring layer is the same.
(E) A step of forming a capacitor element by laminating a capacitor dielectric film and an upper electrode on the planarized surface of the conductive layer.
(F) A step of adhering another insulating substrate to the insulating substrate while ensuring adhesion by the fine unevenness.

The manufacturing method of the multilayer wiring board according to the fourth aspect of the present invention includes the following steps.
(A) A step of forming a wiring layer on the insulating substrate.
(B) depositing an insulating layer and planarizing the upper surface of the insulating layer and the conductive layer.
(C) A step of forming a capacitor element by laminating a capacitor dielectric film and an upper electrode on the planarized surface of the conductive layer.
(D) A step of forming fine irregularities in the wiring layer region other than the region where the capacitive element is formed and the surface of the upper electrode.
(E) A step of adhering another insulating substrate to the insulating substrate while ensuring adhesion by the fine unevenness.

According to the present invention, when the wiring layer of the multilayer wiring board is used as a capacitor lower electrode, there is provided a multilayer wiring board having a structure in which formation of fine irregularities that increase adhesion strength does not adversely affect capacitor characteristics and reliability. be able to.
According to the present invention, it is possible to provide a method for manufacturing a multilayer wiring board for forming a structure having this advantage.

It is a schematic sectional drawing in the middle of formation of the printed wiring board containing the via | veer in connection with 1st Embodiment. It is sectional drawing in the middle of manufacture following FIG. It is sectional drawing in the middle of manufacture following FIG. It is sectional drawing of the laminated wiring board containing a capacitive element structure. It is sectional drawing in the middle of manufacture for demonstrating the manufacturing method of 1st Embodiment. It is sectional drawing in the middle of manufacture following FIG. It is sectional drawing in the middle of manufacture following FIG. It is sectional drawing in the middle of manufacture following FIG. It is sectional drawing in the middle of manufacture for demonstrating the manufacturing method of 2nd Embodiment. FIG. 10 is a cross-sectional view during manufacturing subsequent to FIG. 9. It is sectional drawing in the middle of manufacture following FIG. It is sectional drawing in the middle of manufacture following FIG.

Embodiments of the present invention will be described with reference to the drawings in the following order, taking a printed wiring board as an example.
1. First embodiment: an embodiment in which a lower electrode is laminated on a wiring layer on which fine irregularities are formed.
2. Second Embodiment: An embodiment in which fine irregularities are formed after forming a capacitive element.

<1. First Embodiment>
[Schematic manufacturing method of multilayer wiring board without capacitor details]
The feature of the present invention lies in the details of the capacitive element, particularly the lower electrode structure using the wiring layer of the multilayer wiring board. However, since the overall formation method of the multilayer wiring substrate does not appear in the drawings (to be described later) of the description, an outline of the premise substrate formation method will be described first with reference to FIGS.
The laminated wiring board to which the present invention is applied is a broad concept including a flexible board having a laminated structure, etc., but hereinafter, a printed wiring board is assumed.

1 to 3 are schematic cross-sectional views during the formation of a printed wiring board including vias.
A through-hole 10A is formed by drilling or laser processing (FIG. 1 (B)) on a core substrate (FIG. 1 (A)) in which copper foils 11a and 11b are bonded to both surfaces of the insulating substrate 10 (FIG. 1 (B)). Primary copper plating layers 12a to 12c are formed by electrolytic plating (FIG. 1C).

Patterning is performed with the resist 13 (FIG. 2A), and a wiring layer 14 is formed by selective plating (FIG. 2B).
After removing the resist 13 (FIG. 2C), the entire surface is etched to remove the primary copper plating layers 12a to 12c and the copper foils 11a and 11b to form a copper wiring (FIG. 3A). .

In FIG. 3B, a blackening process for forming needle-like irregularities on the surface of the copper wiring is performed to give an anchor effect. Subsequently, in FIG. 3C, the insulating substrates 19a and 19b and the copper foils 20a and 20b are bonded together by a laminating press using high-temperature pressurization.
Thereafter, through holes and contact holes are formed, and the laminated wiring board is formed so as to have a desired number of layers by repeating the steps after FIG.

  The above is the wiring formation method by the semi-additive construction method. Here, “semi-additive” refers to a case where the entire surface is etched to remove the primary copper plating layers 12a to 12c and the copper foils 11a and 11b in FIGS. 2 (C) to 3 (A). In addition, it means that the wiring layer (14) slightly recedes and a slight dimensional change (pattern shift) occurs.

  In the present embodiment, it is possible to adopt a full additive method as a similar forming method. In FIG. 1 (C), the full additive method performs only catalysis, and does not form the primary copper plating layers 12a to 12c to be plating seed layers. Thereafter, the resist 13 is patterned (FIG. 2A), and electroless plating is performed in FIG. 2B to form a wiring layer (14). In this method, since there is no plating seed layer, the entire surface etching shown in FIG. 3A is not performed, or when there are copper foils 11a and 11b as in this example, etching is extremely light. Therefore, the pattern shift of the wiring layer (14) hardly occurs. This is called “full additive”.

In this embodiment, a subtractive construction method can be adopted as another typical wiring formation method. In this method, copper wiring is formed by etching copper using a resist after copper plating. In this case, since wet etching is usually used, the pattern shift is large as compared with the above two other methods.
In any method, the process of forming needle-like irregularities on the surface of the copper wiring for improving the patterning adhesion (FIG. 3B) is common.

  As described above, since the thick copper layer is etched by the subtractive method, it is inevitable that the variation of the pattern becomes larger than other methods. The semi-additive method can increase the accuracy because etching after the conductor formation can be reduced, but deviation from the resist pattern occurs. The full additive method can form a conductor as the resist pattern. However, since plating takes a long time, a resist with high alkali resistance is required, and electroless copper plating must be continuously maintained in the same state. Management is difficult.

[Capacitance element structure]
FIG. 4 is a more detailed cross-sectional view showing the capacitive element structure. In FIG. 4, after forming fine needle-like irregularities on the surface of the wiring layer (14) of FIG. 3B, a capacitive element having an MIM structure is formed, and then the capacitive element is formed through the formation of an insulating substrate 19a. It is sectional drawing at the time of completing. Therefore, the same components as those in FIGS. 1 to 3 are denoted by the same reference numerals, and the description thereof is omitted.
A conductive layer 16 as the “conductive layer” of the present invention is formed on the wiring layer (14) in a smaller pattern in plan view. The conductive layer 16 is formed so as to be embedded in an insulating layer that embeds the upper surface of the wiring layer (14) and the separated portion of the wiring layer (14), for example, photosensitive polyimide 15 (hereinafter referred to as insulating layer (15)). . More specifically, since the height of the insulating layer (15) and the height of the conductive layer 16 are aligned on the upper surface of the wiring layer (14), the upper surfaces of both are flattened in the same plane.

A capacitor dielectric film 17 and an upper electrode 18 are stacked on the planarized surface of the conductive layer 16, thereby forming an MIM structure.
The capacitor dielectric film 17 and the upper electrode 18 have a slightly larger planar shape including the underlying conductive layer 16 in plan view.
Therefore, the effective capacitance portion of the MIM capacitor is determined by the area of the conductive layer 16 that defines the overlapping portion of the three members. Although details will be described later, the conductive layer 16 is obtained by transferring a mask pattern with high accuracy, so that variation in capacitance value is minimized.

The insulating substrate 19a (hereinafter also referred to as a substrate resin layer (19a)) as the “substrate resin layer” of the present invention is bonded to the core substrate (the insulating substrate 10 on which the copper foils 11a and 11b are formed) from the capacitive element side. ing.
Contact portions 21A and 21B are formed on the substrate resin layer (19a), and the electrodes of the capacitors are taken out.

  As is well known, in order to increase the accuracy of the capacitive element, it is necessary to reduce variations in the film thickness t of the capacitor dielectric film 17 and variations in the area S. In order to increase the capacity, it is necessary to reduce the dielectric film thickness t together with a material having a high dielectric constant ε.

The structure of this embodiment shown in FIG. 4 is not a wiring layer (14) provided with fine needle-like irregularities for improving substrate adhesion, but a capacitor dielectric film on the planarized surface of the conductive layer 16 thereon. 17 is formed. In addition, since the end portion of the capacitor dielectric film 17 extends from the upper surface of the conductive layer 16 to the upper surface of the insulating layer (15) having the same height, the capacitor dielectric film 17 is disposed straight in the cross section. That is, the capacitor dielectric film 17 is in a base environment where there is no film thickness fluctuation when overcoming a step and a uniform film can be easily formed over the entire area. Further, as described above, since the area of the effective capacitor is defined by the area of the upper surface of the conductive layer 16 having high pattern accuracy, the fluctuation of the capacitor area S is small.
As described above, the capacitance value of the capacitive element is easily set to a desired value as designed.

  As described above, in this capacitor structure, the capacitor dielectric film is formed on the uneven surface while avoiding minute unevenness for improving the substrate adhesion. For this reason, there is an advantage that the capacitor dielectric film 17 can be formed thin and uniformly. If the roughness of the base of the capacitor dielectric film 17 is small, it is possible to prevent the occurrence of a path where leakage is likely to increase due to unnecessary stress, which is advantageous for thinning.

Here, the capacitor dielectric film 17 is preferably formed of a crystalline metal oxide. This crystalline metal oxide has the property of exhibiting crystallinity (cubic crystal or monoclinic crystal) even at a temperature low enough to avoid the restriction of materializing the maximum heating temperature of the multilayer wiring board such as the insulating substrate 19a. The film is formed to have
On the other hand, the occurrence of leak paths along the grain boundaries is also well known. Therefore, this crystalline metal oxide does not require high annealing such as 400 to 450 [° C.] or substrate heating during film formation, and is practical dielectric constant within a range of 200 [° C.] or less and room temperature or more. While there is an advantage that the rate can be obtained, leakage is likely to occur as compared with an amorphous metal oxide.
In the present embodiment, since there is a structural feature in which leakage is not easily generated by smoothing the base of the capacitor dielectric film 17 while maintaining the substrate adhesion, the capacitor dielectric film 17 is formed from this crystalline metal oxide. It is desirable to do.

Further, at least the outermost surface of the conductive layer 16 can be made of sufficient capacitor dielectric film crystalline even with Cu, but may be nickel (Ni) or platinum (Pt).
Examples of the metal oxide will be described later.

[Manufacturing Method of Laminated Wiring Substrate Including Capacitor Element Formation]
FIG. 5A to FIG. 8B are cross-sectional views in the middle of manufacturing for explaining the manufacturing method of the first embodiment.
As shown in FIG. 5A, through holes or the like (not shown) are formed in the insulating substrate 10 in which the copper foils 11a and 11b are bonded to the front and back surfaces, and the primary copper plating layers 12a and 12b are formed on the copper foils 11a and 11b. Form.

  As shown in FIG. 5B, patterning is performed with a resist 13, and a wiring layer (14) is formed by selective plating. At this time, patterning with a resist (not shown) and a copper wiring layer are also formed on the back surface. In the following description, wiring formation on the back surface is not shown, but the same processing is performed on the back surface side simultaneously with the front surface side.

  As shown in FIG. 5C, after removing the resist 13, the entire surface is etched to remove the copper foil 11a and the primary copper plating layer 12a, and the exposed portion of the copper surface is not illustrated by blackening treatment or the like. Needle-shaped irregularities are formed.

  As shown in FIG. 5D, patterning is performed with, for example, photosensitive polyimide 15 and, for example, the conductive layer 16 is formed in a desired region in the capacitive element formation portion on the wiring layer (14) by selective plating. . Thereby, the lower electrode of the capacitive element is formed.

  As shown in FIG. 6A, the surface of the conductive layer 16 is polished by tape polishing, for example, to eliminate the needle-like irregularities on the copper surface, and at the same time, smoothing with the photosensitive polyimide 15 is performed. At this time, the wiring layer (14) is stepped from the lower electrode (conductive layer 16) of the capacitive element and is covered with the photosensitive polyimide 15, so that the needle-like irregularities on the surface are preserved.

  In the case of a damascene process in a semiconductor device, a wiring layer may be filled with an insulating film and smoothed, and a parallel plate capacitance may be formed on a smooth lower electrode on the surface. In this case, the effective capacitance element area is defined by the lower electrode area.

  In the printed wiring board, as can be seen from the manufacturing method of FIG. 5C to FIG. 6A, the wiring layer (14) and the insulating layer (photosensitive polyimide 15) thereon ensure adhesion, Needle-like irregularities need to be formed on the surface of the wiring layer (14). For this reason, the wiring layer (14) cannot be simply used as the lower electrode of the capacitor, and it is clear that an approach different from that of the capacitor element manufactured in the semiconductor device is necessary.

  As shown in FIG. 6B, a capacitor dielectric film 17 is formed on the conductive layer 16 of the capacitive element. As a method of forming the capacitor dielectric film 17, for example, a method of selectively forming a film by a sputtering method using a metal mask can be used.

  As shown in FIG. 6C, the upper electrode 18 is formed on the capacitor dielectric film 17 of the capacitive element. As a method of forming the upper electrode 18, selective plating by resist patterning may be used. For example, a method of selectively forming a film by sputtering using a metal mask may be used. The surface of the upper electrode 18 is formed with needle-like irregularities (not shown) by blackening treatment or the like.

  As shown in FIG. 7A, the insulating substrate 19 and the copper foil 20a are bonded together by a lamination press. At this time, an insulating substrate (not shown) and a copper foil are bonded to the back surface.

As shown in FIG. 7B, the insulating substrate 19a and the copper foil 20a are opened by laser processing in order to form the upper electrode 18 of the capacitive element and the contact portions 21A and 21B of the wiring layer (not shown).
As shown in FIG. 7C, a primary copper plating layer 22 is formed.

As shown in FIG. 8A, patterning is performed with a resist 23, and a copper wiring layer 24 is formed by selective plating.
As shown in FIG. 8B, after removing the resist 23, the entire surface is etched to remove the copper foil 20a and the primary copper plating layer 22 to form a copper wiring, thereby completing the basic structure of the capacitive element. To do.

Incidentally, as the material of the capacitor dielectric film 17 may be, for example, _{SiO 2, Si 3 N 4,} Al 2 O 3, HfO 2, ZrO 2, Ta 2 O 5, STO, BTO, a material such as BST. These dielectric materials have a relative dielectric constant of 4 to 400. When such a material is used to incorporate a capacitive element in a printed wiring board, the thickness of the capacitor dielectric film 17 is preferably about 20 to 1000 [nm].

  According to the first embodiment of the present invention, by forming the dielectric film and the upper electrode so as to include the lower electrode, the effective area of the capacitive element is made the lower electrode formed by the plating resist using the mask. And can be defined almost according to the mask dimensions. Also, by polishing so that the upper surface of the lower electrode and the upper surface of the insulating layer (plating resist) are at the same height, damage due to the formation of needle-like irregularities on the surface of the lower electrode as a capacitive element can be avoided, In addition, since the surface of the conductive layer is not smoothed, the needle-like irregularities for ensuring adhesion with the insulating film are protected, and the thickness of the conductor does not change, so it can be used as an inductor forming layer. it can.

<2. Second Embodiment>
FIG. 9A to FIG. 12B are cross-sectional views in the middle of manufacturing for explaining the manufacturing method of the second embodiment. In addition, the same code | symbol is attached | subjected to the structure which is common in 1st Embodiment, and description is abbreviate | omitted.

[Capacitance element structure]
First, the structure will be described with reference to FIG.
A wiring layer (14) is formed on one surface of the insulating substrate 10. An adjacent wiring layer that is formed of the same material and the same thickness as the wiring layer (14) is indicated by reference numeral “(14c)”. In the first embodiment, the insulating layer (15) made of photosensitive polyimide or the like is formed up to a position higher than the upper surface of the wiring layer (14). In contrast, in the second embodiment, the insulating layer (15) is embedded between the conductive layers, and the upper surfaces of the photosensitive polyimide 15, the wiring layer (14) and the wiring layer (14c) on both sides are flattened. .

The capacitor dielectric film 17 and the upper electrode 18 are laminated on the planarized surface of the wiring layer (14) to form a capacitive element.
Part of the capacitor dielectric film 17 and the upper electrode 18 extends on the planarized surface of the insulating layer (15). For this reason, the effective capacitor area of the capacitive element is determined by the area of the upper surface of the wiring layer (14).
In addition, the point that the insulating substrate 19a is bonded and the electrode is taken out is the same as in the first embodiment.

[Manufacturing Method of Laminated Wiring Substrate Including Capacitor Element Formation]
As shown in FIG. 9A, through holes and the like (not shown) are formed in the insulating substrate 10 to which the copper foils 11a and 11b are bonded, and the primary copper plating layers 12a and 12b are formed on the copper foils 11a and 11b. .

  As shown in FIG. 9B, patterning is performed with a resist 13, and a wiring layer (14) is formed by selective plating. At this time, patterning with a resist (not shown) and a copper wiring layer are also formed on the back surface. In the following description, wiring formation on the back surface is not shown, but it is performed on the back surface side simultaneously with the front surface side.

  As shown in FIG. 9C, after the resist 13 is removed, in order to remove the copper foil 11a and the primary copper plating layer 12a, the entire surface is etched to form a copper wiring.

As shown in FIG. 9D, for example, an insulating layer 15 is formed.
As shown in FIG. 10A, the surfaces of the insulating layer 15 and the copper wirings (14) and (14c) are smoothed by, for example, tape polishing.
As shown in FIG. 10B, the capacitor dielectric film 17 is formed on the lower electrode (wiring layer (14)) of the capacitive element. As a method of forming the capacitor dielectric film 17, for example, a method of selectively forming a film by a sputtering method using a metal mask can be used.

  As shown in FIG. 10C, the upper electrode 18 is formed on the capacitor dielectric film 17 of the capacitive element. As a method of forming the upper electrode 18, selective plating by resist patterning may be used. For example, a method of selectively forming a film by sputtering using a metal mask may be used. The upper electrode 18 and the surfaces of the copper wirings (14) and (14c) form needle-like irregularities (not shown) by blackening treatment or the like.

  As shown in FIG. 11A, the insulating substrate 19a and the copper foil 20a are bonded together by a lamination press. At this time, an insulating substrate (not shown) and a copper foil are bonded to the back surface.

As shown in FIG. 11B, the insulating substrate 19a and the copper foil 20a are opened by laser processing in order to form the upper electrode 18 of the capacitive element and the contact portions 21A and 21B of the copper wiring layer (not shown).
As shown in FIG. 11C, a primary copper plating layer 22 is formed.

As shown in FIG. 12A, patterning is performed with a resist 23, and a copper wiring layer 24 is formed by selective plating.
As shown in FIG. 12B, after removing the resist 23, the entire surface is etched to remove the copper foil 20a and the primary copper plating layer 22, thereby forming a copper wiring.

Incidentally, as the material of the capacitor dielectric film 17 may be, for example, _{SiO 2, Si 3 N 4,} Al 2 O 3, HfO 2, ZrO 2, Ta 2 O 5, STO, BTO, a material such as BST. These dielectric materials have a relative dielectric constant of 4 to 400. When such a material is used to incorporate a capacitive element in a printed wiring board, the thickness of the capacitor dielectric film 17 is preferably about 20 to 1000 [nm].

In the present embodiment, the formation of the dielectric film is not limited to the sputtering method using a metal mask. In the present embodiment, the method for forming the upper electrode is not limited to the sputtering method using a metal mask.
Also in this embodiment, as in the first embodiment, the capacitor dielectric film 17 may be formed so as to include a crystalline metal oxide, for example, at a temperature lower than the heat resistance temperature of the insulating substrate and higher than the room temperature.

According to the second embodiment, the number of steps of forming the conductive layer is smaller than that of the first embodiment, and thus the cost can be reduced accordingly.
Note that the capacitance formed in the first embodiment can be effectively used as a decoupling capacitor, for example.

  DESCRIPTION OF SYMBOLS 10,19a ... Insulating substrate, 12a, 12b ... Primary copper plating layer, 14, 14c ... Wiring layer, 15 ... Insulating layer, 16 ... Conductive layer, 17 ... Capacitor dielectric film, 18 ... Upper electrode, 19a ... Insulating substrate.

Claims (13)

It has a laminated substrate structure in which a wiring layer and another insulating substrate are alternately stacked and bonded to an insulating substrate at least once,
Fine irregularities are formed on the surface of the wiring layer in the multilayer substrate structure to ensure adhesion strength when another insulating substrate is bonded to the insulating substrate on which the wiring layer is formed,
A conductive layer is formed on the wiring layer surface on which the fine irregularities are formed,
A laminated wiring board in which a capacitor element in which a conductive dielectric layer is used as a lower electrode and a capacitor dielectric film and an upper electrode are laminated on the lower electrode is formed. An insulating layer whose upper surface is planarized so as to have the same thickness as the conductive layer on the wiring layer is interposed between the insulating substrate and the other insulating substrate,
The multilayer wiring board according to claim 1, wherein the capacitor dielectric film and the upper electrode are laminated on a planarized upper surface of the insulating layer and the conductive layer. The multilayer wiring board according to claim 2, wherein the capacitor dielectric film includes a crystalline metal oxide. The multilayer wiring board according to claim 2, wherein a multilayer body of the capacitor dielectric film and the upper electrode has a planar view shape including a planarized upper surface of the conductive layer. In the region of the insulating substrate different from the formation region of the capacitive element,
Coil lower wiring having the same material and the same thickness as the wiring layer and having fine irregularities formed on the surface,
2. An inductor having a two-layer coil wiring with a coil upper wiring having the same material and thickness as the conductive layer on the coil lower wiring and having no fine irregularities formed on the surface is disposed. The laminated wiring board described. It has a laminated substrate structure in which a wiring layer and another insulating substrate are alternately stacked and bonded to an insulating substrate at least once,
A capacitor element in which a capacitor dielectric film and an upper electrode are stacked on the wiring layer in the multilayer substrate structure is formed,
Ensuring adhesion strength when another insulating substrate is bonded to the insulating substrate on which the wiring layer is formed on the upper surface region of the wiring layer other than the region where the capacitive element is formed and on the upper surface and side surfaces of the upper electrode. A multilayer wiring board with fine irregularities. An insulating layer is embedded between the wiring layer and another wiring layer in the same level, and the upper surface of the insulating layer and the wiring layer is planarized,
The laminate of the capacitor dielectric film and the upper electrode includes a planarized upper surface of the conductive layer, and has a planar view shape in which a part extends on the planarized surface of the adjacent insulating layer. The multilayer wiring board according to claim 6. Forming a wiring layer on an insulating substrate;
Forming fine irregularities on the surface of the wiring layer;
Forming a conductive layer to be a lower electrode of a capacitive element on the wiring layer;
Depositing an insulating layer and planarizing the upper surface of the insulating layer and the conductive layer so that the height from the upper surface of the wiring layer is the same;
Laminating a capacitor dielectric film and an upper electrode on the planarized surface of the conductive layer to form a capacitive element;
Securing adhesion by the fine irregularities and bonding another insulating substrate to the insulating substrate;
A method for manufacturing a laminated wiring board including: The method for manufacturing a multilayer wiring board according to claim 8, wherein the capacitor dielectric film includes a crystalline metal oxide formed at a temperature lower than a heat resistant temperature of the insulating substrate and higher than a room temperature. The capacitor dielectric film and the upper electrode are patterned so as to have a planar view shape including a flattened upper surface of the conductive layer when the capacitor dielectric film and the upper electrode are stacked. The manufacturing method of the multilayer wiring board of Claim 8. Forming a wiring layer on an insulating substrate;
Depositing an insulating layer and planarizing the upper surface of the insulating layer and the conductive layer;
Laminating a capacitor dielectric film and an upper electrode on the planarized surface of the conductive layer to form a capacitive element;
Forming fine irregularities on the wiring layer region other than the region where the capacitive element is formed and on the surface of the upper electrode;
Securing adhesion by the fine irregularities and bonding another insulating substrate to the insulating substrate;
A method for manufacturing a laminated wiring board including: The method for manufacturing a multilayer wiring board according to claim 11, wherein the capacitor dielectric film includes a crystalline metal oxide formed at a temperature lower than a heat resistant temperature of the insulating substrate and higher than a room temperature. The capacitor dielectric film and the upper electrode are patterned so as to have a planar view shape including a flattened upper surface of the wiring layer when the capacitor dielectric film and the upper electrode are stacked. The manufacturing method of the multilayer wiring board of 11.

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