JP2018200911A - Glass circuit board and manufacturing method thereof - Google Patents

Abstract

To provide a built-in capacitor glass circuit board of high yield in manufacturing process, and having a thin film capacitor of a MIM structure having high electrical reliability.SOLUTION: In a glass circuit board including a build-up layer laminating conductor circuit layers 105 and insulation resin layers 131 alternately, at least on one side of a glass base material 100 capable of conducting the front and rear via a through hole 101, a MIM capacitor 132 is provided between lower and upper conductor circuit layers adjoining via the insulation resin layer. The MIM capacitor includes a part of the conductor circuit layer on the underside of the insulation resin layer, a dielectric layer 111, and an upper electrode layer 114. The upper electrode layer is connected with the conductor circuit layer provided on the upper side of the insulation resin layer, and a part of the sectional end of the dielectric layer has a forward tapered shape.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a glass circuit board with a built-in capacitor and a method for manufacturing the same.

  With the increase in functionality and miniaturization of electronic devices, there is an increasing demand for higher density wiring boards that constitute semiconductor devices. In response, miniaturization of passive components such as resistors, capacitors, and inductors is required in accordance with miniaturization of circuit wiring. There is a demand for further miniaturization at a very high level, and there is a limit only to miniaturization of these passive components and high-density mounting on the substrate surface. In order to solve such problems, a technique for incorporating a passive element in a mounting substrate has been proposed (Patent Document 1). In the method of Patent Document 1, passive elements are formed by printing, vacuum film formation, or the like, so that they can be built in a multilayer substrate and miniaturized. Furthermore, since the wiring length can be shortened by forming the passive element in the multilayer substrate, high-frequency noise can be reduced.

  On the other hand, an organic material typified by glass epoxy resin is generally used as the material of the substrate. However, due to the recent progress in the drilling technology for glass, for example, a small through-hole of 100 μm or less for 300 μm thick glass. Holes can be formed with a pitch of 150 μm or less. For this reason, electronic circuit boards using glass materials have attracted attention.

  A circuit board using a glass material as a core (hereinafter referred to as a glass circuit board) has a low coefficient of linear thermal expansion (CTE) of 2 ppm to 8 ppm, and is matched with a silicon chip for high mounting reliability and flatness. High-precision mounting is possible because of its superiority. In addition, since it is excellent in flatness, it is excellent in fine wiring formability and high-speed transmission property. In addition, applications to electronic circuit boards that take advantage of the transparency, chemical stability, high elasticity, and low cost of glass have been studied. For semiconductor device interposers, image sensor circuit boards, and communication equipment. Commercialization of LC demultiplexers (duplexers) is expected. Since there is a need to form a decoupling capacitor, an LC circuit, and the like in these electronic circuits having a glass core, there is an increasing demand for incorporating a capacitor.

  However, a conventional capacitor built-in substrate has been formed by providing a cavity in an organic substrate and embedding a chip capacitor. In this method, since the occupied volume of the chip capacitor is increased, there is a problem in that wiring is restricted. Further, when the core substrate is an organic substrate, there is a problem that the flatness of the substrate is lowered due to the embedding of the chip capacitor. Further, there is a problem that the connection reliability is lowered due to the difference in linear thermal expansion coefficient with the chip component.

  Further, when a capacitor having a MIM structure (Metal Insulator Metal) is built in a multilayer circuit using an organic core substrate, the linear thermal expansion coefficient of the organic core substrate is larger than that of a dielectric layer having a MIM structure. The dielectric layer peels off due to the thermal cycle, or a crack occurs in the dielectric layer. For this reason, there has been a problem of reduced reliability due to occurrence of short circuit or open failure of the capacitor.

JP 2000-151114 A

  The present invention has been made in order to solve the above-described problems, and has a thin film capacitor having an MIM structure (referred to as an MIM capacitor) that enables downsizing, thinning, and high reliability of electronic circuits and electronic devices. It is an object to provide a glass circuit board with a built-in capacitor. It is another object of the present invention to manufacture a capacitor built-in glass circuit board having the MIM capacitor with a high yield.

As means for solving the above-mentioned problems, the invention according to claim 1 of the present invention is characterized in that a conductive circuit layer and an insulating resin layer are alternately arranged on at least one surface of a glass substrate that can be electrically connected through the through-hole. In a glass circuit board with a build-up layer laminated to
An MIM capacitor is provided between the lower and upper conductor circuit layers adjacent via the insulating resin layer,
The MIM capacitor includes a part of the lower conductor circuit layer, a dielectric layer, and an upper electrode layer.
The upper electrode layer is connected to the conductor circuit layer provided on the upper side of the insulating resin layer,
A cross-sectional end portion of the dielectric layer is a glass circuit board characterized in that a part thereof has a forward tapered shape.

The invention described in claim 2 is a glass comprising a build-up layer in which a conductor circuit layer and an insulating resin layer are alternately laminated on at least one surface of a glass base material capable of conducting both front and back through a through hole. In the circuit board,
An MIM capacitor is provided between the lower and upper conductor circuit layers adjacent via the insulating resin layer,
The MIM capacitor includes a part of the conductor circuit layer below the insulating resin layer, a dielectric layer, and an upper electrode layer.
The upper electrode layer is connected to the conductor circuit layer on the upper side of the insulating resin layer,
The cross-sectional end of the dielectric layer is a glass circuit board characterized in that all of them have a forward tapered shape.

  The invention according to claim 3 is the glass circuit board according to claim 1 or 2, wherein the upper electrode layer is provided inside the dielectric layer in a plan view.

  The invention according to claim 4 is characterized in that the dielectric layer is provided inside the lower conductor circuit layer in plan view. It is a glass circuit board.

According to a fifth aspect of the present invention, there is provided a lower adhesion layer between the lower conductor circuit layer and the dielectric layer, and an upper adhesion layer between the upper conductor circuit layer and the dielectric layer. In the MIM capacitor having
The lower adhesion layer and the upper adhesion layer are made of the same material,
2. The upper electrode layer and the upper adhesion layer have the same shape in plan view, and the lower adhesion layer and the lower surface of the dielectric layer in contact with the layer have the same shape in plan view. It is a glass circuit board in any one of -4.

The invention according to claim 6 is a method of manufacturing a glass circuit board having a built-in MIM capacitor,
Forming a through hole in the glass substrate;
A step of repeating a step of forming a conductor circuit layer, a step of forming an insulating resin layer, and a step of forming a via in the insulating resin layer as many times as necessary in this order,
Forming a MIM capacitor in a part of the conductor circuit layer in step A, and
The process of forming the MIM capacitor is as follows:
Forming a lower adhesion layer and a dielectric layer in this order at a portion of the conductor circuit layer forming the MIM capacitor;
Forming a resist pattern A on the dielectric layer;
Removing the dielectric layer using the resist pattern A as an etching mask;
Removing the resist pattern A;
Forming an upper adhesion layer and a seed metal layer in this order;
Forming a resist pattern B on the seed metal layer;
Forming a top electrode layer by electrolytic plating using the seed metal layer as an electrode;
Removing the resist pattern B;
Removing the seed metal layer using the upper electrode layer as an etching mask;
Removing the upper adhesion layer using the seed metal layer as an etching mask, and further removing the lower adhesion layer using the dielectric layer as an etching mask.
The step of removing the dielectric layer is a method of manufacturing a glass circuit board using dielectric layer removing means in which the shape of the end portion of the dielectric layer is a forward tapered shape.

  The invention according to claim 7 is the method for producing a glass circuit board according to claim 6, wherein the same material is used for the upper adhesion layer and the lower adhesion layer.

  The invention according to claim 8 is characterized in that the resist pattern A is formed so that the upper electrode layer is formed inside the dielectric layer in plan view. It is a manufacturing method of the glass circuit board of description.

  The invention according to claim 9 is characterized in that the resist pattern B is formed so that the dielectric layer is formed inside a conductor circuit layer forming the MIM capacitor in plan view. It is a manufacturing method of the glass circuit board in any one of claim | item 6 -8.

  According to the glass circuit board with a built-in capacitor according to the present invention, since a glass having a low coefficient of linear thermal expansion and a high elastic modulus is used as a base material, it is possible to manufacture an electronic component with little dimensional variation due to thermal cycling. Therefore, it is possible to ensure the connection reliability of the electronic circuit constituting the electronic component and the connection reliability of the external connection terminal when the heat cycle is applied.

  Further, the built-in capacitor of the glass circuit board with built-in capacitor according to the present invention includes a lower electrode region in the conductor circuit layer, a dielectric layer formed on the lower electrode layer, and an upper electrode layer formed on the dielectric layer. And the end shape of the dielectric layer has a forward taper shape at least partially from the glass substrate surface toward the far surface of the glass substrate, so that the upper electrode layer can be formed with high yield. And the variation in thickness can be reduced. Therefore, it is possible to provide a capacitor-embedded glass circuit board with high electrical reliability at a high yield.

It is the schematic sectional drawing which illustrated a series of manufacturing processes of a conductor circuit layer among manufacturing methods of a glass circuit board with a built-in capacitor concerning an embodiment of the present invention. FIG. 2 is an explanatory diagram illustrating a series of manufacturing steps of the MIM capacitor by enlarging and displaying a side cross section of the MIM capacitor forming portion A of FIG. 1. It is the schematic sectional drawing which showed the structural example of the glass circuit board with a built-in capacitor in this invention. It is the schematic sectional drawing which showed the structural example of the glass circuit board with a built-in capacitor in this invention. It is the schematic sectional drawing which showed the structural example of the glass circuit board with a built-in capacitor in this invention.

The glass circuit board with a built-in capacitor according to the present invention has a glass circuit provided with a build-up layer in which a conductor circuit layer and an insulating resin layer are alternately laminated on at least one surface of a glass base material capable of conducting through the through hole. It is a substrate.
The glass circuit board with a built-in capacitor according to the present invention is characterized in that an MIM capacitor is provided between the lower and upper conductor circuit layers adjacent to each other via an insulating resin layer.
In the glass circuit board with a built-in capacitor according to the present invention, the MIM capacitor includes a part of the lower conductor circuit layer, a dielectric layer, and an upper electrode layer.
The upper electrode layer is connected to a conductor circuit layer provided on the upper side of the insulating resin layer. In addition, a part of the cross-sectional end of the dielectric layer has a forward taper shape.
Moreover, in the glass circuit board with a built-in capacitor according to the present invention, the entire cross-sectional end of the dielectric layer may have a forward taper shape.

  Hereinafter, the glass circuit board with a built-in capacitor according to the first embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 1 is an explanatory view showing a series of manufacturing steps of a conductor circuit layer in which one wiring layer (conductor circuit layer) is formed immediately above the glass substrate 100 according to the first embodiment of the glass circuit substrate with a built-in capacitor of the present invention. FIG.
FIG. 2 is an explanatory view for explaining a series of manufacturing steps for forming an MIM capacitor in the MIM capacitor forming portion A which is a part of the conductor circuit layer formed on the glass circuit board of FIG.
3 to 5 are sectional views showing structural examples of the capacitor built-in glass circuit boards 200, 201, and 202 in the present invention.

  In the following description, the same elements or parts having the same function are denoted by the same reference numerals, and redundant description is omitted.

  As shown to Fig.1 (a), the glass base material 100 is prepared. The glass substrate 100 is a transparent glass material having optical transparency. There are no particular limitations on the glass component or the blending ratio of each component contained in the glass, and the method for producing the glass. For example, examples of the glass include alkali-free glass, alkali glass, borosilicate glass, quartz glass, sapphire glass, and photosensitive glass, but any glass material containing silicate as a main component may be used. Furthermore, other so-called glass materials may be used. However, it is desirable to use non-alkali glass for semiconductor applications according to the present invention. Further, the thickness of the glass substrate 100 is preferably 1 mm or less, but is more preferably 0.1 mm or more and 0.8 mm or less in consideration of the ease of the glass through-hole forming process and the handleability during production.

  Examples of the method for producing the glass substrate 100 include a float method, a downdraw method, a fusion method, an updraw method, a rollout method, and the like, and a glass material produced by any method may be used. It is not limited by. The linear expansion coefficient of the glass is desirably −1 ppm / K or more and 15.0 ppm / K or less. If it is −1 ppm / K or less, it is difficult to select the glass material itself and it becomes impossible to produce it at low cost. When it is 15.0 ppm / K or more, the difference in thermal expansion coefficient from other layers is large, and the reliability is lowered. Further, when a silicon chip is mounted on the substrate of the present invention, the connection reliability with the silicon chip is lowered. More preferably, it is 0.5 ppm / K or more and 8.0 ppm / K or less, and further preferably 1.0 ppm / K or more and 4.0 ppm / K or less.

  In addition, a functional film such as an antireflection film or an IR cut filter may be formed on the glass substrate 100 in advance. Further, functions such as strength imparting, antistatic imparting, coloring, and texture control may be imparted. Examples of these functional films include a hard coat film for imparting strength, an antistatic film for imparting antistatic, an optical filter film for coloring, an antiglare, and a light scattering film for texture control. Not as long. As a method for forming these functional films, film forming techniques such as vapor deposition, sputtering, and wet method are used.

Subsequently, as described in FIG. 1B, a through hole 101 is formed in the glass substrate 100. The cross-sectional shape and diameter of the through hole 101 are not limited by the present invention. For example, a shape in which the diameter of the central portion is narrower than the top diameter and the bottom diameter of the through hole 101 may be used, or a shape in which the bottom diameter is smaller than the top diameter may be used. Further, the shape may be such that the diameter of the central portion is wider than the top diameter and the bottom diameter of the through hole 101. Known methods for forming the through hole 101 include laser processing, electric discharge processing, and chemical etching processing using sand blast processing, dry etching, hydrofluoric acid or the like when a photosensitive resist material is used. Furthermore, it is possible to produce a glass core using photosensitive glass. Laser processing and electric discharge processing are preferable because they are simple and have high throughput. The laser that can be used can be selected from a CO ₂ laser, a UV laser, a picosecond laser, a femtosecond laser, and the like.

Subsequently, as shown in FIG. 1C, a seed metal layer 102 is formed on the surface of the glass substrate 100 on which the through hole 101 is formed and in the through hole 101. The seed layer metal layer 102 functions as a power feeding layer for electrolytic plating in the wiring formation process in the semi-additive method. The seed metal layer 102 provided directly on the glass substrate 100 and on the inner wall of the through hole 101 is formed by, for example, a sputtering method or a CVD method. For example, Cu, Ni, Al, titanium, Cr, Mo, W, Ta, Single substance selected from Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, titanium N, Cu ₃ N ₄ , Cu alloy, etc., or a combination thereof Can be applied. In the present invention, in consideration of electrical characteristics, ease of production and cost, a titanium layer having good adhesion to glass and then a copper layer are sequentially formed by a sputtering method. The total film thickness of the titanium and copper layers for circuit formation on the glass substrate is preferably 1 μm or less because it is advantageous for forming fine wiring by the semi-additive method. When it is thicker than 1 μm, it is difficult to form fine wiring with a pitch of 30 μm or less.

  After the titanium and copper layers are formed on the glass substrate, an electroless plating layer is formed. When only the titanium and copper layers are formed by the sputtering method, a metal film cannot be formed in the entire inside of the through hole 101, and the connection reliability of the through hole 101 is lowered. According to the present invention, the connection reliability of the through hole 101 can be improved by reinforcing the metal layer in the through hole 101 by the electroless plating method. Examples of the electroless plating layer include electroless copper plating and electroless nickel plating, but electroless nickel plating is performed because of good adhesion to glass, titanium, and copper layers. When the nickel plating layer is thick, not only is it difficult to form fine wiring, but also the adhesiveness is lowered due to an increase in film stress. Therefore, the electroless nickel plating thickness is desirably 1 μm or less. Moreover, More preferably, it is 0.5 micrometer or less, More preferably, it is 0.3 micrometer or less. The electroless nickel plating film may contain phosphorus, which is a eutectoid derived from a reducing agent, sulfur, lead, bismuth, and the like contained in the electroless nickel plating solution. Through the above steps, a substrate (FIG. 1C) in which the seed metal layer 102 is formed on the glass substrate in which the through hole 101 is formed is obtained.

Subsequently, as described in FIG. 1D, a photoresist pattern 103 is formed. A method for forming the photoresist pattern 103 will be described. First, a photoresist layer is formed on the entire surface of the seed metal layer 102. The photoresist layer to be formed includes a negative dry film resist, a negative liquid resist, and a positive liquid resist. However, since the formation of the photoresist layer is simple and inexpensive, a negative photoresist is desirable. Examples of the method for forming the resist layer include a roll laminating method and a vacuum laminating method in the case of a negative dry film resist. In the case of a liquid negative type or positive type resist, it can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating and doctor coating. The method for forming these resist layers is not limited by the present invention.

  Subsequently, a desired circuit pattern is formed on the photoresist layer by a known photolithography method. The resist pattern 103 is patterned by exposing, developing, and aligning so that a portion where a later electrolytic plating layer is formed is exposed. The thickness of the photoresist layer depends on the thickness of the electroplating in the subsequent process, but is preferably 5 μm or more and 25 μm or less. When the thickness is less than 5 μm, the electrolytic plating layer serving as the conductor circuit layer cannot be made 5 μm or more, and the connection reliability of the circuit may be lowered. When it becomes thicker than 25 μm, it becomes difficult to form fine wiring with a pitch of 30 μm or less. In this way, a glass substrate on which the photoresist pattern 103 is formed as shown in FIG.

  Subsequently, as shown in FIG. 1E, an electrolytic plating layer 104 is formed by an electrolytic plating method. Electrolytic plating methods include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, electrolytic iridium plating, etc. Electrolytic copper plating is simple and inexpensive, This is desirable because of its good conductivity. The thickness of the electrolytic copper plating is desirably 3 μm or more and 30 μm or less. In the case of 3 μm or less, there is a risk that the circuit may be lost depending on the subsequent etching process, and there is a risk that the connection reliability and electrical conductivity of the circuit will be lowered. When the electrolytic copper plating thickness is 30 μm or more, it is necessary to form a resist layer having a thickness of 30 μm or more, which increases manufacturing costs. Furthermore, since the resist resolution is lowered, it becomes difficult to form fine wiring with a pitch of 30 μm or less. More preferably, they are 5 micrometers or more and 25 micrometers or less, More preferably, they are 10 micrometers or more and 20 micrometers or less.

  Subsequently, as shown in FIG. 1F, the resist layer 103 that is no longer necessary after the wiring is formed by electrolytic plating is removed, and the seed metal layer 102 is exposed. Although the resist removal method is not limited in the present invention, it can be removed by, for example, an alkaline aqueous solution.

  Subsequently, as shown in FIG. 1 (g), the seed metal layer 102 is removed, and the circuit by electrolytic copper plating is electrically separated, whereby the conductor circuit layer is formed on the glass substrate on which the through hole is formed. Form. The seed metal layer removing method is not limited by the present invention, but a method of sequentially removing the electroless Ni layer, the copper layer, and the titanium layer by chemical etching can be used. The kind of etching solution is appropriately selected depending on the metal species to be removed, and is not limited by the present invention.

Next, referring to FIG. 2, the manufacturing method of the MIM (Metal Insulator Metal) capacitor according to the present invention will be described with reference to FIG. 2 which is an enlarged view of the MIM capacitor forming portion which is an encircled portion indicated by A in FIG. explain. FIG. 2 shows an example of forming an MIM capacitor on a copper conductor circuit formed on a glass substrate, but the present invention is not limited to producing an MIM capacitor directly on a glass circuit substrate. That is, a multilayer circuit may be formed by repeating circuit formation after forming an insulating resin layer on a glass circuit board on which a conductor circuit is formed, and an MIM capacitor may be formed on an arbitrary wiring layer in the multilayer circuit.

  FIG. 2A shows a part of the conductor circuit layer 105. Subsequently, as shown in FIG. 2B, a lower adhesion layer 110 and a dielectric layer 111 are sequentially deposited over the entire surface of the conductor circuit layer 105. Examples of the method for forming the layer include a vacuum deposition method, a sputtering method, an ion plating method, an MBE method, a laser ablation method, and a CVD method, but are not limited in the present invention.

  The lower adhesion layer 110 under the dielectric layer 111 is a layer that improves the adhesion between the dielectric layer 111 and the conductor circuit layer 105. For example, Cu, Ni, Al, titanium, Cr, Mo, W, Ta, A simple substance such as Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, Cu alloy, or a combination of them can be applied. In the present invention, the titanium layer is selected in consideration of adhesion, electrical conductivity, ease of production, and cost, but the present invention is not limited to this. The thickness of the lower adhesion layer 110 is not defined in the present invention, but is desirably 10 nm or more and 1 μm or less. If it is less than 10 nm, the adhesion strength may be insufficient. When the thickness exceeds 1 μm, not only does the film formation time take too much to lack mass productivity, but it also takes more time in the process of removing unnecessary portions. More preferably, it is 10 nm or more and 500 nm or less. Further, when the adhesion between the dielectric layer 111 and the conductor circuit layer 105 is sufficient, the lower adhesion layer 110 may not be provided.

  The dielectric layer 111 shown in FIG. 2B is selected from alumina, silica, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, and strontium titanate from the viewpoint of insulation and relative dielectric constant. I can do it. The thickness of the dielectric layer 111 is desirably 10 nm or more and 5 μm or less. When the thickness is less than 10 nm, the insulating function cannot be maintained and the function as a capacitor is not exhibited. When it exceeds 5 μm, not only the film formation time is too long and the mass productivity is lacking, but also the process of removing unnecessary portions takes longer time. More preferably, it is 50 nm or more and 1 μm or less.

  Subsequently, a resist pattern 103-1 is formed as shown in FIG. The formation of the resist pattern 103-1 may be performed by the same method as described above. In this case, the resist pattern 103-1 is formed inside the conductor circuit layer 105. Although FIG. 2C is described with reference to a schematic cross-sectional view of an example, it is formed so as to be inside even in a plan view.

  Subsequently, in FIG. 2D, unnecessary portions of the dielectric layer 111 and the lower adhesion layer 110 are removed using the resist pattern 103-1 as a mask. As a method for removing the dielectric layer 111 and the lower adhesion layer 110, both a chemical etching method and a dry etching method can be used, and the method is not limited in the present invention. As described above, since the resist pattern 103-1 is formed inside the conductor circuit layer 105, when unnecessary portions are removed using the resist pattern 103-1 as a mask, the dielectric layer 111 is located inside the conductor circuit layer 105. Only formed.

  Further, in the above, the dielectric layer 111 has a size of a surface in contact with the lower adhesion layer 110 of the dielectric layer 111 in a plan view from the surface of the glass substrate 100 to the far side (the side away from the glass substrate 100). On the other hand, the size of the surface of the dielectric layer 111 in contact with the resist pattern 103-1 is small, and the end portion in the side view of the dielectric layer 111 has a forward tapered shape so that unnecessary portions are removed. To do. In order to form the forward tapered shape constituting the dielectric layer 111, a dry etching method represented by reactive ion beam etching, reactive gas etching, reactive ion etching, or the like can be used. A dry etching method in which it is easy to selectively form an end shape by anisotropic etching can be preferably used rather than a wet etching method in which isotropic etching is dominant. In this case, it is possible to control the etching rate at the interface and control the shape of the end of the dielectric layer 111 by the combination of the resist type of the resist pattern 103-1 and the dielectric layer 111.

  Subsequently, the resist pattern 103-1 that is no longer necessary in FIG. 2E is removed. The removal of the resist pattern 103-1 can be performed by a stripping process using an aqueous alkali solution known in the art.

  Subsequently, as shown in FIG. 2F, the upper adhesion layer 112 and the seed metal layer 113 are sequentially deposited over the entire surface. Examples of the method for forming the layer include a vacuum deposition method, a sputtering method, an ion plating method, an MBE method, a laser ablation method, and a CVD method, but are not limited in the present invention.

  The upper adhesion layer 112 on the dielectric layer 111 is a layer that improves adhesion between the dielectric layer 111, the seed metal layer 113, and the upper electrode layer 114 (see FIG. 2H). For example, Cu, Ni, Al, titanium, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, Cu alloy, or a combination of them can be applied. . In the present invention, the titanium layer is selected in consideration of adhesion, electrical conductivity, ease of production, and cost, but the present invention is not limited to this. The thickness of the upper adhesion layer 112 is not defined in the present invention, but is desirably 10 nm or more and 1 μm or less. If it is less than 10 nm, the adhesion strength may be insufficient. When the thickness exceeds 1 μm, not only does the film formation time take too much to lack mass productivity, but it also takes more time in the process of removing unnecessary portions. More preferably, it is 10 nm or more and 500 nm or less. Further, in the case where the dielectric layer 111, the seed metal layer 113, and the upper electrode layer 114 (see FIG. 2H) are sufficiently adhered, the upper adhesion layer 112 may not be provided. For the upper adhesive layer 112, it is desirable to select the same material as that of the lower adhesive layer 110 because the process can be simplified (as will be described later).

  The seed metal layer 113 is a power supply layer for forming the upper electrode layer 114 of the MIM capacitor by a semi-additive method. For the seed metal layer 113, for example, Cu, Ni, Al, Titanium, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, a Cu alloy alone or a combination thereof is applied. can do. More preferably, copper is desirable because the subsequent etching removal is simple. The thickness of the seed metal layer 113 is desirably 10 nm or more and 5 μm or less. When the thickness is 10 nm or less, there is a possibility that an energization failure may occur in the subsequent electrolytic plating process. When the thickness is 5 μm or more, it takes time to remove the etching. More preferably, it is 100 nm or more and 500 nm or less.

  Subsequently, a resist pattern 103-2 is formed as shown in FIG. The formation of the resist pattern 103-2 may be performed by the same method as described above. In this case, the opening region of the resist pattern 103-2 is formed so as to be inside the dielectric layer 111. Although FIG. 2G is described with reference to a schematic cross-sectional view of an example, it is formed so as to be inside even in a plan view.

  Subsequently, the upper electrode layer 114 is formed by electrolytic plating using the seed metal layer 113 in FIG. Examples of electrolytic plating methods include electrolytic nickel plating, electrolytic copper plating, electrolytic chromium plating, electrolytic Pd plating, electrolytic gold plating, electrolytic rhodium plating, and electrolytic iridium plating. Electrolytic copper plating is simple and inexpensive. It is desirable because of its good electrical conductivity. The thickness of the electrolytic copper plating is desirably 3 μm or more and 30 μm or less. If the thickness is less than 3 μm, there is a risk that the circuit may be lost depending on the subsequent etching process. Furthermore, there is a risk that the connection reliability and electrical conductivity of the circuit will be reduced. When the electrolytic copper plating thickness exceeds 30 μm, it is necessary to form a thick resist layer exceeding 30 μm, which increases manufacturing costs. Furthermore, since the resist resolution is lowered, it becomes difficult to form fine wiring with a pitch of 30 μm or less. More preferably, it is 5 μm or more and 25 μm or less. More desirably, it is 10 μm or more and 20 μm or less. As described above, since the resist pattern 103-2 has an opening formed inside the dielectric layer 111, the upper electrode layer 114 is formed only inside the dielectric layer 111.

  Subsequently, the resist pattern 103-2 that is no longer necessary in FIG. 2I is removed. The resist pattern 103-2 can be removed by a stripping process using a known alkaline aqueous solution.

  Subsequently, an unnecessary portion of the seed metal layer 113 is removed in FIG. A known chemical etchant can be used to remove the seed metal layer 113. Further, it may be removed by a dry etching method.

  Subsequently, in FIG. 2K, unnecessary portions of the upper adhesion layer 112 and the lower adhesion layer 110 are removed. As the removal method, a chemical etching method and a dry etching method, both known methods can be used, but the method is not limited in the present invention. In this case, if the upper adhesive layer 112 and the lower adhesive layer 110 are made of the same material, the upper adhesive layer 112 and the lower adhesive layer 110 can be collectively processed in a single removal process as described above, which simplifies the process. it can. Through the above steps, the MIM capacitor is formed.

  Next, application examples of the capacitor built-in wiring board and the electronic component according to the present invention will be described with reference to FIG. As shown in FIG. 3, after the MIM capacitor 132 is formed on the conductor circuit immediately above the glass substrate, the insulating resin layer 131, the via hole 130, and the conductor circuit layer 105 are formed using a known semi-additive method or subtractive method. A multilayer wiring may be formed by repeating the formation. Further, the solder balls 133 may be formed after the external connection terminals 134 are formed.

  Further, as described in FIG. 4, an on-circuit MIM capacitor 132 on the insulating resin layer 131 may be formed. The MIM capacitor 132 may be formed in any layer of the multilayer wiring, and is not limited in the present invention.

  The circuit board according to the present invention may have external connection terminals (solder balls 133) on one side as shown in FIGS. 3 and 4, or may be on both sides as shown in FIG. Further, a semiconductor chip 135 and a chip component 136 may be mounted.

  A method for forming a multilayer wiring will be described below. A known method can be used as a method of forming the multilayer wiring.

  Examples that can be used as the insulating resin 131 of the multilayer wiring layer include epoxy resin, polyimide, maleimide resin, polyethylene terephthalate, polyphenylene oxide, liquid crystal polymer and their composite materials, or photosensitive polyimide resin, photosensitive polybenzoxazole, photosensitive An acrylic-epoxy resin may be used. The method for forming the insulating resin is not limited in the present invention, but a vacuum laminating, vacuum pressing, or roll laminating method can be used as long as it is a sheet. As long as it is liquid, it can be selected from slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, and doctor coating. The thickness of the insulating resin layer 131 is desirably 5 μm or more and 50 μm or less. When the thickness exceeds 50 μm, it is difficult to reduce the diameter of the via hole 130 that can be formed in the insulating resin layer 131, so that it is disadvantageous to increase the density of the wiring. On the other hand, when it is less than 5 μm, it is difficult to ensure interlayer insulation.

The via hole 130 in the multilayer wiring can be formed by laser processing if it is a non-photosensitive insulating resin. Examples of the laser include a CO ₂ laser, a UV laser, a picosecond laser, and a femtosecond laser, but a UV laser and a CO ₂ laser are preferable because they are simple and desirable. A photosensitive insulating resin can be formed by a photolithography method. Desirably, the surface of the resin is roughened and the inside of the via hole is cleaned to improve the adhesion to the conductor circuit layer 105 by appropriately performing desmearing with a permanganate solution after forming the via hole. Alternatively, a method of cleaning the resin surface and the inside of the via by plasma treatment may be performed.

  A known method can be used for forming the conductor circuit layer 105. That is, a thin film metal layer is formed as a seed metal layer having a thickness of about 1 μm on the entire surface of the resin after the via hole is formed. As a method for forming the seed layer, a thin film metal layer can be formed by known electroless copper plating, electroless nickel plating, or sputtering. The seed metal layer is preferably an electroless copper plating layer if it is electroless plating. In the case of electroless plating, it is preferable that electrolytic copper plating be simple and inexpensive. In the case of electroless plating, the Pd layer of the catalyst may be at the resin-copper interface. If it is a sputtering method, Cu, Ni, Al, titanium, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, Cu alloy, or a combination of a plurality of alloys is applied. be able to. More preferably, a sputter layer of titanium layer / copper layer is preferable because of good adhesion and easy removal by etching later. If the wiring formation method after forming the metal layer on the resin is a known semi-additive method, a circuit can be formed by resist pattern formation by photolithography, electrolytic plating, resist peeling, and seed layer removal. In the case of the subtractive method, the circuit layer can be formed on the entire surface of the seed layer by electrolytic plating, resist pattern formation, etching, and resist stripping. The electrolytic plating is preferably electrolytic copper plating from the viewpoint of electrical conductivity and cost.

  As long as the insulating resin layer 131 in FIGS. 3 and 4 is the outermost layer, a solder resist may be used, and the present invention is not limited thereto. Further, the external connection terminal 134 may be subjected to a surface treatment. By performing the surface treatment, the bondability with the solder ball 133 is improved. For the surface treatment, tin or a tin alloy plating film, an electroless Ni—P / electroless Pd—P / Au plating film, or an electroless Ni—P / Au plating film can be formed. Alternatively, pre-solder treatment or organic coating treatment such as OSP (Organic Solderability Preserva titanium ve) may be performed. The solder balls 133 can be formed by a screen printing method, a solder ball transfer mounting method, an electrolytic plating method, or the like. As the composition of the solder ball 133, one kind of tin, silver, copper, bismuth, lead, zinc, indium, antimony, or a mixture of plural kinds thereof can be used, and the mixing ratio of these metal materials is not limited. You may provide the pad for wire bonding instead of solder.

<Effect>
Next, the configuration and effects of using the capacitor-embedded glass circuit boards 200 and 201 as described above and the manufacturing method thereof will be described with reference to FIG.

As shown in FIG. 2D of the present embodiment, by making at least a part of the dielectric layer 111 a forward tapered shape, the seed metal layer 113 is not cut off as shown in FIGS. Since the film can be formed on the conductor circuit layer 105 region without being raised, the power supply for forming the upper electrode layer 114 of the MIM capacitor by the semi-additive method can be stably performed. In FIG. 2, both end portions of the dielectric layer 111 have a forward taper shape. However, if only one side has a forward taper shape, the above-described effect can be obtained, and at least a part of the end portion of the dielectric layer 111 in a plan view. If is a forward tapered shape, an effect can be obtained. However, in view of avoiding complication of the forming process and corresponding to various capacitor shapes in a plan view such as a quadrangle, other polygons, or a circle, the outer peripheral portion of the dielectric layer 111 in the plan view is all forward tapered. It is preferable that

  Further, as shown in FIG. 2E, the dielectric layer 111 is formed inside the conductor circuit layer 105, and the upper electrode layer 114 (see FIG. 2H) of the MIM capacitor is further formed by a semi-additive method. Therefore, it is possible to stably supply power for the purpose. In this case, the conductor circuit layer 105 and the seed metal layer 113 (see FIG. 2 (h)) are arranged not only on the side surfaces but also on the upper surface portion with no insulating material interposed therebetween. In addition, the conductor circuit layer 105 can also be used.

  Further, as shown in FIG. 2I, the upper electrode layer 114 is formed on the inner side with respect to the upper surface of the dielectric layer 111, whereby the capacitance of the MIM capacitor can be stabilized. In the present invention, the end portion of the dielectric layer 111 has a forward taper shape, so that the thickness is relatively thin. When an electric field is applied to the region, the characteristics are deteriorated due to concentration of the electric field or leakage current. It becomes stable. Therefore, the influence of the upper electrode layer 114 can be reduced by forming the upper electrode layer 114 on the inner side with respect to the upper surface of the dielectric layer 111.

  Further, as shown in FIG. 2 (k), when the lower adhesive layer 110 and the upper adhesive layer 112 are made of the same material, the lower adhesive layer 110 and the upper adhesive layer 112 can be collectively processed in one removal process. Therefore, the process can be simplified. Furthermore, the lower adhesion layer 110 and the upper adhesion layer 112 do not use a resist pattern or the like, and unnecessary portions can be removed using the upper layer as a mask. Therefore, the upper adhesion layer and the upper electrode layer are substantially the same in plan view. The lower adhesion layer and the lower surface of the dielectric layer can be formed in substantially the same size in plan view.

<Example 1>
Based on the multilayer wiring board having the glass substrate according to the present invention, a method for manufacturing the multilayer wiring board will be described with reference to FIGS.

First, as shown in FIG. 1A, a glass substrate 100 (OA-10G manufactured by Nippon Electric Glass Co., Ltd., 0.5 mm thickness, linear thermal expansion coefficient 3 ppm / K) is prepared.
Subsequently, as shown in FIG. 1B, the through hole 101 was formed with a top diameter of 80 μm and a bottom diameter of 60 μm using a picosecond laser processing machine.
Further, as shown in FIG. 1C, a titanium film having a thickness of 50 nm and a copper film having a thickness of 300 nm were formed on the front and back surfaces of the glass substrate 100 as a seed metal layer 102 by a sputtering method. Further, an electroless nickel plating layer having a thickness of 0.1 μm was formed for the purpose of increasing the seed metal layer in the through hole 101. As described above, the seed metal layer 102 made of titanium, copper, and nickel was formed.
Subsequently, as shown in FIG. 1D, a photosensitive dry film resist having a thickness of 25 μm was provided on the glass surface seed metal layer 102 by roll lamination, and a resist pattern 103 was formed by photolithography.
Next, after forming the electrolytic copper plating layer 104 so as to have a thickness of 15 μm as shown in FIG. 1E, the resist pattern 103 is peeled off in an alkaline solution, whereby the substrate shown in FIG. Obtained. Further, the Ni layer of the seed metal layer 102 is dissolved and removed sequentially using a nitric acid-hydrogen peroxide mixed etching solution, the Cu layer using a sulfuric acid-hydrogen peroxide mixed etching solution, and the titanium layer using a potassium hydroxide-hydrogen peroxide etching solution. Glass core substrate Fig. 1 (g) was obtained.

Next, the formation of the MIM capacitor in the present invention will be described with reference to FIG.
As shown in FIG. 2B, a titanium / alumina layer of 50 nm / 300 nm is formed on the entire surface of the conductor circuit layer 105 formed on the glass substrate 100 shown in FIG. Then, a dielectric layer 111 was formed thereon by a sputtering method. Subsequently, a dry film resist was formed on the entire upper surface of the dielectric layer 111 by vacuum lamination to form a resist layer (not shown).
Subsequently, as described in FIGS. 2C to 2E, after the resist pattern 103-1 is formed by a known photolithography method, the end portion of the dielectric layer 111 becomes a forward tapered shape by a dry etching method. Then, the resist pattern 103-1 was peeled off with an alkaline aqueous solution.
Subsequently, as shown in FIG. 2F, a titanium / Cu layer was formed on the entire upper surface so as to be 50 nm / 200 nm. Subsequently, a dry film resist was formed on the entire upper surface by vacuum lamination to form a resist layer (not shown).
Subsequently, after forming a resist pattern 103-2 by a known photolithography method as shown in FIG. 2G, the upper electrode layer 114 of the MIM capacitor is formed by electrolytic copper plating as shown in FIG. It was formed with a thickness of 10 μm. Further, as shown in FIG. 2 (i), after the resist pattern 103-2 is peeled and removed with an alkaline aqueous solution, the seed metal layer 113 for forming the MIM capacitor is subjected to sulfuric acid-peroxidation as shown in FIG. 2 (j). It was dissolved and removed with a hydrogen etching solution. Finally, as shown in FIG. 2 (k), the upper adhesion layer 112 and the lower adhesion layer 110 are etched using the potassium hydroxide-hydrogen peroxide etchant to etch the upper adhesion layer 112 and the titanium layer as the lower adhesion layer 110. By removing, the MIM capacitor which is this invention was formed.

  Furthermore, an insulating resin layer was formed on both front and back surfaces by vacuum lamination of GX-T31 (manufactured by Ajinomoto Fine Techno), a built-up resin having a fat thickness of 40 μm, and then a via hole having a diameter of 60 μm was formed with a UV laser processing machine. Further, after forming an electroless copper plating layer having a thickness of 0.8 μm by desmearing treatment and electroless copper plating treatment, a dry film resist layer having a thickness of 25 μm was formed on both the front and back surfaces. After forming a resist pattern by photolithography, a multilayer circuit layer in which a conductor circuit layer having a thickness of 15 μm was formed on the front and back surfaces by electrolytic copper plating was formed.

  By repeating the above multilayer circuit formation, the built-up multilayer circuit was formed with two conductor circuit layers on the front and back surfaces of the glass substrate. A solder resist layer 131 was formed on the outermost layers on the front and back surfaces, and the external connection terminals 134 were exposed by a photolithography process. Further, as shown in FIG. 3, a nickel-gold plating layer (not shown) is formed on the surface of the external connection terminal 134, and further a solder ball 133 is formed, so that a glass circuit board 200 with a built-in capacitor is produced. .

<Comparative Example 1>
As Comparative Example 1, an attempt was made to produce a glass core circuit board with a built-in capacitor in which the end of the dielectric layer 111 shown in FIG. 2 (e) has a vertical shape from the surface of the glass substrate 100 toward the far surface from the glass substrate 100. It was. The manufacturing method is the same as the method described in the above-described embodiment except for the method of removing unnecessary portions of the dielectric layer 111 described in FIG. In this case, when dry etching is performed to remove unnecessary portions of the dielectric layer 111, the type of introduced gas is changed in the middle, and an altered layer (a layer that prevents dry etching) is formed on the exposed surface of the dielectric layer 111. By doing so, removal by dry etching from the lateral direction was prevented, and a vertical shape was obtained.

<Comparative Example 2>
As Comparative Example 2, an attempt was made to produce a glass core circuit board with a built-in capacitor in which the end of the dielectric layer 111 shown in FIG. 2D has a reverse taper shape from the surface of the glass substrate 100 toward the far surface. The manufacturing method is the same as the method described in the above-described embodiment except for the method of removing unnecessary portions of the dielectric layer 111 described in FIG. In this case, in removing unnecessary portions of the dielectric layer 111, by selecting the resist pattern 103-1 having excellent adhesion to the dielectric layer 111 or the lower adhesion layer 110 having poor adhesion to the dielectric layer 111, In addition, a reverse taper shape was obtained by controlling the removal so as to proceed from the interface between the dielectric layer 111 and the lower adhesion layer 110.

  In the manufacturing methods of Examples and Comparative Examples 1 and 2 described above, a significant difference was confirmed in the formation quality of the upper electrode layer 114 in FIGS. 2 (h) and 2 (i), and the results are described below.

Example 1 The upper electrode layer 114 was formed to be 100%, and the thickness was also good at 10 μm ± 1 μm with respect to 10 μm.
Comparative Example 1 The upper electrode layer 114 was found to have an unformed portion of about 2 to 5%, and the target thickness was 7 μm ± 5 μm with respect to 10 μm.
Comparative Example 2 ... The upper electrode layer 114 was formed at 10 to 15%.

  In the seed metal layer 113, when the resistance value was measured using a tester between the upper surface of the dielectric layer 111 and other portions, Example 1 was the lowest, Comparative Example 1 was higher than Example 1, and Comparative Example In 2, it showed a higher value.

  The above-described embodiment is an example, and it is needless to say that other specific detailed structures can be appropriately changed.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to manufacture the glass circuit board with a built-in capacitor which has a glass base material with high reliability. The glass circuit board with a built-in capacitor according to the present invention can be used for manufacturing a semiconductor package substrate, an interposer, an optical element substrate, or an electronic component.

100 ... Glass substrate 101 ... Through hole (through hole)
DESCRIPTION OF SYMBOLS 102 ... Seed metal layer 103 ... Resist pattern 104 ... Electroplating layer 105 ... Conductor circuit layer 110 ... Lower adhesion layer 111 ... Dielectric layer 112 ... Upper adhesion layer 113 ... Seed metal layer (MIM capacitor part)
114 ... Upper electrode layer 130 ... Via hole 131 ... Insulating resin layer (solder resist layer)
132 ... MIM capacitor 133 ... solder ball 134 ... external connection terminal 135 ... semiconductor chip 136 ... chip components 200, 201, 202 ... glass circuit board with built-in capacitor A ... MIM capacitor forming portion

Claims (9)

In a glass circuit board provided with a build-up layer in which conductor circuit layers and insulating resin layers are alternately laminated on at least one surface of a glass base material capable of conducting through the through-holes,
An MIM capacitor is provided between the lower and upper conductor circuit layers adjacent via the insulating resin layer,
The MIM capacitor includes a part of the lower conductor circuit layer, a dielectric layer, and an upper electrode layer.
The upper electrode layer is connected to the conductor circuit layer provided on the upper side of the insulating resin layer,
A glass circuit board, wherein a part of a cross-sectional end portion of the dielectric layer has a forward tapered shape. In a glass circuit board provided with a build-up layer in which conductor circuit layers and insulating resin layers are alternately laminated on at least one surface of a glass base material capable of conducting through the through-holes,
An MIM capacitor is provided between the lower and upper conductor circuit layers adjacent via the insulating resin layer,
The MIM capacitor includes a part of the conductor circuit layer below the insulating resin layer, a dielectric layer, and an upper electrode layer.
The upper electrode layer is connected to the conductor circuit layer on the upper side of the insulating resin layer,
A glass circuit board characterized in that all of the end portions of the cross section of the dielectric layer have a forward tapered shape.   The glass circuit board according to claim 1, wherein the upper electrode layer is provided inside the dielectric layer in a plan view.   The glass circuit board according to claim 1, wherein the dielectric layer is provided inside the lower conductor circuit layer in a plan view. In the MIM capacitor having a lower adhesion layer between the lower conductor circuit layer and the dielectric layer, and having an upper adhesion layer between the upper conductor circuit layer and the dielectric layer,
The lower adhesion layer and the upper adhesion layer are made of the same material,
2. The upper electrode layer and the upper adhesion layer have the same shape in plan view, and the lower adhesion layer and the lower surface of the dielectric layer in contact with the layer have the same shape in plan view. The glass circuit board in any one of -4. A method of manufacturing a glass circuit board with a built-in MIM capacitor,
Forming a through hole in the glass substrate;
A step of repeating a step of forming a conductor circuit layer, a step of forming an insulating resin layer, and a step of forming a via in the insulating resin layer as many times as necessary in this order,
Forming a MIM capacitor in a part of the conductor circuit layer in step A, and
The process of forming the MIM capacitor is as follows:
Forming a lower adhesion layer and a dielectric layer in this order at a portion of the conductor circuit layer forming the MIM capacitor;
Forming a resist pattern A on the dielectric layer;
Removing the dielectric layer using the resist pattern A as an etching mask;
Removing the resist pattern A;
Forming an upper adhesion layer and a seed metal layer in this order;
Forming a resist pattern B on the seed metal layer;
Forming a top electrode layer by electrolytic plating using the seed metal layer as an electrode;
Removing the resist pattern B;
Removing the seed metal layer using the upper electrode layer as an etching mask;
Removing the upper adhesion layer using the seed metal layer as an etching mask, and further removing the lower adhesion layer using the dielectric layer as an etching mask.
The step of removing the dielectric layer uses a dielectric layer removing means in which the shape of the end of the dielectric layer is a forward tapered shape.   The method for manufacturing a glass circuit board according to claim 6, wherein the same material is used for the upper adhesion layer and the lower adhesion layer.   8. The method of manufacturing a glass circuit board according to claim 6, wherein the resist pattern A is formed so that the upper electrode layer is formed inside the dielectric layer in a plan view.   The glass according to claim 6, wherein the resist pattern B is formed so that the dielectric layer is formed inside a conductor circuit layer that forms the MIM capacitor in a plan view. A method of manufacturing a circuit board.

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