JP2001185687A - Integrated circuit device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit device containing a stack type of capacitor, in which a dielectric layer having superior crystallinity is formed, an interlayer insulating film is made thinner and an influence of dry etching is suppressed by making depth of through holes uniform, and a method for manufacturing it. SOLUTION: A semiconductor substrate is provided with a dug part (2 in Fig.1) having a specified depth with a flat bottom part, and a lower electrode (4 in Fig.1) protruding from the bottom part of the dug part to the outside of an upper part is formed over there with an insulating film in between, and a dielectric layer having high dielectric constant (5 in Fig.1) whose thickness is almost equal to the depth of the dug part and an upper electrode (6 in Fig.1) are placed in the flat region of the bottom part of the dug part, to form a capacitor element (10 in Fig.1), thereby a difference in level of the capacitor element is made smaller. A through hole that penetrates to at least the lower electrode protruding to the upper part of the dug part and the upper electrode is provided in an interlayer insulating film covering the capacitor element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device including a capacitor (or a capacitor or a capacitance) using a thin film having a high dielectric constant and a method of manufacturing the same.

[0002]

2. Description of the Related Art With the rapid spread of mobile phones, competition for the development of smaller and lighter mobile phones has become active. In particular, digital signal processing LSIs and analog I
The development of C has led to this realization. However, since microwave ICs (MMICs) are initially expensive in compound semiconductor substrates, passive elements such as capacitors and inductors that require a large area have been provided outside the MMIC. Since then, with the spread of mobile phones, there has been a demand for further miniaturization and weight reduction, and there has been an increasing demand for an MMIC that is integrally miniaturized including these passive elements such as capacitors and inductors.

Conventionally, a capacitor of a microwave IC has a silicon nitride film (SiN) or a silicon oxide film (SiO ₂ ).
However, since the relative dielectric constant was as low as 4 to 7, a large area was required. Therefore, in order to reduce the area of the capacitor, a method of providing a high dielectric constant material having a relative dielectric constant as large as several hundreds, which has been used for an external capacitor, in the MMIC has attracted attention. Examples of the high dielectric constant material include SrTiO ₃ , BaTiO ₃ , Ba _0.5 Sr _0.5 TiO
_Third magnitude.

As a structure and a manufacturing method for forming a capacitor having a high dielectric constant thin film in an MMIC, for example, Japanese Patent Application Laid-Open No.
No. 0-3355582 (conventional example 1). FIG. 6 is a process cross-sectional view schematically showing a method for manufacturing a semiconductor device in Conventional Example 1.

[0005] First, as shown in FIG.
SiO ₂ having a thickness of about 100 nm on a semiconductor substrate 21 such as
Is formed by a low-pressure CVD method. On top of that, Pt (70 nm) / Ti (20 nm) / Pt
Lower electrode 2 made of (70 nm) / Ti (20 nm)
3, the dielectric layer 2 made of SrTiO ₃ having a thickness of 200nm
4. An upper electrode 25 made of Pt having a film thickness of 70 nm is sequentially formed by sputtering, and is processed in order from the top by ion milling to produce a capacitor having an MIM structure. Note that the deposition temperature of the dielectric layer 24 is 450 ° C.

Next, as shown in FIG. 6B, a protective film 26 made of SiO ₂ having a thickness of 100 nm is formed on the capacitor.
Is formed by a normal pressure CVD method. Thereafter, using the photoresist as a mask, the protective film 26 and the insulating film 22 are removed by wet etching except for a portion 5 μm outside from the outer periphery of the lower electrode 23 (see FIG. 6C).

After that, the surface of the semiconductor is subjected to a surface treatment using a hydrochloric acid: water = 1: 1 solution, and as shown in FIG.
A process insulating film 27 for fabricating an FET is formed by a low-pressure CVD method. Thereafter, gate formation and ohmic formation are performed using the process insulating film 27 to form an FET (see FIG. 6E).

Next, the high dielectric constant thin film is used not only for the capacitor of the MMIC but also for the charge holding capacitor of the nonvolatile memory LSI.
No. 293 (Conventional Example 2). FIG.
FIG. 11 is a cross-sectional view of a capacitor of a nonvolatile memory to which a high-dielectric-constant thin film is applied in Conventional Example 2.

As shown in FIG. 7, a MOS type FET is provided on the surface of a semiconductor substrate 31 made of silicon or the like, and a contact plug 39 made of polysilicon or the like is connected to the conductive impurity diffusion region 33 serving as an ohmic contact. . The periphery of the contact plug 39 is filled with a flattening insulating film 44. The flattening insulating film 44 is provided thickly.
A digging (trench) is provided so as to expose an upper portion of the contact plug 39. In this trench, a barrier metal 40 such as TiN, a lower electrode 41 such as Ir, Ba _0.5
A dielectric layer 42 having a high dielectric constant such as Sr _0.5 TiO _{3 and} an upper electrode 43 such as Pt are provided. In such a capacitor, the cell occupation area can be reduced by using the side surface of the trench.

Next, there is known a trench capacitor in which a capacitor of a DRAM memory LSI is formed by forming a deep trench in a semiconductor substrate.
No. 23857 (conventional example 3). FIG.
FIG. 11 is a cross-sectional view schematically showing a structure of a trench capacitor of a DRAM memory LSI according to Conventional Example 3.

As shown in FIG. 8, a semiconductor substrate 51 made of silicon or the like is vertically deeply dug (trench) 63a,
63b is provided, and an n-type impurity is diffused into the inner surface of the trench to form a plate electrode 60, on which SiO _{2 is formed.}
Is formed thinly, and further, a storage electrode 62 made of polysilicon is embedded in the trench.

[0012]

Here, the MMIC for a portable telephone needs to provide a large-sized capacitor between the power supply lines for high-frequency bypass and power supply smoothing.
In addition, the breakdown voltage of the capacitor is required to be about 100 V, which is the same as that of an external case, against electrostatic surge generated by sweater friction in winter. The breakdown voltage substantially depends on the thickness of the high dielectric constant film, and as shown in the conventional example 1 of FIG.
With m, the withstand voltage is insufficient, and 400 to 600 nm is required. On the other hand, since the relative dielectric constant is 100 to 200, which is higher than that of SiN, the capacitance can be secured and the area can be reduced.

However, the conventional capacitor element is
Including the thickness of the electrode, the thickness becomes close to 1 μm, which is considerably higher than the FET electrode on the substrate surface, and the following problems occur. That is, when wiring is formed with a capacitor interposed, it is necessary to provide a thick interlayer insulating film and planarize it. However, the depth of a through hole from the planarized interlayer insulating film is smaller than that of the capacitor upper electrode and the FET electrode. Is very different.

In this case, if both through holes are simultaneously opened by parallel plate dry etching (RIE), the capacitor upper electrode 6 having a shallow through hole is exposed to etching for a long time, and the metal such as Pt used as an electrode is R
It is sputtered by IE, and the speed is low, but the electrode needs to be thickened because it is etched. In addition, gas plasma penetrates from the grain boundary of the electrode, spatter damage, etc.,
Problems such as a decrease in the dielectric constant and an increase in the leak current also occurred.
On the other hand, it is possible to form the through holes separately according to the depth, but in this case, there is a problem that the number of manufacturing steps is increased and the manufacturing period is lengthened.

Further, in the conventional example 2 shown in FIG. 7, a method of using a side surface by digging is proposed in order to reduce the capacitor area, but this method is the same as the conventional example 3 shown in FIG. It is merely an extension of a trench capacitor in which a substrate is dug in principle.

Here, in order for the high dielectric constant thin film 5 to exhibit a high dielectric constant, it is necessary that the thin film constitutes a perovskite type crystal, and the columnar crystal is made as close as possible to a single crystal by adjusting the element composition. Is important. This is because a shift in the element composition causes segregation of component elements at crystal grain boundaries.

Conversely, this means that a crystalline high-dielectric-constant film can be formed only on one plane, and if the dielectric layer includes corners and side surfaces, the columnar crystal orientation (orientation plane) is applied. In this case, the crystallinity is broken and the component elements are segregated, and a leak current is generated. For this reason, in a recent memory LSI using a high dielectric constant capacitor, a second conventional example shown in FIG.
Such a trench type is not used, and a stack type provided on a plane surface of an insulating film is generally used.

The present invention has been made in view of the above problems, and its main purpose is to form a dielectric layer having good crystallinity, reduce the thickness of an interlayer insulating film, and reduce the depth of a through hole. An object of the present invention is to provide an integrated circuit device including a stacked capacitor and a method of manufacturing the integrated circuit device, which can uniformly suppress the influence of dry etching.

[0019]

In order to achieve the above object, according to the present invention, in a first aspect, a substrate or an insulating film provided on the substrate is provided with a recess having a flat bottom and a predetermined depth. A lower electrode formed so as to protrude upward from the bottom of the depression, and a dielectric layer and an upper electrode separated from corners and sidewalls of the depression on the lower electrode in a flat region of the bottom of the depression. Are formed.

According to a second aspect of the present invention, in the second aspect, the substrate or the insulating film provided on the substrate has a recess having a flat bottom and a predetermined depth, and is formed to protrude upward from the bottom of the recess. A lower electrode is formed, a dielectric layer and an upper electrode are formed on the lower electrode in a flat region at the bottom of the recess, away from corners and side walls of the recess, and a capacitive element is formed. At least a through-hole penetrating to each of the lower electrode and the upper electrode protruding above the depression is formed in the covering insulating film.

According to a third aspect of the present invention, there is provided a method of manufacturing an integrated circuit device. The method comprises the steps of (a) forming a recess having a flat bottom at a predetermined depth in a substrate or an insulating film provided on the substrate, and (b) forming a lower electrode on the substrate or the insulating film. Depositing a dielectric layer and an upper electrode in this order; and (c) depositing the upper electrode and the dielectric layer such that the upper electrode and the dielectric layer remain on a flat region at the bottom of the recess. And (d) etching the lower electrode such that the lower electrode remains from the bottom of the dent to a predetermined region outside the dent.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION In a preferred embodiment of the integrated circuit device according to the present invention, a substrate is provided with a digging (or dent) (2 in FIG. 1) having a flat bottom and a predetermined depth. A lower electrode (4 in FIG. 1) projecting from the bottom of the digging to the upper outside is formed via an insulating film, and a dielectric layer having a high dielectric constant substantially equal to the digging depth is formed in a flat region of the digging bottom. (5 in FIG. 1) and the upper electrode (6 in FIG. 1) are arranged to form a capacitor element (10 in FIG. 1), thereby reducing the step of the capacitor element and an interlayer insulating film covering the capacitor. In addition, a through-hole is provided at least to each of the lower electrode and the upper electrode which protrude outside the digging.

[0023]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

Embodiment 1 First, an integrated circuit device according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view illustrating the structure of an integrated circuit device according to a first embodiment of the present invention. FIG.
4A to 4H are process sectional views schematically showing the manufacturing method, and are separated for convenience of drawing.

Referring to FIG. 1, the structure of the integrated circuit device of this embodiment will be described.
The surface of the semiconductor substrate 1 made of As or the like has a recess 2 having a depth of about 500 nm, and the surface including the recess ₂ is covered with an insulating film 3 made of SiO ₂ having a thickness of 200 nm.
On this insulating film 3, Pt (70 nm) / Ti
A lower electrode 4 made of (20 nm) / Pt (70 nm) / Ti (20 nm) is provided so as to protrude into the dug 2 and the substrate surface on the upper periphery. High dielectric constant dielectric layer 5 made of SrTiO ₃ having a thickness of about 500 nm and Ti (20 nm) /
An upper electrode 6 of Pt (70 nm) is provided.

These capacitors are made of 1 μm thick Si
It is covered with a flattened interlayer insulating film 7 made of O ₂ . A through-hole (opening) 8 is formed in the interlayer insulating film 7 on the lower electrode 4 and the upper electrode 6 drawn out of the digging 2 to the substrate surface.
Is provided, and Au plating (2 μm) / Ti (100 n
m) etc. are provided. Further, a semiconductor element 11 such as a MESFET is provided on the surface of the semiconductor substrate 1 near the capacitor, and a through hole 8 and a wiring 9 are also provided in an FET electrode 13 of the semiconductor element 11.

A method of manufacturing such an integrated circuit device will be described with reference to FIGS. 2 (a) to 4 (h). First, as shown in FIG. 2A, an n-type GaAs FET active layer region 12 is formed on a surface of a semiconductor substrate 1 made of semi-insulating GaAs or the like by selective ion implantation using a photoresist film mask. I do. Further, a semiconductor layer epitaxially grown by MOCVD or the like may be insulated by generating defects by ion implantation and may be subjected to element isolation.

Thereafter, using the photoresist film pattern 15 as a mask, for example, the GaAs semiconductor substrate 1 is etched by about 0.5 μm with a solution obtained by mixing phosphoric acid, hydrogen peroxide solution and water, and a recess 2 is provided. In this wet etching, the etching of the GaAs surface is performed smoothly. After that, the photoresist film 15 is removed with an organic solvent.

Next, as shown in FIG. 2B, an insulating film 3 of SiO ₂ or the like is formed to a thickness of 200 nm by using a low pressure vapor deposition method.
About the entire surface of the substrate, and then, by sputtering,
Ti 20 nm, Pt 70 nm, Ti 20 nm, Pt 70
nm is sequentially deposited to form the lower electrode 4. At this time,
By increasing the substrate temperature to about 300 ° C., the columnarization of Pt is promoted. Subsequently, using a sintered target such as SrTiO ₃ , sputtering is performed at a substrate temperature of 450 ° C. in an atmosphere of Ar and oxygen to form a dielectric layer 5. Then, Pt
The upper electrode 6 is formed by sputtering 70 nm and Ti 20 nm at a substrate temperature of 300 ° C.

Next, as shown in FIG. 2C, a photoresist film pattern 16 is provided in the recess 2 and the upper electrode 6 and the dielectric layer 5 are sequentially etched by ion milling. Since the etching rate for ion milling of Ti in the lower electrode 4 is low, the etching can be stopped in the upper Pt / Ti. Thereafter, the photoresist film 16 is treated with oxygen plasma or the like, and then removed with an organic solvent.

[0031] Then, as shown in FIG. 3 (d), a photoresist layer pattern 17 to cover provided to the flat surface of the outer upper of the two digging, etching the lower electrode 4 by ion milling, SiO ₂ insulating film 3 Stop when exposed. After that, the photoresist film 17 is treated with an oxygen plasma or the like and then removed with an organic solvent.

Next, as shown in FIG. 3E, a protective film 14 of SiO ₂ or the like having a thickness of 20
Deposit about 0 nm to cover and protect the capacitor element 10 and the like. Then, as shown in FIG. 3F, a region slightly larger than the processed lower electrode 6 is covered with a photoresist film pattern 18, and the protective film 14 and the insulating film 3 are buffered with hydrofluoric acid.
Is etched to expose the surface of the GaAs semiconductor substrate 1. Since this step is performed by wet etching, no dry etching damage occurs on the substrate surface. After that, the photoresist film 17 is removed with an organic solvent.

Next, as shown in FIG. 4 (g), an Al gate and an FET electrode 13 made of AuGe alloy are formed in the region of the semiconductor element 11 of the FET.
(H) As shown in FIG.
Is deposited to a thickness of about 1 μm, and the surface is flattened by etching back or polishing of a photoresist to form an interlayer insulating film 7.
When the film thickness is reduced, the film is additionally grown and adjusted to a desired film thickness.

Next, a photoresist film pattern 19 is provided, and a through hole 8 is provided by RIE using CF ₄ gas or the like. This RIE operation is set so that the etching is performed by 30% in excess of the thickness of the SiO ₂ film in the flat portion.

Then, Ti 100 nm and Au 200 nm
Is deposited on the entire surface of the substrate by sputtering, a photoresist film pattern is provided, and Au
After the photoresist film is removed, ion milling is performed on the entire surface, and an extra Au / Ti sputter layer is removed to form the wiring 9. Through the above manufacturing steps, the integrated circuit device shown in FIG. 1 is obtained.

When there is no digging as in the conventional example shown in FIG. 6, the upper electrode 6 is 0.6 μm thicker than the lower electrode 4.
Therefore, the interlayer insulating film 7 needs to be thickened to about 1.5 μm in accordance with the height. In this case, etching corresponding to the through hole having the deepest thickness is performed, and the upper electrode 6 having the shallow through hole is excessively etched, and the surface thereof is damaged.

However, according to the manufacturing method of the integrated circuit device of the present embodiment, the height of the lower electrode 4 to be connected and the height of the FET electrode 13 of the semiconductor element 11 are substantially reduced by digging the vicinity of the region of the upper electrode 6 of the capacitor 10. Can be matched. Therefore, it is not necessary to increase the thickness of the interlayer insulating film 7, the depth of the through hole 8 becomes substantially uniform, only the upper electrode 6 is not etched long by RIE, and the dielectric constant decreases and the leakage current decreases. Deterioration such as increase can be suppressed.

The dielectric layer 5 formed by the method of this embodiment is made of a 500 nm-thick SrTiO ₃ film, and has been confirmed to have a relative dielectric constant of 180 and a breakdown voltage of 140 V.

Second Embodiment Next, an integrated circuit device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view schematically illustrating the structure of the integrated circuit device according to the present embodiment. In the first embodiment, the digging 2 is provided in the semiconductor substrate 1. However, in the present embodiment, the digging is provided in the insulating film 3b. Is the same as in the first embodiment.

As shown in FIG. 5, the integrated circuit device according to the present embodiment forms a first insulating film 3a on the surface of a semiconductor substrate 1.
0.3 μm thick SiN etc. by plasma vapor deposition
And extent deposition thickness was 0.5μm about depositing SiO ₂ of more plasma vapor deposition as a second insulating film 3b, a second insulating film 3b is opened by utilizing the selectivity of etching of the insulating film, the first Etching is stopped when the insulating film 3a is exposed.

Thereafter, similar to the first embodiment,
Insulating film 3 made of SiO ₂ , Ti 20 nm, Pt 70 n
m, lower electrode 4 made of Ti 20 nm, Pt 70 nm,
Dielectric layer 5 of SrTiO ₃ , Pt 70 nm, Ti
An upper electrode 6 of 20 nm, a protective film 14 of SiO ₂ or the like are formed in a predetermined shape, SiO is deposited to a thickness of about 1 μm, and the surface is flattened to form an interlayer insulating film 7. After that, a through hole 8 is provided in the interlayer insulating film 7 and a wiring 9 is formed to obtain the integrated circuit device shown in FIG.

As described above, the upper electrode 6 of the capacitor 10
By digging in the vicinity of the region, the height of the lower electrode 4 to be connected or the height of the electrode of the semiconductor element 11 can be substantially matched. Therefore, the thickness of the interlayer insulating film 7 does not need to be increased, and the depth of the through hole 8 can be made substantially uniform. Therefore, only the upper electrode 6 is not etched long by the RIE process, and the dielectric constant decreases and the leak current increases. Degradation can be suppressed.

[0043] In the above first and second embodiments, an example is described using SrTiO ₃ as a dielectric layer, the present invention is not limited to the above embodiments, BaTiO ₃ , Ba _0.5 Sr _0.5 TiO ₃ , PbZr
Similar effects can be obtained by using a high dielectric constant film such as TiO ₃ . Although the upper and lower electrodes of the capacitor were mainly made of Pt, metals such as Ir and Ta, IrO ₂ , SrRuO ₃ and Pb
It may include a layer of a conductive oxide such as TiO ₃ . Furthermore, although the substrate has been described as a GaAs semiconductor, it is apparent that a general substrate such as a Si semiconductor, ceramic, or glass may be used.

[0044]

As described above, according to the structure of the integrated circuit device of the present invention, the thickness of the interlayer insulating film can be reduced, so that the depths of the through holes to the respective electrodes can be made uniform, and the capacitor can be formed. Therefore, since the influence of dry etching can be suppressed, deterioration such as a decrease in dielectric constant and an increase in leak current can be suppressed. This is because, before forming the dielectric layer of the capacitor, the substrate or the insulating layer is dug to prevent the capacitor portion from protruding.

[Brief description of the drawings]

FIG. 1 is a sectional view schematically showing a structure of an integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view showing a method of manufacturing an integrated circuit device according to a first example of the present invention in the order of processes.

FIG. 3 is a process cross-sectional view showing a method of manufacturing the integrated circuit device according to the first embodiment of the present invention in the order of processes.

FIG. 4 is a process sectional view showing a method of manufacturing the integrated circuit device according to the first example of the present invention in the order of processes.

FIG. 5 is a sectional view schematically showing a structure of an integrated circuit device according to a second embodiment of the present invention.

FIG. 6 is a process cross-sectional view showing a method for manufacturing the semiconductor device of Conventional Example 1 in process order.

FIG. 7 is a cross-sectional view of a semiconductor device of Conventional Example 2.

FIG. 8 is a cross-sectional view of a semiconductor device of Conventional Example 3.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Digging 3 Insulating film 3a 1st insulating film 3b 2nd insulating film 4 Lower electrode 5 Dielectric layer 6 Upper electrode 7 Process insulating film 8 Through hole 9 Wiring 10 Capacitor element 11 Semiconductor element 12 FET active layer area 13 FET electrode 14 Protective film 15 to 19 Photoresist film 21 Semiconductor substrate 22 Insulating film 23 Lower electrode 24 Dielectric layer 25 Upper electrode 26 Protective film 27 Process insulating film 28 Semiconductor element 31 Semiconductor substrate 32 Element isolation oxide film 33 Impurity diffusion layer 34 Insulation Film 35 word line 36 insulating film 37 bit line 38 interlayer insulating film 39 contact plug 40 barrier metal 41 lower electrode 42 dielectric layer 43 upper electrode 44 planarization insulating film 45 polishing stopper 51 semiconductor substrate 52 element isolation oxide film 53 n ⁺ Drain diffusion layer 54 n ⁺ Source diffusion layer 55 Silicon oxide film 56 Insulation film 57 Gate electrode 58 Insulation film 59 Connection electrode 60 n ⁺ Diffusion layer (plate electrode) 61 Capacitance insulation film 62 Storage electrode 63 a, 63 b Trench 64 Silicon oxide film 65 p ⁺ Inversion prevention layer 66 digit line

Claims (7)

[Claims] 1. A substrate or an insulating film provided on the substrate has a recess having a flat bottom and a predetermined depth, and a lower electrode is formed so as to project upward from the bottom of the recess. An integrated circuit device, wherein a dielectric layer and an upper electrode are formed on the lower electrode in a flat region at the bottom, away from corners and side walls of the depression. 2. A substrate or an insulating film provided on the substrate, wherein the bottom has a flat recess having a predetermined depth, and a lower electrode is formed so as to project upward from the bottom of the recess. A dielectric layer and an upper electrode are formed apart from the corners and side walls of the depression on the lower electrode in the flat region at the bottom to form a capacitive element, and at least an insulating film covering the capacitive element, An integrated circuit device, wherein a through-hole penetrating to each of the lower electrode and the upper electrode protruding above the depression is formed. 3. The integrated circuit device according to claim 1, wherein a predetermined depth of the depression is set to be substantially equal to a thickness of the dielectric layer and the upper electrode. . 4. The integrated circuit device according to claim 1, wherein the dielectric layer is a film that maintains crystallinity in a predetermined crystal orientation. 5. A step of: (a) forming a recess having a flat bottom at a predetermined depth in a substrate or an insulating film provided on the substrate; and (b) forming a lower electrode on the substrate or the insulating film. Depositing a dielectric layer and an upper electrode in this order; and (c) depositing the upper electrode and the dielectric so that the upper electrode and the dielectric layer remain on a flat region at the bottom of the recess. And (d) etching the lower electrode such that the lower electrode remains from the bottom of the depression to a predetermined region outside the depression. Of manufacturing an integrated circuit device. 6. A step of: (a) forming a recess having a flat bottom at a predetermined depth in a substrate or a first insulating film provided on an upper layer of the substrate; and (b) forming the recess in the substrate or the first insulating film. Depositing a lower electrode, a dielectric layer, and an upper electrode in this order on the film; and (c) removing the upper electrode and the dielectric layer so that the upper electrode and the dielectric layer remain on a flat region at the bottom of the depression. Etching the upper electrode and the dielectric layer; and (d) etching the lower electrode such that the lower electrode remains from the bottom of the depression to a predetermined region outside the depression. e) depositing a second insulating film so as to cover the lower electrode, the dielectric layer, and the upper electrode, and then planarizing the second insulating film; and (f) the second insulating film. Each of the lower electrode and the upper electrode protruding above the depression is provided on the film. Method of manufacturing an integrated circuit device characterized in that it comprises a step of forming a through hole penetrating at least. 7. The integrated circuit device according to claim 5, wherein a predetermined depth of the depression is set to be substantially equal to a thickness of the dielectric layer and the upper electrode. Manufacturing method.